Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay
1Features
1
•Qualified for Automotive Applications
•AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: -40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
•Power-On-Reset (POR) Generator with Adjustable
Delay Time: 25 μs to 30 s
•Very Low Supply Current: 2.1 μA (Typical)
•High Threshold Accuracy: 1% (max)
•Precision Hysteresis
•Fixed and Adjustable Threshold Voltages:
– Fixed Thresholds for Standard Rails:
1.2 V to 5 V
– Adjustable Down to 1.15 V
•Manual Reset (MR) Input
•Open-Drain RESET Output
•Temperature Range: –40°C to +125°C
•Package: 1.5-mm × 1.5-mm WSON
2Applications
•Infotainment Head Unit
•Hybrid/Digital Cluster
•External Amplifier
•ADAS Camera
•Automotive Gateway
Typical Application Circuit
3Description
The TPS3890-Q1 is a precision voltage supervisor
with low-quiescent current that monitors system
voltages as low as 1.15 V, asserting an open-drain
RESET signal when the SENSE voltage drops below
a preset threshold or when the manual reset (MR) pin
drops to a logic low. The RESET output remains low
for the user-adjustable delay time after the SENSE
voltage and manual reset (MR) return above the
respective thresholds. The TPS3890-Q1 family uses
a precision reference to achieve 1% threshold
accuracy. The reset delay time can be user-adjusted
between 25 μs and 30 s by connecting the CT pin to
an external capacitor. The TPS3890-Q1 has a very
low quiescent current of 2.1 μA and is available in a
small 1.5-mm × 1.5-mm package, making the device
well-suitedforbattery-poweredandspaceconstrained applications. The device is fully specified
over a temperature range of –40°C to +125°C (TJ).
Device Information
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS3890-Q1WSON (6)1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
SPACE
SPACE
SPACE
SPACE
SPACE
SPACE
V
Accuracy vs Temperature
ITN
(1)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Changes from Revision A (October 2017) to Revision BPage
•Added Automotive features ................................................................................................................................................... 1
•Added new voltage options to Device Comparison Table...................................................................................................... 3
Changes from Original (March 2017) to Revision APage
•Added TPS389050L-Q1 to Device Comparison Table .......................................................................................................... 3
PART NUMBERNOMINAL SUPPLY VOLTAGENEGATIVE THRESHOLD (V
TPS389001-Q1Adjustable1.15 V1.157 V
TPS389012-Q11.2 V1.15 V1.157 V
TPS389015-Q11.5 V1.44 V1.449 V
TPS389018-Q11.8 V1.73 V1.740 V
TPS389025-Q12.5 V2.40 V2.414 V
TPS389030-Q13.0 V2.89 V2.907 V
TPS389033-Q13.3 V3.17 V3.189 V
TPS389033G-Q13.3 V3.06 V3.084 V
TPS389033K-Q13.3 V2.93 V2.947 V
TPS389050-Q15.0 V4.80 V4.828 V
TPS389050G-Q15.0 V4.65 V4.677 V
TPS389050L-Q15.0 V4.40 V4.425 V
6Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
)POSITIVE THRESHOLD (V
ITN
ITP
)
Pin Functions
PIN
NO.NAME
1SENSEI
2GND—Ground
3MRIDriving the manual reset pin (MR) low causes RESET to go low (assert).
4VDDISupply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
5CT—
6RESETO
I/ODESCRIPTION
This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the
negative threshold voltage V
positive threshold voltage V
, RESET goes low (asserts). When the voltage on SENSE rises above the
ITN
, RESET goes high (deasserts).
ITP
The CT pin offers a user-adjustable delay time. Connecting this pin to a ground-referenced capacitor sets
the RESET delay time to deassert. t
(sec) = CCT(µF) × 1.07 + 25 µs (nom).
PD(r)
RESET is an open-drain output that is driven to a low-impedance state when either the MR pin is driven to
a logic low or the monitored voltage on the SENSE pin is lower than the negative threshold voltage (V
RESET remains low (asserted) for the delay time period after both MR is set to a logic high and the
SENSE input is above V
. A pullup resistor from 10 kΩ to 1 MΩ should be used on this pin.
over operating junction temperature range (unless otherwise noted)
VDD–0.37
SENSE–0.37
Voltage
RESET–0.37
MR–0.37
V
CT
CurrentRESET–2020mA
Operating junction, T
Temperature
Storage, T
stg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V
(ESD)
Electrostatic discharge
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Human-body model (HBM), per AEC Q100-002
Charged-device model (CDM), per AEC Q100-011±750
(1)
MINMAXUNIT
V
–0.37
J
A
–40125
–40125
°COperating ambient, T
–65150
VALUEUNIT
(1)
±2000
V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
over the operating junction temperature range of –40°C to +125°C (TA= TJ), 1.5 V ≤ VDD≤ 5.5 V, and MR = VDD(unless
otherwise noted); typical values are at VDD= 5.5 V and TJ= 25°C
The TPS3890-Q1 supervisory product family is designed to assert a RESET signal when either the SENSE pin
voltage drops below V
adjustable time after both the manual reset (MR) and SENSE voltages return above their respective thresholds.
8.2 Functional Block Diagram
or the manual reset (MR) is driven low. The RESET output remains asserted for a user-
ITN
8.3 Feature Description
The combination of user-adjustable reset delay time with a broad range of threshold voltages allow these devices
to be used in a wide array of applications. Fixed negative threshold voltages (V
to 3.17 V (see the Device Comparison Table for available options), and the adjustable device can be used to
customize the threshold voltage for other application needs by using an external resistor divider. The CT pin
allows the reset delay to be set between 25 μs and 30 s with the use of an external capacitor.
8.3.1 User-Configurable RESET Delay Time
The rising RESET delay time (t
) can be configured by installing a capacitor connected to the CT pin. The
PD(r)
TPS3890-Q1 uses a CT pin charging current (ICT) of 1.15 µA to help counter the effect of capacitor and boardlevel leakage currents that can be substantial in certain applications. The rising RESET delay time can be set to
any value between 25 µs (no CCTinstalled) and 30 s (CCT= 26 µF).
The capacitor value needed for a given delay time can be calculated using Equation 1:
t
(sec) = CCT× VCT÷ ICT+ t
PD(r)
The slope of Equation 1 is determined by the time that the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged
PD(r)(nom)
through the internal CT pulldown resistor (RCT). When the RESET conditions are cleared, the internal precision
current source is enabled and begins to charge the external capacitor and when the voltage on this capacitor
reaches 1.22 V, RESET is deasserted. Note that in order to minimize the difference between the calculated
RESET delay time and the actual RESET delay time, use a low-leakage type capacitor (such as a ceramic
capacitor) and minimize parasitic board capacitance around this pin.
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and SENSE is above V
the user-defined reset delay. If MR is not controlled externally, then MR must be connected to VDD. Note that if
the logic signal driving MR is not greater than or equal to VDD, then some additional current flows into VDD and
out of MR and the difference is apparent when comparing Figure 8 and Figure 9.
Figure 23 shows how MR can be used to monitor multiple system voltages when only a single CT capacitor is
needed to set the RESET delay time.
, RESET is deasserted after
ITP
8.3.3 RESET Output
RESET remains high (deasserted) as long as SENSE is above the positive threshold (V
signal (MR) is logic high. If SENSE falls below the negative threshold (V
asserted, driving the RESET pin to a low impedance.
When MR is again logic high and SENSE is above V
specified reset delay period (t
state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to
enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled
up to any voltage up to 5.5 V, independent of the device supply voltage. To ensure proper voltage levels, give
some consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, the
output capacitive loading, and the output leakage current (I
8.3.4 SENSE Input
The SENSE input can vary from ground to 5.5 V (7.0 V, absolute maximum), regardless of the device supply
voltage used. The SENSE pin is used to monitor the critical voltage rail. If the voltage on this pin drops below
V
, then RESET is asserted. When the voltage on the SENSE pin exceeds the positive threshold voltage,
ITN
RESET deasserts after the user-defined RESET delay time.
The internal comparator has built-in hysteresis to ensure well-defined RESET assertions and deassertions even
when there are small changes on the voltage rail being monitored.
The TPS3890-Q1 device is relatively immune to short transients on the SENSE pin. Glitch immunity is dependent
on threshold overdrive, as illustrated in Figure 19 for V
cases, for noisy applications good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the
SENSE input to reduce sensitivity to transient voltages on the monitored signal.
Figure 23. Using MR to Monitor Multiple System Voltages
) or if MR is driven low, then RESET is
ITN
, a delay circuit is enabled that holds RESET low for a
). When the reset delay has elapsed, the RESET pin goes to a high-impedance
The adjustable version (TPS389001-Q1) can be used to monitor any voltage rail down to 1.15 V using the circuit
shown in Figure 24.
Figure 24. Using the TPS389001-Q1 to Monitor a User-Defined Threshold Voltage
The target threshold voltage for the monitored supply (V
ITx(MON)
) and the resistor divider values can be calculated
by using Equation 2 and Equation 3, respectively:
V
Equation 3 can be used to calculate either the negative threshold or the positive threshold by replacing V
either V
R
ITx(MON)
ITN
TOTAL
= V
ITx
or V
ITP
= R1+ R
× (1 + R1÷ R2)(2)
with
ITx
, respectively.
2
(3)
Resistors with high values minimize current consumption; however, the input bias current of the device degrades
accuracy if the current through the resistors is too low. Therefore, choosing an R
value so that the current
TOTAL
through the resistor divider is at least 100 times larger than the SENSE input current is simplest. See the
Optimizing Resistor Dividers at a Comparator Input application report for more details on sizing input resistors.
8.3.4.1 Immunity to SENSE Pin Voltage Transients
The TPS3890-Q1 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends
on both transient duration and overdrive (amplitude) of the transient. Overdrive is defined by how much VSENSE
exceeds the specified threshold, and is important to know because the smaller the overdrive, the slower the
response of the outputs (that is, undervoltage and overvoltage). Threshold overdrive is calculated as a percent of
the threshold in question, as shown in Equation 4.
Overdrive = | (V
SENSE
/ V
– 1) × 100% |(4)
ITx
Figure 17 to Figure 20 illustrate the glitch immunity that the TPS3890-Q1 has versus temperature with three
different overdrive voltages. The propagation delay versus overdrive curves (Figure 13 to Figure 16) can be used
to determine how sensitive the TPS3890-Q1 family of devices are across an even wider range of overdrive
voltages.
Table 1 summarizes the various functional modes of the device.
Table 1. Truth Table
V
DD
VDD< V
POR
V
< VDD< V
POR
VDD≥ V
VDD≥ V
VDD≥ V
(1) When VDDfalls below V
DD(MIN)
DD(MIN)
DD(MIN)
DD(MIN)
(1)
, undervoltage-lockout (UVLO) takes effect and RESET is held low until VDDfalls below V
DD(MIN)
MRSENSERESET
——Undefined
——L
L—L
HV
HV
SENSE
SENSE
< V
> V
ITN
ITP
L
H
POR
www.ti.com
.
8.4.1 Normal Operation (VDD> V
When VDDis greater than V
DD(min)
, the RESET signal is determined by the voltage on the SENSE pin and the
DD(min)
)
logic state of MR.
•MR high: when the voltage on VDD is greater than 1.5 V, the RESET signal corresponds to the voltage on
the SENSE pin relative to the threshold voltage.
•MR low: in this mode, RESET is held low regardless of the voltage on the SENSE pin.
8.4.2Above Power-On-Reset But Less Than V
When the voltage on VDD is less than the V
DD(min)
DD(min)(VPOR
voltage, and greater than the power-on-reset voltage (V
< VDD< V
DD(min)
)
POR
the RESET signal is asserted regardless of the voltage on the SENSE pin.
8.4.3 Below Power-On-Reset (VDD< V
When the voltage on VDD is lower thanV
)
POR
, the device does not have enough voltage to internally pull the
POR
asserted output low and RESET is undefined and must not be relied upon for proper device function.
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
A typical application for the TPS389018-Q1 is shown in Figure 25. The TPS389018-Q1 can be used to monitor
the 1.8-V VDD rail required by the TI Delfino™ microprocessor family. The open-drain RESET output of the
TPS389018-Q1 is connected to the XRS input of the microprocessor. A reset event is initiated when the VDD
voltage is less than V
or when MR is driven low by an external source.
ITN
Figure 25. TPS3890-Q1 Monitoring the Supply Voltage for a Delfino Microprocessor
9.2.1 Design Requirements
The TPS3890-Q1 RESET output can be used to drive the reset (XRS) input of a microprocessor. The RESET pin
of the TPS3890-Q1 is pulled high with a 1-MΩ resistor; the reset delay time is controlled by the CT capacitor and
is set depending on the reset requirement times of the microprocessor. During power-up, XRS must remain low
for at least 1 ms after VDD reaches 1.5 V for the C2000™ Delfino family of microprocessors. For 100-MHz
operation, the Delfino TMS320F2833x microcontroller uses a supply voltage of 1.8 V that must be monitored by
the TPS3890-Q1.
9.2.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS389018-Q1 has a negative threshold of 1.73 V and a positive threshold of 1.74 V,
making the device suitable for monitoring a 1.8-V rail. The secondary constraint for this application is the reset
delay time that must be at least 1 ms to allow the Delfino microprocessor enough time to startup up correctly.
Because a minimum time is required, the worst-case scenario is a supervisor with a high CT charging current
(ICT) and a low CT comparator threshold (VCT). For applications with ambient temperatures ranging from –40°C
to +125°C, CCTcan be calculated using I
CT(Max)
, V
, and solving for CCTin Equation 1 such that the
CT(MIN)
minimum capacitance required at the CT pin is 1.149 nF. If standard capacitors with ±20% tolerances are used,
then the CT capacitor must be 1.5 nF or larger to ensure that the 1-ms delay time is met.
A 0.1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice and a 1-MΩ
resistor is used as the RESET pullup resistor to minimize the current consumption when RESET is asserted. The
MR pin can be connected to an external signal if desired or connected to VDD if not used.
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 5.5 V. An
input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device has a 7-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 7 V, additional precautions must be taken.
Table 2 shows how to decode the function of the device based on the part number, with TPS389033G-Q1 used
as an example.
Table 2. Device Naming Convention
DESCRIPTIONNOMENCLATUREVALUE
(high-accuracy supervisor family)
TPS3890
33
(nominal rail voltage to be monitored)
G
(percent below nominal rail voltage for V
Q1
(automotive version)
ITN
)
——
101.0 V
121.2 V
181.8 V
333.3 V
505.0 V
—4%
G7%
K11%
L12%
——
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•Optimizing Resistor Dividers at a Comparator Input
•Sensitivity Analysis for Power Supply Design
•Getting Started With TMS320C28x Digital Signal Controllers
•TPS3890EVM-775 Evaluation Module User Guide
•C2000 Delfino Family of Microprocessors
•TMS320F2833x Digital Signal Controllers (DSCs)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
Delfino, C2000, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
TPS389001QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252N
TPS389012QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252O
TPS389015QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252P
TPS389018QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252Q
TPS389025QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252R
TPS389030QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252S
TPS389033GQDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1257V
TPS389033KQDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1257W
TPS389033QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1252T
TPS389050GQDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1257T
TPS389050LQDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1257U
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
10-Dec-2020
Samples
(4/5)
TPS389050QDSERQ1ACTIVEWSONDSE63000RoHS & GreenNIPDAUAGLevel-1-260C-UNLIM-40 to 1257S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
10-Dec-2020
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max heightDSE0006A
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.25)
4X 0.5
(R0.05) TYP
(0.8)
1
3
PKG
(1.6)
5X (0.7)
6
SYMM
4
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
NON SOLDER MASK
METAL
PADS 4-6
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
SOLDER MASK DETAILS
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
SOLDER MASK
OPENING
PADS 1-3
DEFINED
4220552/A 04/2021
EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max heightDSE0006A
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.25)
4X (0.5)
(R0.05) TYP
PKG
(0.8)
1
3
(1.6)
5X (0.7)
6
SYMM
4
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE