Texas Instruments TPS3870-Q1 Datasheet

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

RESET

VDD

SENSE

MR

CT

GND

RESET

V

CORE

Processor

OV Threshold

Optional

Up to

5.5V

TPS3870Q1

1

Monitor Voltage

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2

3

4

5

6

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TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

TPS3870-Q1 Overvoltage Reset IC With Time Delay and Manual Reset

1 Features

1

• Qualified for automotive applications

• AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C

ambient operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C7B

• Input voltage range: 1.7 V to 5.5 V

• Undervoltage lockout (UVLO): 1.7 V

• Low quiescent current: 7 µA (Max)

• High threshold accuracy:
– ± 0.25% (typical)
– ± 0.7% (–40°C to +125°C)

• Fixed threshold levels
– 50-mV steps from 500 mV to 1.3 V
– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V

• User adjustable voltage threshold levels

• Internal glitch immunity and hysteresis

• Tolerance available from 3% to 7% in 1% steps

• Fixed time delay options: 50 µs, 1 ms, 5 ms, 10
ms, 20 ms, 100 ms, 200 ms

• Programmable time delay option with a single
external capacitor

• Open-drain active low OV monitor

• RESET voltage latching output mode

2 Applications

• Advanced driver assistance system (ADAS)

• Camera

• Sensor fusion

• HEV/EV

• FPGA, ASIC and DSP based systems

Integrated Overvoltage Detection

3 Description

The TPS3870-Q1 device is an integrated overvoltage
(OV) monitor or reset IC in industry’s smallest 6-pin
DSE package. This highly accurate voltage
supervisor is ideal for systems that operate on low­voltage supply rails and have narrow margin supply
tolerances. Low threshold hysteresis prevent false
reset signals when the monitored voltage supply is in
its normal range of operation. Internal glitch immunity
and noise filters further eliminate false resets
resulting from erroneous signals.

The TPS3870-Q1 does not require any external
resistors for setting overvoltage reset thresholds,
which further optimizes overall accuracy, cost,
solution size, and improves reliability for safety
systems. The Capacitor Time (CT) pin is used to
select between the two available reset time delays
designed into each device and also to adjust the
reset time delay by connecting a capacitor. A
separate SENSE input pin and VDD pin allow for the
redundancy sought by high-reliability systems.

This device has a low typical quiescent current
specification of 4.5 µA (typical). The TPS3870-Q1 is
suitable for automotive applications and is qualified
for AEC-Q100 Grade 1.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS3870-Q1 WSON (6) 1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Overvoltage Accuracy Distribution

(1)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD ratings............................................................... 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 6

7.7 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram....................................... 12

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 20

10 Power Supply Recommendations ..................... 22

10.1 Power Supply Guidelines...................................... 22

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................. 22

11.2 Layout Example .................................................... 22

12 Device and Documentation Support................. 23

12.1 Device Nomenclature............................................ 23

12.2 Documentation Support ........................................ 24

12.3 Receiving Notification of Documentation Updates 24

12.4 Support Resources ............................................... 24

12.5 Trademarks........................................................... 24

12.6 Electrostatic Discharge Caution............................ 24

12.7 Glossary................................................................ 24

13 Mechanical, Packaging, and Orderable

Information........................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (July 2019) to Revision A Page

• Advance Information to Production Data release................................................................................................................... 1

2

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5 Device Comparison Table

Table 1 shows the released versions of the TPS3870-Q1, including the nominal overvoltage thresholds. For all

possible voltages, threshold tolerance, time delays, and threshold options, see Table 6. Contact TI sales
representatives or on TI's E2E forum for details and availability of other options; minimum order quantities apply.

Table 1. Device Comparison Table

TIME DELAY (ms)

PART NUMBER V

TPS3870J4080DSERQ1 0.80 V Programmable 10 ms 200 ms 4%
TPS3870J4330DSERQ1 3.30 V Programmable 10 ms 200 ms 4%

MON

CT Pin =

Capacitor

CT Pin =

Open

CT Pin = VDD

THRESHOLD
TOLERANCE

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3

SENSE

VDD

CT RESET

MR

GND

TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

6 Pin Configuration and Functions

PIN

NO. NAME

1 SENSE I

2 VDD I

3 CT I

4 RESET O

5 GND — Ground

6 MR I

I/O DESCRIPTION

Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage
threshold, the RESET pin is driven low. Connect to VDD pin if monitoring VDD supply voltage.

Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.

Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or
leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.

Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (V
pull-up resistor terminated to the desired pull-up voltage.

Manual reset (MR), pull this pin to a logic low (V
deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.

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DSE Package

6-Pin WSON

Top View

Pin Functions

). See the timing diagram in Figure 19 for more details. Connect this pin to a

IT+

) to assert a reset signal . After the MR pin is

MR_L

4

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Voltage V
Voltage V
Voltage V
Voltage V
Voltage V
Current I

Temperature

(2)

(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that TJ= TA.

DD
RESET
CT
SENSE
MR

RESET

Continuous total power dissipation See the Thermal Information
Operating junction temperature, T
Operating free-air temperature, T
Storage temperature, T

stg

7.2 ESD ratings

V

(ESD)

Electrostatic
discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per AEC

Q100-011

(1)

MIN MAX UNIT

–0.3 6 V
–0.3 6 V
–0.3 6 V
–0.3 6 V
–0.3 6 V

±40 mA

J

A

-40 150 °C

-40 150 °C

-65 150 °C

VALUE UNIT

(1)

All pins ±500

±2000

V

Corner pins ±750

7.3 Recommended Operating Conditions

V

DD

V

SENSE

V

CT

V

RESET

V

MR

I

RESET

T

J

(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.
(2) The maximum rating is VDDor 5.5 V, whichever is smaller.
(3) If the logic signal driving MR is less than VDD, then additional current flows into VDDand out of MR.

Supply pin voltage 1.7 5.5 V
Input pin voltage 0 5.5 V
CT pin voltage

(1) (2)

Output pin voltage 0 5.5 V
MR pin Voltage

(3)

Output pin current 0.3 10 mA
Junction temperature (free-air temperature) -40 125 ℃

MIN NOM MAX UNIT

V

DD

V

0 5.5 V

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SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

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7.4 Thermal Information

TPS3870-Q1

THERMAL METRIC

(1)

UNITDSE (WSON)

PINS

R

θJA

R

θJC(top)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 184.2 °C/W
Junction-to-case (top) thermal resistance 30.6 °C/W
Junction-to-board thermal resistance 86.4 °C/W
Junction-to-top characterization parameter 13.4 °C/W
Junction-to-board characterization parameter 86.1 °C/W
Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

At 1.7 V ≤ VDD≤ 5.5 V, CT = MR = Open, RESET Voltage (V
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD= 3.3 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

DD

UVLO Under Voltage Lockout
V

POR

V

IT+(OV)

V

HYS

I

DD

I

SENSE

V

OL

I

LKG

V

MR_L

V

MR_H

V

CT_H

R

MR

I

CT

V

CT

(1) RESET pin is driven low when VDDfalls below UVLO.
(2) V

POR

(3) Hysteresis is with respect of the trip point (V
(4) VCTvoltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.

Supply Voltage 1.7 5.5 V

Power on reset voltage

(1)

(2)

VDDfalling below 1.7 V 1.2 1.7 V

VOL(max) = 0.25 V, I
Positive- going threshold accuracy -0.7 ±0.25 0.7 %
Hysteresis Voltage

(3)

Supply current VDD≤ 5.5 V 4.5 7 µA
Input current, SENSE pin V

= 5 V 1 1.5 µA

SENSE

VDD= 1.7 V, I
Low level output voltage

VDD= 2 V, I

VDD= 5 V, I
Open drain output leakage current VDD= V

RESET

MR logic low input 0.3 V
MR logic high input 1.4 V
High level CT pin voltage 1.4 V
Manual reset Internal pullup resistance 100 KΩ
CT pin charge current 337 375 413 nA
CT pin comparator threshold voltage

(4)

is the minimum VDDvoltage level for a controlled output state.

)

IT+(OV)

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

= 15 µA 1 V

OUT

0.3 0.55 0.8 %

= 0.4 mA 250 mV

OUT

= 3 mA 250 mV

OUT

= 5 mA 250 mV

OUT

= 5.5 V 300 nA

1.133 1.15 1.167 V

7.6 Timing Requirements

At 1.7 V ≤ VDD≤ 5.5 V, CT = MR = Open, RESET Voltage (V
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD= 3.3 V.

t

D

t

D

t

D

t

D

t

D

t

D

6

Reset time delay, TPS3870J CT = Open 7 10 13 ms
Reset time delay, TPS3870J CT = 10 kΩ to V
Reset time delay, TPS3870K CT = Open 0.7 1 1.3 ms
Reset time delay, TPS3870K CT = 10 kΩ to V
Reset time delay, TPS3870L CT = Open 3.5 5 6.5 ms
Reset time delay, TPS3870L CT = 10 kΩ to V

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) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

MIN NOM MAX UNIT

DD

DD

DD

140 200 260 ms

14 20 26 ms

70 100 130 ms

All percentages are calculated with respect to typical V

IT

Tolerance[+3% to +7%]

[ -1.5% = -0.7%-0.8%) ]

0.5%

[ -1.0% = -0.7%-0.3%) ]

[ -1.25% = -0.7%-0.55%) ]

VIT

+(OV)

[0.55%]

[-0.25%]

[0.25%]

[-0.7%]

V

IT+(OV)

- V

HYS

[-0.8%]

[-0.3%]

[-0.55%]

Hys band for V

IT+(OV)

[0.7%]

[0.55%]

[0.55%]

[ -0.1% = 0.7%-0.8%) ]

0.5%

[ 0.4% = 0.7%-0.3%) ]

[ 0.15% = 0.7%-0.55%) ]

Overdrive[2.5%] above V

IT+(OV)

Accuracy at 25ºC

Accuracy across (-40ºC to 125ºC)

Nominal monitored voltage

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Timing Requirements (continued)

TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

At 1.7 V ≤ VDD≤ 5.5 V, CT = MR = Open, RESET Voltage (V

) = 10 kΩ to VDD, RESET load = 10 pF, and over the

RESET

operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ= 25°C, typical
conditions at VDD= 3.3 V.

MIN NOM MAX UNIT

t

D

t

PD

t

R

t

F

t

SD

t

GI (VIT+)

t

GI (MR)

t

PD (MR)

t

MR_W

t

D (MR)

(1) 5% Overdrive from threshold. Overdrive % = [V
(2) tPDmeasured from threshold trip point V
(3) Output transitions from VOLto 90% for rise times and 90% to VOLfor fall times.
(4) During the power-on sequence, VDDmust be at or above V

Reset time delay, TPS3870M
Propagation detect delay

Output rise time
Output fall time
Startup delay

(1)(3)

(1)(3)

(4)

Glitch Immunity overvoltage V

(1)(2)

, 5% Overdrive

IT+(OV)

(1)

Glitch Immunity MR pin 25 ns
Propagation delay from MR low to assert RESET 500 ns
MR pin pulse width duration to assert RESET 1 µs
MR reset time delay t

SENSE

to RESET VOLvoltage

IT+(OV)

- V

IT+(OV)

DD (MIN)

] / V

CT = 10 kΩ to V
CT = Open

IT+(OV)

for at least tSD+ tDbefore the output is in the correct state.

DD

50 µs
15 30 µs

2.2 µs

0.2 µs

300 µs

3.5 µs

D

ms

Figure 1. Voltage Threshold and Hysteresis Accuracy

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t

D

Hysteresis

V

DD(MIN)

V

POR

UVLO

RESET

t

PD

Undefined

SENSE

V

DD

V

IT+(OV)

V

IT+(OV)

- V

HYS

t

D

t

SD

TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

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(1) VDD= 2 V, RPU= 10 kΩ to V

DD

(2) Variant M (time delay bypass) has a ~40 µs pulse at RESET pin during power up window, this is present only when

the power cycle off time is longer than 10 seconds, this behavior will not occur if SENSE pin is within window of
operation during VDDpower up.

Figure 2. SENSE Timing Diagram

8

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Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

D008

VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V

Overdrive (%)

SENSE Glitch Immunity (Ps)

0 5 10 15 20 25 30 35 40 45 50 55

9

10

11

12

13

14

15

16

D010

-40qC
25qC
125qC

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

0.5

0.52

0.54

0.56

0.58

0.6

D006

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

Temperature (qC)

Supply Current (PA)

-50 -25 0 25 50 75 100 125

2

3

4

5

6

7

D007

VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V

Temperature (qC)

Accuracy (%)

-50 -25 0 25 50 75 100 125

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

D002

0.8 V

1.2 V

1.8 V

3.3 V

5.0 V

V

IT+(OV)

Accuracy (%)

Frequency (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

0

5

10

15

20

25

30

35

D004

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7.7 Typical Characteristics

At TJ= 25°C, VDD= 3.3 V, and RPU= 10 kΩ, unless otherwise noted.

Tested across multiple voltage options

Figure 3. Overvoltage Accuracy vs Temperature Figure 4. Overvoltage Accuracy Distribution

TPS3870-Q1

SNVSBI5A –JULY 2019–REVISED SEPTEMBER 2019

Tested across multiple voltage options

Figure 5. Overvoltage Hysteresis Voltage Accuracy vs

Temperature

Output (RESET Pin) = Low

Figure 7. Supply Current vs Temperature

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Output (RESET Pin) = High

Figure 6. Supply Current vs Temperature

VDD = 1.7 V

Figure 8. SENSE Glitch Immunity (VIT+) vs Overdrive

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9