TPS3852-Q1 High-Accuracy Voltage Supervisor with Integrated Watchdog Timer
1Features
1
•AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
•VDDInput Voltage Range: 1.6 V to 6.5 V
•0.8% Voltage Threshold Accuracy
•Low Supply Current: IDD= 10 µA (typ)
•User-Programmable Watchdog Timeout
•Factory-Programmed Precision Watchdog and
Reset Timers:
– ±15% Accurate WDT and RST Delays
•Open-Drain Outputs
•Manual Reset Input (MR)
•Precision Voltage Monitoring:
– Supports Common Rails from 1.8 V to 5.0 V
– 4% and 7% Thresholds Available
– 0.5% Hysteresis
•Watchdog Disable Feature
•Available in a Small 3-mm × 3-mm, 8-Pin VSON
Package
2Applications
•Safety-Critical Applications
•Automotive Vision Systems
•Automotive ADAS Systems
•Telematics Control Units
•FPGAs and ASICs
•Microcontrollers and DSPs
3Description
The TPS3852-Q1 is a precision voltage supervisor
with an integrated window watchdog timer. The
TPS3852-Q1includesaprecisionundervoltage
supervisor with an undervoltage threshold (V
achieves0.8%accuracyoverthespecified
temperature range of –40°C to +125°C. In addition,
the TPS3852-Q1 includes accurate hysteresis making
the device ideal for use with tight tolerance systems.
The supervisor RESETdelay features a 15%
accuracy, high-precision delay timer.
The TPS3852-Q1 includes a programmable window
watchdog timer for a wide variety of applications. The
dedicated watchdog output (WDO) enables increased
resolution to help determine the nature of fault
conditions.Thewatchdogtimeoutscanbe
programmed either by an external capacitor or by
factory-programmeddefaultdelaysettings.The
watchdog can be disabled to avoid undesired
watchdog timeouts during the development process.
The TPS3852-Q1 is available in a small 3.00-mm ×
3.00-mm, 8-pin VSON package. The TPS3852-Q1
features wettable flanks that allow for easy optical
inspection.
Device Information
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS3852-Q1VSON (8)3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
ITN
) that
Typical Application CircuitUndervoltage Threshold (V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and
CWD2—
GND4—Ground pin
MR3I
RESET8O
SET15ILogic input. Grounding the SET1 pin disables the watchdog timer.
VDD1ISupply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI6I
WDO7O
Thermal pad—Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further
enables the selection of the preset watchdog timeouts; see the Timing Requirements table.
When using a capacitor, the TPS3852-Q1 determines the window watchdog upper boundary with Equation 1.
See Table 4 and the CWD Functionality section for additional information.
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD.
RESET remains low for a fixed reset delay (t
) time after MR is deasserted (high).
RST
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes
low when VDDgoes below the undervoltage threshold (V
RESET timeout counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (V
monitored voltage is within the correct operating range (above V
Watchdog input. A falling transition (edge) must occur at this pin between the lower (t
window boundaries in order for WDO to not assert.
). When VDDis within the normal operating range, the
ITN
). Above POR, RESET goes low and remains low until the
POR
ITN
+ V
) and the RESET timeout is complete.
HYST
) and upper (t
WDL(max)
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored
when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then
WDI cannot be left unconnected and must be driven to either VDD or GND.
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (t
impedance state.
over operating free-air temperature range (unless otherwise noted)
Supply voltage rangeVDD–0.37V
Output voltage rangeRESET, WDO–0.37V
Voltage ranges
Output pin current±20mA
Input current (all pins)±20mA
Continuous total power dissipationSee Thermal Information
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VDD+ 0.3 V or 7.0 V, whichever is smaller.
(3) Assume that TJ= TAas a result of the low dissipated power in this device.
SET1, WDI, MR–0.37
CWD, CRST–0.3VDD+ 0.3
Operating junction, T
Storage, T
stg
(3)
J
(3)
A
(1)
MINMAXUNIT
(2)
V
–40150
–40150
°COperating free-air, T
–65150
6.2 ESD Ratings
VALUEUNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
Charged-device model (CDM), per AEC Q100-011±750
(1)
±2000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at V
+ V
ITN
open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ= 25°C
GENERAL CHARACTERISTICS
(1)
V
DD
I
DD
RESET FUNCTION
(2)
V
POR
(3)
V
UVLO
V
ITN
V
HYST
I
MR
WINDOW WATCHDOG FUNCTION
I
CWD
V
CWD
V
OL
I
D
V
IL
V
IH
V
IL(WDI)
V
IH(WDI)
(1) During power on, VDDmust be a minimum of 1.6 V for at least 300 µs before RESET correlates with VDD.
(2) When VDDfalls below V
(3) When VDDfalls below UVLO, RESET is driven low.
≤ VDD≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ≤ +125°C (unless otherwise noted); the
Low-level input voltage (MR, SET1)0.25V
High-level input voltage (MR, SET1)0.8V
Low-level input voltage (WDI)0.3 × V
High-level input voltage (WDI)0.8 × V