TEXAS INSTRUMENTS TPS3808 Technical data

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1 2 3 4
5
6
DBV PACKAGE
(TOP VIEW)
RESET
GND
MR
V
DD
SENSE CT
1.2V 3.3V
TPS3808G12 TPS3808G33 DSP
SENSE V
DD
V
DD
SENSE
V
I/OVCORE
GPIO
GNDGNDGND
CTCT
RESET
RESET
MR
Low Quiescent Current, Programmable-Delay

FEATURES DESCRIPTION

Power-On Reset Generator with Adjustable
Delay Time: 1.25ms to 10s
Very Low Quiescent Current: 2.4µA typ
High Threshold Accuracy: 0.5% typ
Fixed Threshold Voltages for Standard
Voltage Rails from 0.9V to 5V and Adjustable Voltage Down to 0.4V Are Available
Manual Reset ( MR) Input
Open-Drain RESET Output
Temperature Range: -40 ° C to 125 ° C
Small SOT23 Package

APPLICATIONS

DSP or Microcontroller Applications
Notebook/Desktop Computers
PDAs/Hand-Held Products
Portable/Battery-Powered Products
FPGA/ASIC Applications
Supervisory Circuit
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
The TPS3808xxx family of microprocessor supervis­ory circuits monitor system voltages from 0.4V to
5.0V, asserting an open drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset ( MR) pin drops to a logic low. The RESET output remains low for the user adjust­able delay time after the SENSE voltage and manual reset ( MR) return above their thresholds.
The TPS3808 uses a precision reference to achieve
0.5% threshold accuracy for V delay time can be set to 20ms by disconnecting the CT pin, 300ms by connecting the CT pin to V a resistor, or can be user-adjusted between 1.25ms and 10s by connecting the CT pin to an external capacitor. The TPS3808 has a very low typical quiescent current of 2.4µA so it is well-suited to battery-powered applications. It is available in a small SOT23 package and is fully specified over a tempera­ture range of -40 ° C to +125 ° C.
3.3V. The reset
IT
DD
using
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1. Typical Application Circuit
Copyright © 2004, Texas Instruments Incorporated
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TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT SUPPLY TEMPERATURE TRANSPORT MEDIA,
NOMINAL SPECIFIED
VOLTAGE
TPS380G801 Adjustable 0.405V -40 ° C to +125 ° C AVW
TPS3808G09 0.9V 0.84V -40 ° C to +125 ° C AVV
TPS3808G12 1.2V 1.12V -40 ° C to +125 ° C AVY
TPS3808G15 1.5V 1.40V -40 ° C to +125 ° C AVS
TPS3808G18 1.8V 1.67V -40 ° C to +125 ° C AVR
TPS3808G25 2.5V 2.33V -40 ° C to +125 ° C AVQ
TPS3808G30 3.0V 2.79V -40 ° C to +125 ° C AVP
TPS3808G33 3.3V 3.07V -40 ° C to +125 ° C AVO
TPS3808G50 5.0V 4.65V -40 ° C to +125 ° C AVN
(1) Custom threshold voltages from 0.82V to 3.3V, 4.4V to 5.0V are available on a quick-turn basis for fast prototyping. Minimum order
quantities apply. Contact factory for details and availability.
THRESHOLD PACKAGE ORDERING
(1)
VOLTAGE (V
) MARKING NUMBER
IT
RANGE QUANTITY
TPS3808G01DBVT Tape and Reel, 250 TPS3808G01DBVR Tape and Reel, 3000 TPS3808G09DBVT Tape and Reel, 250 TPS3808G09DBVR Tape and Reel, 3000 TPS3808G12DBVT Tape and Reel, 250 TPS3808G12DBVR Tape and Reel, 3000 TPS3808G15DBVT Tape and Reel, 250 TPS3808G15DBVR Tape and Reel, 3000 TPS3808G18DBVT Tape and Reel, 250 TPS3808G18DBVR Tape and Reel, 3000 TPS3808G25DBVT Tape and Reel, 250 TPS3808G25DBVR Tape and Reel, 3000 TPS3808G30DBVT Tape and Reel, 250 TPS3808G30DBVR Tape and Reel, 3000 TPS3808G33DBVT Tape and Reel, 250 TPS3808G33DBVR Tape and Reel, 3000 TPS3808G50DBVT Tape and Reel, 250 TPS3808G50DBVR Tape and Reel, 3000

ABSOLUTE MAXIMUM RATINGS

over operating junction temperature range (unless otherwise noted)
Input voltage range, V CT voltage range, V Other voltage ranges: V RESET pin current 5 mA Operating junction temperature range, T Storage temperature range, T ESD rating, HBM 2 kV ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that TJ= TA.
2
DD
CT
, VMR, V
RESET
SENSE
(2)
J
STG
(1)
TPS3808 UNIT
-0.3 to 7.0 V
-0.3 to V
-40 to +150 ° C
-65 to +150 ° C
+ 0.3 V
DD
-0.3 to 7 V
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ELECTRICAL CHARACTERISTICS

1.8V V otherwise noted. Typical values are at TJ= 25 ° C.
V
DD
I
DD
V
OL
V
IT
V
hys
R
MR
I
SENSE
I
OH
C
IN
V
IL
V
IH
t
w
t
d
t
pHL
θ
JA
DD
6.5V, R
= 100k , C
LRESET
LRESET
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input supply range 1.8 6.5 V
Supply current (current into V
pin)
DD
Low-level output voltage
Power-up reset voltage
(1)
TPS3808G01 -2.0 ± 1.0 +2.0
Negative-going
VIT≤ 3.3V -1.5 ± 0.5 +1.5
input threshold 3.3V < VIT≤ 5.0V -2.0 ± 1.0 +2.0 % accuracy
VIT≤ 3.3V -40 ° C < TJ< +85 ° C -1.25 ± 0.5 +1.25
3.3V < VIT≤ 5.0V -40 ° C < TJ< +85 ° C -1.5 ± 0.5 +1.5
Hysteresis on VITpin %V
TPS3808G01 1.5 3.0 Fixed versions 1.0 2.5
MR Internal pull-up re­sistance
Input current at SENSE pin
TPS3808G01 V Fixed versions V
RESET leakage current V Input capacitance, any
pin
CT pin VIN= 0V to V
Other pins VIN= 0V to 6.5V 5 MR logic low input 0.3 V MR logic high input 0.7 V
Maximum transient duration
SENSE VIH= 1.05V
MR VIH= 0.7V
CT = Open 12 20 28 ms
CT = V RESET delay time See timing diagram
DD
CT = 100pF 0.75 1.25 1.75 ms
CT = 180nF 0.7 1.2 1.7 s Propagation delay MR to RESET VIH= 0.7V High to low level RESET
delay
SENSE to RESET VIH= 1.05V Thermal resistance,
junction-to-ambient
= 50pF, over operating temperature range (T
V
= 3.3V, RESET not asserted
DD
MR, RESET, CT open V
= 6.5V, RESET not asserted
DD
MR, RESET, CT open
1.3V V
1.8V V V
OL
SENSE SENSE RESET
< 1.8V, IOL= 0.4mA 0.3 V
DD
6.5V, IOL= 1.0mA 0.4 V
DD
(max) = 0.2V, I
= V
IT
= 15µA 0.8 V
RESET
= 6.5V 1.7 µA = 6.5V, RESET not asserted 300 nA
DD
, VIL= 0.95V
IT
, VIL= 0.3V
DD
, VIL= 0.3V
DD
, VIL= 0.95V
IT
IT
DD
DD
IT
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
= -40 ° C to +125 ° C), unless
J
2.4 5.0 µA
2.7 6.0 µA
70 90 k
-25 25 nA
5
DD
DD
20
0.001
180 300 420 ms
150 ns
20 µs
290 ° C/W
IT
pF
V
µs
(1) The lowest supply voltage (V
) at which RESET becomes active. T
DD
15µs/V.
rise(VDD)
3
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Adjustable Voltage Version
Fixed Voltage Version
Reset
Logic
Timer
90k
V
DD
V
DD
GND
0.4V
V
REF
SENSE
CT
TPS3808G01
Adjustable Voltage
Reset
Logic
Timer
90k
V
DD
V
DD
GND
0.4V V
REF
SENSE
CT
R
1
R
2
R
1
+ R
2
= 4M
MR
MR
RESET RESET
+ +
DBV PACKAGE
SOT23
(TOP VIEW)
1
2
3 4
5
RESET
GND
MR
SENSE
V
DD
CT
6
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
FUNCTIONAL BLOCK DIAGRAMS
Figure 2. Adjustable and Fixed Voltage Versions
NAME
RESET 1 RESET is an open drain output that is driven to a low impedance state when RESET is asserted (either the
GND 2 Ground MR 3 Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to V CT 4 Reset period programming pin. Connecting this pin to V
SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
V
DD
4
TERMINAL
SOT23 (DBV)
PIN NO.

PIN ASSIGNMENTS

TERMINAL FUNCTIONS
DESCRIPTION
SENSE input is lower than the threshold voltage (V low (asserted) for the reset period after both SENSE is above VITand MR is set to a logic high. A pull-up resistor from 10k to 1M should be used on this pin, and allows the reset pin to attain voltages higher than VDD.
results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor 100pF gives a user-programmable delay time. See Selecting The Reset Delay Time in the Device Operation section for more information.
voltage VIT, then RESET is asserted.
6 Supply voltage. It is good analog design practice to place a 0.1µF ceramic capacitor close to this pin.
) or the MR pin is set to a logic low). RESET will remain
IT
through a 40k to 200k resistor or leaving it open
DD
by a 90k pull-up resistor.
DD
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Time
0.8V
0.0V
V
IT
+ V
HYS
V
IT
0.7V
DD
0.3V
DD
MR
SENSE
RESET
VDD
t
D
t
D
t
D
tD= Reset Delay
= Undefined State
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
TIMING DIAGRAM
Figure 3. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing

TRUTH TABLE

MR SENSE > V
L 0 L
L 1 L H 0 L H 1 H
IT
RESET
5
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0 1 2 3 4 5 6 7
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5 0
40
C
+25C
+85C
+125C
I
DD
(µA)
VDD (V)
100
10
1
0.1
0.01
0.001
0.0001 0.001 0.01 0.1 C
T
(µF)
101
−40°C, +25°C, +125°C
RESET Timeout (sec)
10
8 6 4 2 0
10 30 50 70 90 110 130
Temperature (°C)
−50 −30 −10
−10
−8
−6
−4
−2
Normalized RESET Timeout Period (%)
100
10
1
0 5 10 15 20 30 35 4525
Overdrive (%V
IT
)
5040
Transient Duration below V
IT
(µs)
RESET OCCURS
ABOVE THE CURVE
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

V
= 3.3V, TJ= 25 ° C, R
DD
= 100k , C
LRESET
= 50pF
LRESET
SUPPLY CURRENT RESET TIMEOUT PERIOD
vs vs
SUPPLY VOLTAGE C
Figure 4. Figure 5.
NORMALIZED RESET TIMEOUT PERIOD
vs MAXIMUM TRANSIENT DURATION AT SENSE
TEMPERATURE vs
(C
= OPEN, CT= VDD, CT= Any) SENSE THRESHOLD OVERDRIVE VOLTAGE
T
T
6
Figure 6. Figure 7.
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4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
V
OL
Low−Level RESET Voltage (V)
VDD= 1.8V
RESET
Current (mA)
1.0
0.8
0.6
0.4
0.2 0
10 30 50 70 90 110 130
Temperature (°C)
−50 −30 −10
−1.0
−0.8
−0.6
−0.4
−0.2
Normalized V
IT
(%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1 0
V
OL
Low−Level RESET Voltage (V)
RESET Current (mA)
VDD= 3.3V
VDD= 6.5V
TYPICAL CHARACTERISTICS (continued)
V
= 3.3V, TJ= 25 ° C, R
DD
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
= 100k , C
LRESET
= 50pF
LRESET
NORMALIZED SENSE THRESHOLD VOLTAGE (V
vs vs
TEMPERATURE RESET CURRENT
Figure 8. Figure 9.
) LOW-LEVEL RESET VOLTAGE
IT
LOW-LEVEL RESET VOLTAGE
vs
RESET CURRENT
Figure 10.
7
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V
I
TPS3808G01
V
DD
SENSE
GND
RESET
R
1
R
2
1nF
V
IT
1
R
1
R
2
0.405
2.5V
V
DD
SENSE
V
DDSHV 1, 3, 6, 7,9
GNDGND
CT
RESET
MR
1M
TPS3808G25
RESPWRON
OMAP1510
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004

DEVICE OPERATION

The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below V manual reset ( MR) is driven low. The RESET output remains asserted for a user-adjustable time after both the manual reset ( MR) and SENSE voltages return above their thresholds. A broad range of voltage threshold and reset delay time adjustments are avail­able, allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set from 0.82V to 3.3V or from 4.4V to 5.0V, while the TPS3808G01 can be set to any voltage above 0.405V using an external resistor divider. Two preset delay times are also user-selectable: con­necting the CT pin to V
results in a 300ms reset
DD
delay, while leaving the CT pin open yields a 20ms reset delay. In addition, connecting a capacitor be­tween CT and GND allows the designer to select any reset delay period from 1.25ms to 10s.
IT
supply line can be used to allow the reset signal for the microprocessor to have a voltage higher than V
or the
(up to 6.5V). The pull-up resistor should be no smaller than 10k as a result of the finite impedance
DD
of the RESET line.

SENSE INPUT

The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin drops below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET assertions and de-assertions. It is good analog design practice to put a 1nF to 10nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808G01 can be used to monitor any voltage rail down to 0.405V using the circuit shown in Figure 12 .

RESET OUTPUT

A typical application of the TPS3808G25 used with the OMAP1510 processor is shown in Figure 11 . The open drain RESET output is typically connected to the RESET input of a microprocessor. A pull-up resistor must be used to hold this line high when RESET is not asserted. The RESET output is unde­fined for voltage below 0.8V, but this is normally not a problem since most microprocessors do not function below this voltage. RESET remains high (unasserted) as long as SENSE is above its threshold (V manual reset ( MR) is logic high. If either SENSE falls below V driving the RESET pin to a low impedance.
Figure 11. Typical Application of the TPS3808
Once MR is again logic high and SENSE is above V + V enabled which holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pull-up resistor from the open drain RESET to the
8
or MR is driven low, RESET is asserted,
IT
with an OMAP Processor
(the threshold hysteresis), a delay circuit is
hys
) and the
IT
Figure 12. Using the TPS3808G01 to Monitor a
User-Defined Threshold Voltage

MANUAL RESET ( MR) INPUT

The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3V returns to a logic high and SENSE is above its reset threshold, RESET is de-asserted after the user de­fined reset delay expires. Note that MR is internally tied to V unconnected if MR will not be used.
Figure 13 shows how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to V some additional current draw into V
IT
the internal pull-up resistor on MR. To minimize current draw, a logic-level FET can be used as shown in Figure 14 .
) on MR causes RESET to assert. After MR
DD
using a 90k resistor so this pin can be left
DD
, there will be
DD
as a result of
DD
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CT(nF) tD(s)0.5 103(s) 175
1.2V 3.3V
TPS3808G12 TPS3808G33 DSP
SENSE V
DD
V
DD
SENSE
V
I/OVCORE
GPIO
GNDGNDGND
CTCT
RESET
RESET
MR
1M
3.3V
V
DD
SENSE
90k
GND
RESET
MR
Signal
MR
TPS3808xxx
Delay (s) = CT (nF) + 0.5 · 10−3 (s)
RESET
3.3V
TPS3808G33
V
DD
SENSE
CT
50k
3.3V
TPS3808G33
V
DD
SENSE
CT
3.3V
TPS3808G33
V
DD
SENSE
CT RESET
20ms Delay
300ms Delay
(c)
RESET
(b)
(a)
175
C
T
Figure 13. Using MR to Monitor Multiple System
Voltages
TPS3808
SBVS050B – MAY 2004 – REVISED OCTOBER 2004
by the choice of resistor. Figure 15 b shows a fixed 20ms delay time by leaving the CT pin open. Fig­ure 15 c shows a ground referenced capacitor con­nected to CT for a user-defined program time be­tween 1.25ms and 10s.
The capacitor CT should be 100pF nominal value in order for the TPS3808xxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using the following equation:
(1)
The reset delay time is determined by the time it takes an on-chip precision 220nA current source to charge the external capacitor to 1.23V. When a RESET is asserted the capacitor is discharged. When the RESET conditions are cleared, the internal cur­rent source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23V, RESET is de-asserted. Note that a low leakage type capacitor such as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay time.
Figure 14. Using an External MOSFET to Minimize
IDDWhen MR Signal Does Not Go to V
DD

SELECTING THE RESET DELAY TIME

The TPS3808 has three options for setting the RESET delay time as shown in Figure 15 . Figure 15 a shows the configuration for a fixed 300ms typical delay time by tying CT to V 200k must be used. Supply current is not affected
; a resistor from 40k to
DD

IMMUNITY TO SENSE PIN VOLTAGE TRANSIENTS

The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent on threshold overdrive, as shown in the
Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage graph in the Typical
Characteristics section.
Figure 15. Configuration Used to Set the RESET Delay Time
9
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
TPS3808G01DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G01DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G01DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G01DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G09DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G09DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G12DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G12DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G15DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G18DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G18DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G18DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G18DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G25DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G25DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G25DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G25DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
TPS3808G30DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
TPS3808G30DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
26-Apr-2005
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
(2)
TPS3808G30DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
26-Apr-2005
(3)
no Sb/Br)
TPS3808G30DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G50DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G50DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS3808G50DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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