TEXAS INSTRUMENTS TPS3808 Technical data

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1
2
3 4

5

6

DBV PACKAGE

SOT23

(TOP VIEW)

RESET

GND

MR

V

DD

SENSE
CT

1.2V 3.3V

TPS3808G12 TPS3808G33 DSP

SENSE V

DD

V

DD

SENSE

V

I/OVCORE

GPIO

GNDGNDGND

CTCT

RESET

RESET

MR

Low Quiescent Current, Programmable-Delay

FEATURES DESCRIPTION

• Power-On Reset Generator with Adjustable

Delay Time: 1.25ms to 10s

• Very Low Quiescent Current: 2.4µA typ

• High Threshold Accuracy: 0.5% typ

• Fixed Threshold Voltages for Standard

Voltage Rails from 0.9V to 5V and Adjustable
Voltage Down to 0.4V Are Available

• Manual Reset ( MR) Input

• Open-Drain RESET Output

• Temperature Range: -40 ° C to 125 ° C

• Small SOT23 Package

APPLICATIONS

• DSP or Microcontroller Applications

• Notebook/Desktop Computers

• PDAs/Hand-Held Products

• Portable/Battery-Powered Products

• FPGA/ASIC Applications

Supervisory Circuit

TPS3808

SBVS050B – MAY 2004 – REVISED OCTOBER 2004

The TPS3808xxx family of microprocessor supervis­ory circuits monitor system voltages from 0.4V to

5.0V, asserting an open drain RESET signal when
the SENSE voltage drops below a preset threshold or
when the manual reset ( MR) pin drops to a logic low.
The RESET output remains low for the user adjust­able delay time after the SENSE voltage and manual
reset ( MR) return above their thresholds.

The TPS3808 uses a precision reference to achieve

0.5% threshold accuracy for V
delay time can be set to 20ms by disconnecting the
CT pin, 300ms by connecting the CT pin to V
a resistor, or can be user-adjusted between 1.25ms
and 10s by connecting the CT pin to an external
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4µA so it is well-suited to
battery-powered applications. It is available in a small
SOT23 package and is fully specified over a tempera­ture range of -40 ° C to +125 ° C.

≤ 3.3V. The reset

IT

DD

using

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Typical Application Circuit

Copyright © 2004, Texas Instruments Incorporated

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TPS3808

SBVS050B – MAY 2004 – REVISED OCTOBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

PRODUCT SUPPLY TEMPERATURE TRANSPORT MEDIA,

NOMINAL SPECIFIED

VOLTAGE

TPS380G801 Adjustable 0.405V -40 ° C to +125 ° C AVW

TPS3808G09 0.9V 0.84V -40 ° C to +125 ° C AVV

TPS3808G12 1.2V 1.12V -40 ° C to +125 ° C AVY

TPS3808G15 1.5V 1.40V -40 ° C to +125 ° C AVS

TPS3808G18 1.8V 1.67V -40 ° C to +125 ° C AVR

TPS3808G25 2.5V 2.33V -40 ° C to +125 ° C AVQ

TPS3808G30 3.0V 2.79V -40 ° C to +125 ° C AVP

TPS3808G33 3.3V 3.07V -40 ° C to +125 ° C AVO

TPS3808G50 5.0V 4.65V -40 ° C to +125 ° C AVN

(1) Custom threshold voltages from 0.82V to 3.3V, 4.4V to 5.0V are available on a quick-turn basis for fast prototyping. Minimum order

quantities apply. Contact factory for details and availability.

THRESHOLD PACKAGE ORDERING

(1)

VOLTAGE (V

) MARKING NUMBER

IT

RANGE QUANTITY

TPS3808G01DBVT Tape and Reel, 250
TPS3808G01DBVR Tape and Reel, 3000
TPS3808G09DBVT Tape and Reel, 250
TPS3808G09DBVR Tape and Reel, 3000
TPS3808G12DBVT Tape and Reel, 250
TPS3808G12DBVR Tape and Reel, 3000
TPS3808G15DBVT Tape and Reel, 250
TPS3808G15DBVR Tape and Reel, 3000
TPS3808G18DBVT Tape and Reel, 250
TPS3808G18DBVR Tape and Reel, 3000
TPS3808G25DBVT Tape and Reel, 250
TPS3808G25DBVR Tape and Reel, 3000
TPS3808G30DBVT Tape and Reel, 250
TPS3808G30DBVR Tape and Reel, 3000
TPS3808G33DBVT Tape and Reel, 250
TPS3808G33DBVR Tape and Reel, 3000
TPS3808G50DBVT Tape and Reel, 250
TPS3808G50DBVR Tape and Reel, 3000

ABSOLUTE MAXIMUM RATINGS

over operating junction temperature range (unless otherwise noted)

Input voltage range, V
CT voltage range, V
Other voltage ranges: V
RESET pin current 5 mA
Operating junction temperature range, T
Storage temperature range, T
ESD rating, HBM 2 kV
ESD rating, CDM 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) Due to the low dissipated power in this device, it is assumed that TJ= TA.

2

DD

CT

, VMR, V

RESET

SENSE

(2)

J

STG

(1)

TPS3808 UNIT

-0.3 to 7.0 V

-0.3 to V

-40 to +150 ° C

-65 to +150 ° C

+ 0.3 V

DD

-0.3 to 7 V

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ELECTRICAL CHARACTERISTICS

1.8V ≤ V
otherwise noted. Typical values are at TJ= 25 ° C.

V

DD

I

DD

V

OL

V

IT

V

hys

R

MR

I

SENSE

I

OH

C

IN

V

IL

V

IH

t

w

t

d

t

pHL

θ

JA

DD

≤ 6.5V, R

= 100k Ω , C

LRESET

LRESET

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input supply range 1.8 6.5 V

Supply current (current into V

pin)

DD

Low-level output voltage

Power-up reset voltage

(1)

TPS3808G01 -2.0 ± 1.0 +2.0

Negative-going

VIT≤ 3.3V -1.5 ± 0.5 +1.5

input threshold 3.3V < VIT≤ 5.0V -2.0 ± 1.0 +2.0 %
accuracy

VIT≤ 3.3V -40 ° C < TJ< +85 ° C -1.25 ± 0.5 +1.25

3.3V < VIT≤ 5.0V -40 ° C < TJ< +85 ° C -1.5 ± 0.5 +1.5

Hysteresis on VITpin %V

TPS3808G01 1.5 3.0
Fixed versions 1.0 2.5

MR Internal pull-up re­sistance

Input current at SENSE
pin

TPS3808G01 V
Fixed versions V

RESET leakage current V
Input capacitance, any

pin

CT pin VIN= 0V to V

Other pins VIN= 0V to 6.5V 5
MR logic low input 0.3 V
MR logic high input 0.7 V

Maximum transient
duration

SENSE VIH= 1.05V

MR VIH= 0.7V

CT = Open 12 20 28 ms

CT = V
RESET delay time See timing diagram

DD

CT = 100pF 0.75 1.25 1.75 ms

CT = 180nF 0.7 1.2 1.7 s
Propagation delay MR to RESET VIH= 0.7V
High to low level RESET

delay

SENSE to RESET VIH= 1.05V
Thermal resistance,

junction-to-ambient

= 50pF, over operating temperature range (T

V

= 3.3V, RESET not asserted

DD

MR, RESET, CT open
V

= 6.5V, RESET not asserted

DD

MR, RESET, CT open

1.3V ≤ V

1.8V ≤ V
V

OL

SENSE
SENSE
RESET

< 1.8V, IOL= 0.4mA 0.3 V

DD

≤ 6.5V, IOL= 1.0mA 0.4 V

DD

(max) = 0.2V, I

= V

IT

= 15µA 0.8 V

RESET

= 6.5V 1.7 µA
= 6.5V, RESET not asserted 300 nA

DD

, VIL= 0.95V

IT

, VIL= 0.3V

DD

, VIL= 0.3V

DD

, VIL= 0.95V

IT

IT

DD

DD

IT

TPS3808

SBVS050B – MAY 2004 – REVISED OCTOBER 2004

= -40 ° C to +125 ° C), unless

J

2.4 5.0 µA

2.7 6.0 µA

70 90 k Ω

-25 25 nA

5

DD

DD

20

0.001

180 300 420 ms

150 ns

20 µs

290 ° C/W

IT

pF

V

µs

(1) The lowest supply voltage (V

) at which RESET becomes active. T

DD

≥ 15µs/V.

rise(VDD)

3

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Adjustable Voltage Version

Fixed Voltage Version

Reset

Logic

Timer

90k

V

DD

V

DD

GND

0.4V

V

REF

SENSE

CT

TPS3808G01

Adjustable Voltage

Reset

Logic

Timer

90k

V

DD

V

DD

GND

0.4V
V

REF

SENSE

CT

R

1

R

2

R

1

+ R

2

= 4MΩ

MR

MR

RESET RESET

+ +

−−

DBV PACKAGE

SOT23

(TOP VIEW)

1

2

3 4

5

RESET

GND

MR

SENSE

V

DD

CT

6

TPS3808

SBVS050B – MAY 2004 – REVISED OCTOBER 2004

FUNCTIONAL BLOCK DIAGRAMS

Figure 2. Adjustable and Fixed Voltage Versions

NAME

RESET 1 RESET is an open drain output that is driven to a low impedance state when RESET is asserted (either the

GND 2 Ground
MR 3 Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to V
CT 4 Reset period programming pin. Connecting this pin to V

SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold

V

DD

4

TERMINAL

SOT23 (DBV)

PIN NO.

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

DESCRIPTION

SENSE input is lower than the threshold voltage (V
low (asserted) for the reset period after both SENSE is above VITand MR is set to a logic high. A pull-up
resistor from 10k Ω to 1M Ω should be used on this pin, and allows the reset pin to attain voltages higher than
VDD.

results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor ≥ 100pF gives a user-programmable delay time. See Selecting The Reset Delay Time in the Device
Operation section for more information.

voltage VIT, then RESET is asserted.

6 Supply voltage. It is good analog design practice to place a 0.1µF ceramic capacitor close to this pin.

) or the MR pin is set to a logic low). RESET will remain

IT

through a 40k Ω to 200k Ω resistor or leaving it open

DD

by a 90k Ω pull-up resistor.

DD