Datasheet TPS3305-18DGN, TPS3305-18D, TPS3305-33DR, TPS3305-33DGNR, TPS3305-33DGN Datasheet (Texas Instruments)

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Dual Supervisory Circuits for DSP and
Processor-Based Systems

D

Power-On Reset Generator with Fixed
Delay Time of 200 ms, no External
Capacitor Needed

D

Watchdog Timer Retriggers the RESET
Output at SENSEn ≥ V

IT+

D

T emperature-Compensated Voltage
Reference

D

Maximum Supply Current of 40 µA

D

Supply Voltage Range...2.7 V to 6 V

D

Defined RESET Output from VDD ≥ 1.1 V

D

MSOP-8 and SO-8 Packages

D

T emperature Range...–40°C to 85°C

typical applications

Figure 1 lists some of the typical applications for the TPS3305 family , and a schematic diagram for a DSP-based
system application. This application uses TI part numbers TPS3305–25, TPS7133, TPS71025, and
TMS320VC549.

TPS7133

V

O

V

I

GND

TPS71025

V

O

V

I

GND

V

DD

GND

SENSE 1
SENSE 2

MR

RESET

WDI

DSP

GND

DV

DD

CV

DD

TMS320VC549TPS3305–25
RESET
XF

2.5 V

3.3 V

5 V – 10 V

External

Reset

Source

Figure 1. Applications Using the TPS3305 Family

• Applications using DSPs, Microcontrollers

or Microprocessors

• Industrial Equipment

• Programmable Controls

• Automotive Systems

• Portable/Battery Powered Equipment

• Intelligent Instruments

• Wireless Communication Systems

• Notebook/Desktop Computers

description

The TPS3305 family is a series of micropower supply voltage supervisors designed for circuit initialization,
primarily in DSP and processor-based systems, which require two supply voltages.

The product spectrum of the TPS3305 is designed for monitoring two independent supply voltages of

3.3 V/1.8 V, 3.3 V/2.5 V or 3.3 V /5 V.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

SENSE1
SENSE2

WDI

GND

V

DD

MR
RESET
RESET

D OR DGN PACKAGE

(TOP VIEW)

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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description (continued)

The various supply voltage supervisors are designed to monitor the nominal supply voltage, as shown in the
following supply voltage monitoring table.

SUPPLY VOLTAGE MONITORING

NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP)

DEVICE

SENSE1 SENSE2 SENSE1 SENSE2

TPS3305-18 3.3 V 1.8 V 2.93 V 1.68 V
TPS3305-25 3.3 V 2.5 V 2.93 V 2.25 V
TPS3305-33 5 V 3.3 V 4.55 V 2.93 V

During power-on, RESET is asserted when the supply voltage V

DD

becomes higher than 1.1 V . Thereafter , the

supply voltage supervisor monitors the SENSEn inputs

and keeps RESET active as long as SENSEn remains

below the threshold voltage V

IT+

.

An internal timer delays the return of the RESET

output to the inactive state (high) to ensure proper system reset.

The delay time, t

d typ

= 200 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage

V

IT+

. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage V

IT–

, the RESET output

becomes active (low) again.
The TPS3305-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative

transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
t

t(out)

= 1.6 s, RESET becomes active for the time period t

d

. This event also reinitializes the watchdog timer.

Leaving WDI unconnected disables the watchdog.
The TPS3305-xx family of devices incorporates a manual reset input, MR

. A low level at MR causes RESET
to become active. In addition to the active-low RESET output, the TPS3305-xx family includes an active-high
RESET output.

The TPS3305-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages.
The TPS3305-xx family is characterized for operation over a temperature range of – 40°C to 85°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

SMALL OUTLINE

(D)

PowerPAD

µ-SMALL OUTLINE

(DGN)

MARKING

DGN PACKAGE

CHIP FORM

(Y)

TPS3305-18D TPS3305-18DGN TIAAM TPS3305-18Y

–40_C to 85_C

TPS3305-25D TPS3305-25DGN TIAAN TPS3305-25Y
TPS3305-33D TPS3305-33DGN TIAAO TPS3305-33Y

PowerPAD is a trademark of Texas Instruments Incorporated.

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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description (continued)

FUNCTION/TRUTH TABLES

MR

SENSE1>V

IT1

SENSE2>V

IT2

RESET RESET

L X

†

X

†

L H
H 0 0 L H
H 0 0 L H
H 0 1 L H
H 0 1 L H
H 1 0 L H
H 1 0 L H
H 1 1 L H
H 1 1 H L

†

X = Don’t care

functional block diagram

_

+

_

+

R4

R2

R1

R3

Reference

Voltage

of 1.25 V

RESET

Logic + Timer

Oscillator

14 kΩ

V

DD

MR

SENSE 1

SENSE 2

GND

WDI

RESET

RESET

TPS3305

Watchdog

Logic + Timer

40 kΩ

Transition
Detection

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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timing diagram

t

d

t

d

t

d

RESET Because of WDI

RESET Because of MR

RESET Because of SENSE Below V

IT–

RESET Because of SENSE Below V

IT–

SENSEn

V

(nom)

V

IT–

MR

1

0

1

0

RESET

t

t

t

1

0

WDI

t

t(out)

t

t

d

RESET Because

of SENSE Below V

IT–

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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TPS3305Y chip information

These chips, when properly assembled, display characteristics similar to those of the TPS3305. Thermal
compression or ultrasonic bonding may take place on the doped aluminium bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.

56

48

TPS3305Y

(1)
(2)
(3)

(5)

(6)

CHIP THICKNESS: 10 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS

(4)

(7)

(8)

(1)(2)(3)(4)

(5) (6)

(7) (8)

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

GND 4 Ground
MR 7 I Manual reset
RESET 5 O Active-low reset output
RESET 6 O Active-high reset output
SENSE1 1 I Sense voltage input 1
SENSE2 2 I Sense voltage input 2
WDI 3 I Watchdog timer input
V

DD

8 Supply voltage

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

DD

(see Note1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

All other pins (see Note 1) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum low output current, I

OL

5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum high output current, I

OH

–5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0 or V

I

> VDD) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0 or V

O

> VDD) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Soldering temperature 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h

continuously.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DGN 2.14 mW 17.1 mW/°C 1.37 mW 1.11 mW

D 725 mW 5.8 mW/°C 464 mW 377 mW

recommended operating conditions at specified temperature range

MIN MAX UNIT

Supply voltage, V

DD

2.7 6 V

Input voltage at MR and WDI, V

I

0 VDD+0.3 V

Input voltage at SENSE1 and SENSE2, V

I

0 (VDD+0.3)VIT/1.25V V

High-level input voltage at MR and WDI, V

IH

0.7xV

DD

V

Low-level input voltage at MR and WDI, V

IL

0.3×V

DD

V
Input transition rise and fall rate at MR, ∆t/∆V 50 ns/V
Operating free-air temperature range, T

A

–40 85 °C

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

7

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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDD = 2.7 V to 6 V, IOH = –20 µA VDD– 0.2V

V

OH

High-level output voltage

VDD = 3.3 V, IOH = –2 mA

VDD– 0.4V

V
VDD = 6 V, IOH = –3 mA VDD– 0.4V
VDD = 2.7 V to 6 V, IOL = 20 µA 0.2

V

OL

Low-level output voltage

VDD = 3.3 V, IOL = 2 mA 0.4

V
VDD = 6 V, IOL = 3 mA 0.4

Power-up reset voltage (see Note 2) VDD ≥ 1.1 V, IOL = 20 µA 0.4 V

1.64 1.68 1.72

VSENSE1, VDD = 2.7 V to 6 V,

2.20 2.25 2.30

VSENSE2DDTA = 0°C to 85°C

2.86 2.93 3

V

Negative-going input threshold voltage

4.46 4.55 4.64

V

IT–

ggg g

(see Note 3)

1.64 1.68 1.73

VSENSE1, VDD = 2.7 V to 6 V,

2.20 2.25 2.32

VSENSE2DDTA =–40°C to 85°C

2.86 2.93 3.02

V

4.46 4.55 4.67

V

IT–

= 1.68 V 15

p

V

IT–

= 2.25 V 20

V

hys

Hysteresis at VSENSEn input

V

IT–

= 2.93 V 30

mV

V

IT–

= 4.55 V 40

I

H(AV)

Average high-level input current

WDI = VDD = 6 V
Time average (dc = 88%)

100 150

I

L(AV)

Average low-level input current

WDI

WDI = 0 V, VDD = 6 V,
Time average (dc = 12%)

–15 –20

µ

A

WDI WDI = VDD = 6 V, 120 170

p

MR MR = 0.7 × VDD,VDD = 6 V –130 –180

IHHigh-level input current

SENSE1 VSENSE1 = VDD = 6 V 5 8

µ

A

SENSE2 VSENSE2 = VDD = 6 V 6 9
WDI WDI = 0 V, V

DD,

= 6 V –120 –170

I

L

Low-level input current

MR

MR = 0V, VDD = 6 V –430 –600

µA

SENSEn VSENSE1,2 = 0 V –1 1

I

DD

Supply current 40 µA

C

i

Input capacitance VI = 0 V to V

DD

10 pF

NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.

3. T o ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements at V

DD

= 2.7 V to 6 V, R

L

= 1 MΩ, C

L

= 50 pF, T

A

= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SENSEn V

SENSEnL

= V

IT–

–0.2 V , V

SENSEnH

= V

IT+

+0.2 V 6 µs

t

w

Pulse width

MR

100 ns

WDI

V

IH

= 0.7 ×

V

DD

,

V

IL

= 0.3 ×

V

DD

100 ns

switching characteristics at V

DD

= 2.7 V to 6 V, R

L

= 1 MΩ, C

L

= 50 pF, T

A

= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

t(out)

Watchdog time out

V

I(SENSEn)

≥ V

IT+

+ 0.2 V,

MR

≥ 0.7 × VDD, See timing diagram

1.1 1.6 2.3 s

t

d

Delay time

V

I(SENSEn)

≥ V

IT+

+ 0.2 V,

MR

≥ 0.7 × VDD, See timing diagram

140 200 280 ms

t

PHL

Propagation (delay) time,
high-to-low level output

MR to RESET,
MR to RESET

V

I(SENSEn

)

≥ V

IT+

+0.2 V ,

t

PLH

Propagation (delay) time,
low-to-high level output

MR to RESET,
MR

to RESET

I(SENSEn) IT+

VIH = 0.7 × VDD,VIL = 0.3 × V

DD

200

500

ns

t

PHL

Propagation (delay) time,
high-to-low level output

SENSEn to RESET,
SENSEn to RESET

VIH = V

IT+

+0.2 V, VIL = V

IT–

–0.2 V ,

t

PLH

Propagation (delay) time,
low-to-high level output

SENSEn to RESET,
SENSEn to RESET

IH IT+ IL IT

MR ≥ 0.7 × V

DD

1

5µs

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

1

0.999

0.997

0.995
–40 –15 10 35

Normalized Input Threshold Voltage – VIT(TA), VIT(25 )

1.002

1.003

NORMALIZED SENSE THRESHOLD VOLTAGE

vs

FREE-AIR TEMPERATURE AT V

DD

1.005

60 85

VDD = 6 V
MR

= Open

1.004

1.001

0.998

0.996

C

°

TA – Free-Air Temperature – °C

Figure 3

4

0

–6

–10

–0.5 0 0.5 1 2.5 3 3.5

– Supply Current –

8

14

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

18

4567

16

12
10

6

2

–2
–4

–8

1.5 2 4.5 5.5 6.5

I

DD

Aµ

VDD – Supply Voltage – V

SENSEn = V

DD

MR = Open
TA = 25°C

TPS3305–33

Figure 4

–400

–500

–700

–900

–1–0.5 0 1 1.5 2.5 3

– Input Current –

–200

–100

INPUT CURRENT

vs

INPUT VOLTAGE AT MR

100

3.5 4 5.5 6.5

0

–300

–600

–800

0.5 2

4.5

56

V

I

– Input Voltage at MR

– V

I

I

Aµ

VDD = 6 V
TA = 25°C

Figure 5

5
4

2

0

0 100 200 300 400 500 600

– Minimum Pulse Duration at

7

9

MINIMUM PULSE DURATION AT SENSE

vs

THRESHOLD OVERDRIVE

10

700 800 900 1000

8

6

3

1

SENSE – Threshold Overdrive – mV

t

w

V

sense –

sµ

VDD = 6 V
MR

= Open

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

10

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TYPICAL CHARACTERISTICS

Figure 6

1

0.5

0

0 –0.5 –1 –1.5 –2 –2.5 –3

– High-Level Output Voltage – V

1.5

2

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

2.5

–3.5 –4 –5 –6–4.5 –5.5

IOH – High-Level Output Current – mA

V

OH

85°C

–40°C

VDD = 2 V
MR

= Open

Figure 7

– High-Level Output Voltage – V

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

IOH – High-Level Output Current – mA

V

OH

3.5
3

2

0

0 –5 –10 –15 –20 –25 –30

4.5

6

6.5

–35 –40 –45 –50

85°C

–40°C

5.5
5

4

2.5

1.5
1

0.5

VDD = 6 V
MR

= Open

Figure 8

85°C

–40°C

VDD = 2 V
MR

= Open

1

0.5

0

0 0.5 1 1.5 2 3 3.5

– Low-Level Output Voltage – V

1.5

2

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

2.5

4 4.5 5.5 6

2.5

5

IOL – Low-Level Output Current – mA

V

OL

Figure 9

3.5
3

1.5

0

0 5 10 15 20 30 35

4.5

5.5

6.5

40 50 55 60

85°C

–40°C

VDD = 6 V
MR

= Open

– Low-Level Output Voltage – V

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

IOL – Low-Level Output Current – mA

V

OL

6

5

4

2.5
2

1

0.5

25 45

TPS3305-18, TPS3305-25, TPS3305-33

DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

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MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TPS3305-18, TPS3305-25, TPS3305-33
DUAL PROCESSOR SUPERVISORS

SLVS198 – DECEMBER 1998

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad
(See Note D)

0,15 NOM

Gage Plane

4073271/A 01/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05
2,95

1

0,38

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,65

M

0,25

0°–6°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-187

PowerPAD is a trademark of Texas Instruments Incorporated.

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated