Texas Instruments TPS2550, TPS2551 Datasheet

* USB Requirement that downstream-facing ports
are bypassed with at least 120 F per hubm
IN
EN
OUT
ILIM
GND
PowerPad
USBData
USB Port
120 F*m
R 15k
ILIM
W
0.1 Fm
R
100k
FAULT
W
INPUT
5VUSB
FAULT Signal
ControlSignal
TPS2550/51
2
1
3
5
6
4
OUT
EN
GND
ILIM FAULT
IN
TPS2550/TPS2551
DBVPACKAGE
(TOP VIEW)
TPS2550/TPS2551
DRVPACKAGE
(TOP VIEW)
2
1
3
5
6
4
OUT
EN
GND
ILIM
FAULT
IN
PAD
EN= ActiveLowfortheTPS2550 EN= ActiveHighfortheTPS2551
TPS2014600mA TPS20151 A TPS2041B500mA TPS2051B500mA TPS2045A 250mA TPS2049100mA TPS2055A 250mA TPS20611 A TPS20651 A TPS20681.5 A TPS20691.5 A
TPS2042B500mA TPS2052B500mA TPS2046B250mA TPS2056250mA TPS20621 A TPS20661 A TPS20601.5 A TPS20641.5 A
TPS2080500mA TPS2081500mA TPS2082500mA TPS2090250mA TPS2091250mA TPS2092250mA
TPS2043B500mA TPS2053B500mA TPS2047B250mA TPS2057A 250mA TPS20631 A TPS20671 A
TPS2044B500mA TPS2054B500mA TPS2048A 250mA TPS2058250mA
TPS2085500mA TPS2086500mA TPS2087500mA TPS2095250mA TPS2096250mA TPS2097250mA
TPS201xA 0.2A to2 A TPS202x0.2 A to2A TPS203x0.2 A to2A
GENERAL SWITCHCATALOG
33m ,SingleW 80m ,SingleW
80m ,DualW 80m ,DualW
80m , TripleW
80m ,QuadW 80m ,QuadW
TPS2550 TPS2551
www.ti.com
SLVS736 – FEBRUARY 2008
ADJUSTABLE CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
1

FEATURES

Adjustable Current-Limit, 100 mA 1100 mA
Fast Overcurrent Response - 2 µ S Typical
85-m High-Side MOSFET (DBV Package)
Reverse Input-Output Voltage Protection
Operating Range: 2.5 V to 6.5 V
Deglitched Fault Report
1- µ A Maximum Standby Supply Current
Ambient Temperature Range: 40 ° C to 85 ° C
Built-in Soft-Start
15 kV ESD Protection (with external
capacitance) output load exceeds the current-limit threshold or a

APPLICATIONS

USB Ports/Hubs
Cell phones
Laptops
Heavy Capacitive Loads
Reverse-Voltage Protection

DESCRIPTION

The TPS2550/51 power-distribution switch is intended for applications where heavy capacitive loads and short-circuits are likely to be encountered, incorporating a 100-m , N-channel MOSFET in a single package. The current-limit threshold is user adjustable between 100 mA and 1.1 A via an external resistor. The power-switch rise and fall times are controlled to minimize current surges during switching.
The device limits the output current to a desired level by switching into a constant-current mode when the
short is present. An internal reverse-voltage detection comparator disables the power-switch in the event that the output voltage is driven higher than the input to protect devices on the input side of the switch. The FAULT logic output asserts low during both overcurrent and reverse-voltage conditions.
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1. Typical Application as USB Power Switch
Copyright © 2008, Texas Instruments Incorporated
www.ti.com
TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
AVAILABLE OPTIONS AND ORDERING INFORMATION
DEVICE AMBIENT ENABLE SON
(1)
TEMPERATURE (DRV) (DBV) CONTINUOUS LOAD CURRENT
TPS2550 Active low TPS2550DRV TPS2550DBV 1.1 A TPS2551 Active high TPS2551DRV TPS2551DBV 1.1 A
– 40 ° C to 85 ° C
(1) Add an R suffix to the device type for tape and reel.
(1)
SOT23
RECOMMENDED MAXIMUM

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted
Voltage range on IN, OUT, EN or EN, ILIM, FAULT – 0.3 to 7 V Voltage range from IN to OUT – 7 to 7 V
I
Continuous output current Internally limited
OUT
Continuous total power dissipation FAULT sink current 25 mA
ILIM source current 1 mA
ESD
T
Maximum junction temperature – 40 to 150 ° C
J
T
Storage temperature – 65 to 150 ° C
Sgt
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 300 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are referenced to GND unless otherwise noted.
HBM 2 kV CDM 500 V
(1) (2)
VALUE UNIT
See "Dissipation Rating
Table"

DISSIPATION RATING TABLE

BOARD PACKAGE THERMAL THERMAL TA≤ 25 ° C DERATING TA= 70 ° C TA= 85 ° C
(1)
Low-K High-K Low-K High-K
DBV 350 ° C/W 55 ° C/W 285 mW 2.85 mW/ ° C 155 mW 114 mW
(2)
DBV 160 ° C/W 55 ° C/W 625 mW 6.25 mW/ ° C 340 mW 250 mW
(1)
DRV 140 ° C/W 20 ° C/W 715 mW 7.1 mW/ ° C 395 mW 285 mW
(2)
DRV 75 ° C/W 20 ° C/W 1330 mW 13.3 mW/ ° C 730 mW 530 mW
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
RESISTANCE RESISTANCE
θ
JA
θ
JC
RATING
TA= 25 ° C RATING RATING
POWER FACTOR ABOVE POWER POWER
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RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
V
IN
V
EN
V
/EN
I
OUT
R
ILIM
I
/FAULT
T
J
Input voltage, IN 2.5 6.5 V
Enable voltage V
TPS2550 0 6.5
TPS2551 0 6.5 Continuous output current, OUT 0 1.1 A Current-limit set resistor from ILIM to GND 14.3 80.6 k FAULT sink current 0 10 mA
Operating virtual junction temperature
DRV – 40 105
DBV – 40 125

ELECTRICAL CHARACTERISTICS

over recommended operating junction temperature range, 2.5 V V (unless otherwise noted)
PARAMETER TEST CONDITIONS
POWER SWITCH
DBV package, TJ= 25 ° C 85 95
r
DS(on)
t
r
t
f
Static drain-source on-state resistance m
Rise time, output
Fall time, output
ENABLE INPUT EN OR EN
V V I
EN
t
on
t
off
High-level input voltage 1.1
IH
Low-level input voltage 0.66
IL
Input current VEN= 0 V or 6.5 V, V Turnon time 3 ms Turnoff time 3 ms
CURRENT LIMIT
I
OS
I
OC
t
IOS
Short-circuit current, OUT connected to GND R
Current-limit threshold (Maximum DC output current I
Response time to short circuit VIN= 5.0 V (see Figure 3 ) 2 µ s
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point (V
– VIN)
OUT
Time from reverse-voltage condition to MOSFET turn off
SUPPLY CURRENT
I
IN_off
I
IN_on
I
REV
Supply current, low-level output 0.1 1 µ A
Supply current, high-level output
Reverse leakage current V
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
DBV package, – 40 ° C TJ≤ 125 ° C 135
DRV package, TJ= 25 ° C 100 115
DRV package, – 40 ° C TJ≤ 105 ° C 145
VIN= 6.5 V 1.0 1.5
VIN= 2.5 V 0.65 1.0
VIN= 6.5 V 0.2 0.5
VIN= 2.5 V 0.2 0.5
/EN
CL= 1 µ F, RL= 100 , (see Figure 2 )
delivered to load) R
OUT
VIN= 5.0 V 3 5 7 ms
VIN= 6.5 V, No load on OUT, VEN= 6.5 V or VEN= 0 V, 14.3 k
R
80.6 k
ILIM
VIN= 6.5 V, No load on OUT, VEN= 0 V or
VEN= 6.5 V
= 6.5 V, VIN= 0 V TJ= 25 ° C 0.01 1 µ A
OUT
6.5 V, R
IN
ILIM
(1)
= 14.3 k , V
= 0 V, or V
/EN
MIN TYP MAX UNIT
CL= 1 µ F, RL= 100 , (see Figure 2 )
= 0 V or 6.5 V – 0.5 0.5 µ A
R
= 80.6 k 110 215 300
ILIM
= 38.3 k 300 500 650
ILIM
R
= 15 k 1050 1400 1650
ILIM
R
= 80.6 k 290 315 340
ILIM
= 38.3 k 620 665 705
ILIM
R
= 15 k 1550 1650 1750
ILIM
95 135 190 mV
R
= 15 k 150 µ A
ILIM
R
= 80.6 k 130 µ A
ILIM
TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
= 5.0 V
EN
° C
ms
V
mA
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TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, 2.5 V V (unless otherwise noted)
PARAMETER TEST CONDITIONS
UNDERVOLTAGE LOCKOUT
V
FAULT FLAG
V
THERMAL SHUTDOWN
Low-level input voltage, IN VINrising 2.35 2.45 V
UVLO
Hysteresis, IN TJ= 25 ° C 25 mV
Output low voltage, FAULT I
OL
Off-state leakage V
FAULT deglitch
Thermal shutdown threshold 155 ° C Thermal shutdown threshold in current-limit 135 ° C Hysteresis 15 ° C
= 1 mA 180 mV
/FAULT
= 6.5 V 1 µ A
/FAULT
FAULT assertion or de-assertion due to overcurrent condition 5 7.5 10 ms
FAULT assertion or de-assertion due to reverse-voltage
condition
6.5 V, R
IN
ILIM
(1)
= 14.3 k , V
= 0 V, or V
/EN
MIN TYP MAX UNIT
2 4 6 ms
= 5.0 V
EN
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Charge
Pump
Driver
UVLO
Current
Limit
Thermal
Sense
IN
GND
EN
ILIM
OUT
FAULT
CS
Reverse
Voltage
Comparator
-
+
Current
Sense
4-ms
Deglitch
8-msDeglitch
TPS2550 TPS2551
SLVS736 – FEBRUARY 2008

DEVICE INFORMATION

Terminal Functions
TERMINAL
NAME TPS2550DBV TPS2551DBV TPS2550DRV TPS2551DRV
EN 3 4 I Enable input, logic low turns on power switch EN 3 4 I Enable input, logic high turns on power switch GND 2 2 5 5 Ground connection; should be connected
IN 1 1 6 6 I Input voltage; connect a 0.1 µ F or greater
FAULT 4 4 3 3 O Active-low open-drain output, asserted during
OUT 6 6 1 1 O Power-switch output ILIM 5 5 2 2 I External resistor used to set current-limit
POWER PAD PAD Internally connected to GND; used to heat-sink PAD the part to the circuit board traces. Should be
I/O DESCRIPTION
externally to POWER PAD
ceramic capacitor from IN to GND as close to the IC as possible.
overcurrent, overtemperature, or reverse-voltage conditions.
threshold; recommended 14.3 k R k .
connected to GND pin.
ILIM
80.6
FUNCTIONAL BLOCK DIAGRAM
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R
L
C
L
OUT
t
r
t
f
90%
90%
10%
10%
50%
50%
90%
10%
V
EN
V
OUT
VOLTAGEWAVEFORMS
TESTCIRCUIT
t
on
t
off
50%
50%
90%
10%
t
on
t
off
V
OUT
V
OUT
V
EN
t
IOS
I
OS
I
OUT
I
OUT
I
OS
I
OC
DECREASING
LOAD
RESISTANCE
V
OUT
DECREASING
LOAD
RESISTANCE
TPS2550 TPS2551
SLVS736 – FEBRUARY 2008

PARAMETER MEASUREMENT INFORMATION

Figure 2. Test Circuit and Voltage Waveforms
Figure 3. Response Time to Short-Circuit Waveform
Figure 4. Output Voltage vs. Current-Limit Threshold
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TPS2550 TPS2551
SLVS736 – FEBRUARY 2008

TYPICAL CHARACTERISTICS

Figure 5. Turnon Delay and Rise Time
Figure 6. Turnoff Delay and Fall Time
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TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 7. Device Enabled into Short-Circuit
Figure 8. Full-Load to Short-Circuit Transient Response
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TYPICAL CHARACTERISTICS (continued)
TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
Figure 9. Short-Circuit to Full-Load Recovery Response
Figure 10. No-Load to Short-Circuit Transient Response
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TPS2550 TPS2551
SLVS736 – FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 11. Short-Circuit to No-Load Recovery Response
Figure 12. No Load to 1 Transient Response
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