TEXAS INSTRUMENTS TPS23753 Technical data

TPS23753

M1

R

CS

C

OUT

D

VC

GATE

RTN

V

C

CS

C

VC

CTL

V

B

D1

58V

C1

0.1µF

R

DEN

R

CLS

From Ethernet

Transformers

V

DD1

V

SS

CLS

C

IN

V

OUT

R

CTL

C

CTL

From Spare

Pairs or

Transformers

D

S

DEN

BLNK

FRS

D

A

R

FRS

V

B

C

VB

Adapter

R

FBU

R

FBL

TLV431

R

OB

C

IZ

APD

R

APD2

R

APD1

R

BLNK

V

DD

C

IO

T1

BR1

BR2

R

VC

* AdapterinterfaceandR

BLNK

areOptional

*

*

TPS23753

www.ti.com

.............................................................................................................................................................. SLVS853A – JUNE 2008 – REVISED JUNE 2008

IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER

1

FEATURES

• Optimized for Isolated Converters

• Complete PoE Interface

• Adapter ORing Support

• 12 V Adapter Support

• Programmable Frequency with Synch.

• Robust 100 V, 0.7 Ω Hotswap MOSFET

• Small TSSOP 14 Package

• 15 kV / 8 kV System Level ESD Capable

• – 40 ° C to 125 ° C Junction Temperature Range

• Design Procedure Application Note - SLVA305

• Adapter ORing Application Note - SLVA306

APPLICATIONS

• IEEE 802.3-2005 Compliant Powered Devices

• VoIP Telephones

• Access Points

• Security Cameras

DESCRIPTION

The TPS23753 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
current-mode dc/dc controller optimized specifically
for isolated converter designs. The PoE
implementation supports the IEEE 802.3-2005
(previously 802.3af) standard, 12.95 W (13 W) PD.

The TPS23753 supports a number of input-voltage
ORing options including highest voltage, external
adapter preference, and PoE preference.

The PoE interface features an external detection
signature pin that can also be used to disable the
internal hotswap MOSFET. This allows the PoE
function to be turned off. Classification can be
programmed to any of the defined types with a single
resistor.

The dc/dc controller features a bootstrap startup
mechanism with an internal, switched current source.
This provides the advantages of cycling overload fault
protection without the constant power loss of a pull up
resistor.

The programmable oscillator may be synchronized to
a higher-frequency external timing reference.

1

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Basic TPS23753 Implementation

Copyright © 2008, Texas Instruments Incorporated

TPS23753

SLVS853A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................

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This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either V
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

or ground. Specific guidelines for handling devices of this type are contained in the publication

CC

PRODUCT INFORMATION

(1)

DEVICE DUTY CYCLE POE UVLO ON / HYST. PACKAGE MARKING

TPS23753 0 – 80% 35/4.5 PW (TSSOP-14) TP23753

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

Voltags are with respect to V

(unless otherwise noted)

SS

(1)

VALUE UNIT

V

Input voltage range [APD, BLNK

I

VDD, V
V
CLS

DD1

, DEN, RTN

DD1

to RTN – 0.3 to 100 V

(3)

(3)

CS to RTN – 0.3 to V

, CTL, FRS

(2)

– 0.3 to 100 V

– 0.3 to 6.5 V

(3)

(3)

, V

] to RTN – 0.3 to 6.5 V

B

B

VCto RTN – 0.3 to 19 V
GATE to RTN – 0.3 to VC+ 0.3 V

Sourcing current V

B

Internally limited mA

Average sourcing or sinking current GATE 25 mA

ESD rating

ESD – system level (contact/air)

T

Operating junction temperature range ° C

J

(4)

HBM 2 kV
CDM 500 V

8/15 kV

– 40 to Internally

Limited

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) I
(3) Do not apply voltage to these pins.

= 0 for V

RTN

> 80V.

RTN

(4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the

TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure

threshold.

V

RMS

DISSIPATION RATINGS

θ

PACKAGE

JT

(1)

( ° C/W)

PW (TSSOP-14) 0.97 173.6 99.3

(1) JEDEC method with high-k board (4 layers, 2 signal and 2 planes).
(2) JEDEC method with low-k board (2 signal layers).

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θ

JA

(2)

( ° C/W)

θ

JA

(1)

( ° C/W)

TPS23753

www.ti.com

.............................................................................................................................................................. SLVS853A – JUNE 2008 – REVISED JUNE 2008

RECOMMENDED OPERATING CONDITIONS

Voltage with respect to V

Input voltage range, VDD, V
Input voltage range, VDD, V

V

I

R

BLNK

T

J

Input voltage range, VCto RTN 0 18 V
Input voltage range, APD, CTL to RTN 0 V
Input voltage range, CS to RTN 0 2 V
RTN current (T
VBsourcing current 0 2.5 5 mA
VBcapacitance 0.08 0.1 2.2 µ F

Synchronization pulse width input (when used) 25 150 ns
Operating junction temperature range – 40 125 ° C

(unless otherwise noted)

SS

, RTN 0 57 V

DD1

to RTN 0 57 V

DD1

≤ 125 ° C) 350 mA

J

ELECTRICAL CHARACTERISTICS

Unless otherwise noted: CS = APD = CTL = RTN, GATE open, R

24.9 k Ω , R

Controller Section Only

[V

= RTN and V

SS

V

C

UVLO

1

UVLO

H

t

ST

V

B

FRS

D

MAX

V

SYNC

CTL

V

ZDC

BLNK

CS

V

CSMAX

t

1

V

SLOPE

I

SL_EX

(1) The hysteresis tolerance tracks the rising threshold for a given device.

open, V

CLS

= V

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Undervoltage lockout V

Operating current VC= 12 V, CTL = V

Startup time, CVC= 22 µ F ms

Startup current source - I

Voltage 6.5 V ≤ VC≤ 18 V, 0 ≤ IVB≤ 5 mA 4.75 5.10 5.25 V

Switching frequency 223 248 273 kHz

Duty cycle CTL= VB, Measure GATE 76 78.5 81 %
Synchronization Input threshold 2.0 2.2 2.4 V

0% duty cycle threshold V
Softstart period Interval from switching start to V
Input resistance 70 100 145 k Ω

Blanking delay BLNK = RTN 35 52 75 ns

Maximum threshold voltage V
Turn off delay VCS= 0.65 V 25 41 60 ns
Internal slope compensation voltage Peak voltage at maximum duty cycle, referred to CS 90 118 142 mV
Peak slope compensation current V
Bias current (sourcing) Gate high, dc component of CS current 2 3 4.2 µ A

= 48 V, V

VDD-VSS

] or [V

DD1

= RTN = V

SS

VC

VDD1-RTN

= 48 V, 8.5 V ≤ V

], all voltages referred to RTN. Typical specifications are at 25 ° C.

DD

VCrising 8.65 9 9.3
Hysteresis

V
V
V
V

CTL= VB, Measure GATE
R

In addition to t

R

(1)

= 10.2 V, VC(0) = 0 V 50 85 175

DD1

= 35 V, VC(0) = 0 V 30 48 85

DD1

= 10.2 V, VVC= 8.6 V 0.44 1.06 1.80

DD1

= 48 V, VVC= 0 V 2.5 4.3 6.0

DD1

= 60.4 k Ω

FRS

↓ until GATE stops 1.3 1.5 1.7 V

CTL

1

= 49.9 k Ω 41 52 63

BLNK

= VB, VCS↑ until GATE duty cycle drops 0.50 0.55 0.60 V

CTL

= VB, ICSat maximum duty cycle (ac component) 30 42 54 µ A

CTL

MIN NOM MAX UNIT

B

V

0 350 k Ω

= 60.4 k Ω , R

FRS

≤ 18 V, – 40 ° C ≤ TJ≤ 125 ° C

VC-RTN

B

CSMAX

BLNK

= 249 k Ω , C

= C

VB

= 0.1 µ F, R

VC

3.3 3.5 3.7

0.40 0.58 0.85 mA

400 800 µ s

=

DEN

mA

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TPS23753

SLVS853A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise noted: CS = APD = CTL = RTN, GATE open, R

24.9 k Ω , R

open, V

CLS

= 48 V, V

VDD-VSS

VDD1-RTN

= 48 V, 8.5 V ≤ V

Controller Section Only

[V

= RTN and V

SS

GATE

APD

V

APDEN

V

APDH

THERMAL SHUTDOWN

(2) The hysteresis tolerance tracks the rising threshold for a given device.
(3) These parameters are provided for reference only, and do not constitute part of TI ' s published device specifications for purposes of TI ' s

product warranty.

= V

DD

] or [V

DD1

= RTN = V

SS

], all voltages referred to RTN. Typical specifications are at 25 ° C.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Source current V
Sink current V

Threshold voltage V

= VB, VC= 12 V, GATE high, Pulsed measurement 0.30 0.46 0.60 A

CTL

= VB, VC= 12 V, GATE low, Pulsed measurement 0.50 0.79 1.1 A

CTL

V

↑ 1.42 1.5 1.58

APD

Hysteresis

(2)

Turn off temperature 135 145 155 ° C
Hysteresis

(3)

= 60.4 k Ω , R

FRS

≤ 18 V, – 40 ° C ≤ TJ≤ 125 ° C

VC-RTN

BLNK

= 249 k Ω , C

= C

VB

VC

0.28 0.3 0.32

= 0.1 µ F, R

20 ° C

DEN

ELECTRICAL CHARACTERISTICS

PoE and Control

[V

= V

DD

] or [V

DD1

DEN (DETECTION) (V

Detection current VDD= 1.6 V 62 64.3 66.5 µ A

Detection bias current VDD= 10 V, DEN open, Measure I

V

PD_DIS

I

lkg

Hotswap disable threshold 3 4 5 V
DEN leakage current V

CLS (CLASSIFICATION) (V

I

CLS

V

CL_ON

V

CL_HYS

V

CU_OFF

V

CU_HYS

I

lkg

Classification current mA

Classification regulator lower
threshold

Classification regulator upper
threshold

Leakage current VDD= 57 V, V

RTN (PASS DEVICE) (V

On resistance 0.7 1.2 Ω
Current limit V
Inrush limit V
Foldback voltage threshold VDDrising 11 12.3 13.6 V

I

lkg

Leakage current VDD= V

UVLO

UVLO_R VDDrising 33.9 35 36.1
UVLO_H Hysteresis

Undervoltage lockout threshold V

(1) The hysteresis tolerance tracks the rising threshold for a given device.

DD1

] = RTN, V

= 0 V, all voltages referred to V

VC-RTN

. Typical specifications are at 25 ° C.

SS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= V

Measure I

DD1

= RTN = V

DD

SUPPLY

positive)

SUPPLY

VDD= 10 V 399 406 413

SUPPLY

= VDD= 57 V, Float V

DEN

13 V ≤ VDD≤ 21 V, Measure I
R

= 1270 Ω 1.8 2.14 2.4

CLS

R

= 243 Ω 9.9 10.6 11.3

CLS

R

= 137 Ω 17.6 18.6 19.4

CLS

R

= 90.9 Ω 26.5 27.9 29.3

CLS

R

= 63.4 Ω 38 39.9 42

CLS

DD1

= V

DD

DD1

SUPPLY

and RTN, Measure I

= RTN = V

SUPPLY

DEN

positive)

5.2 12 µ A

0.1 5 µ A

Regulator turns on, VDDrising 10 11.7 13
Hysteresis

(1)

1.9 2.05 2.2
Regulator turns off, VDDrising 21 22 23
Hysteresis

(1)

= 0 V, DEN = VSS, Measure I

CLS

DD1

= 1.5 V, VDD= 48 V, Pulsed Measurement 405 450 505 mA

RTN

= 2 V, VDD: 0 V → 48 V, Pulsed Measurement 100 140 180 mA

RTN

= 100 V, DEN = V

RTN

(1)

SS

CLS

= RTN)

0.5 0.77 1

4.40 4.55 4.70

1 µ A

40 µ A

=

V

V

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GATE

RTN

V

C

CS

V

DD

V

SS

DEN

BLNK

FRS

V

B

CTL

CLS

1
2
3
4
5
6
7

8

14
13

11

10

9

12

APD

V

DD1

TPS23753

www.ti.com

.............................................................................................................................................................. SLVS853A – JUNE 2008 – REVISED JUNE 2008

ELECTRICAL CHARACTERISTICS (continued)

PoE and Control

[V

= V

DD

THERMAL SHUTDOWN

(2) These parameters are provided for reference only, and do not constitute part of TI ' s published device specifications for purposes of TI ' s

] or [V

DD1

Turn off temperature 135 145 155 ° C
Hysteresis

product warranty.

] = RTN, V

DD1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2)

= 0 V, all voltages referred to VSS. Typical specifications are at 25 ° C.

VC-RTN

20 ° C

DEVICE INFORMATION

TOP VIEW

Table 1. Terminal Functions

TERMINAL

NO. NAME

1 CTL I The control loop input to the PWM (pulse width modulator). Use VBas a pull up for CTL.
2 V

3 CS I

4 V

5 GATE O Gate drive output for the dc/dc converter switching MOSFET.
6 RTN RTN is the negative rail input to the dc/dc converter and output of the PoE hotswap.
7 V
8 V

9 V
10 DEN I/O
11 CLS O Connect a resistor from CLS to V
12 APD I

13 BLNK I/O
14 FRS I/O Connect a resistor from FRS to RTN to program the converter switching frequency.

B

C

SS

DD1

DD

I/O DESCRIPTION

O

I/O power this pin. Connect a 0.22 µ F minimum ceramic capacitor to RTN, and a larger capacitor to

5 V bias rail for dc/dc control circuits. Apply a 0.1 µ F to RTN. VBmay be used to bias an external
optocoupler for feedback.

Dc/dc converter switching MOSFET current sense input. Connect CS to the high side of the
RTN-referenced current sense resistor.

Dc/dc converter bias voltage. The internal startup current source and converter bias winding output
facilitate startup.

Negative power rail derived from the PoE source.
Source of dc/dc converter startup current. Connect to V
Positive input power rail for PoE interface circuit. Derived from the PoE source.
Connect a 24.9 k Ω resistor from DEN to V

to V

during powered operation causes the internal hotswap MOSFET to turn off.

SS

to program the classification current per Table 2 .

SS

Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an
external adapter. Connect to the adapter through a resistor divider.

Connect to RTN to utilize the internally set blanking period or connect through a resistor to RTN to
program the blanking period.

to provide the PoE detection signature. Pulling this pin

DD

for most applications.

DD

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5

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D

CLRB

Q

Oscillator

1

GATE

V

DD1

V

B

V

SS

Regulator

enb

Reference

CTL

BLNK

FRS

RTN

Control

enb

CONV.

OFF

+

-

800 sm

400 sm

SoftStart

0.55V

+

0.75V

­+

-

CK

RTN

CS

enb

11.5V&

9.5V

22V&

21.25V

35V &

30.5V

Class

Regulator

80mW

1

0

SRQ

12.5V
& 1V

ILIMb

H
L

Common

Circuitsand

PoEThermal

Monitor

RTN

CLS

V

SS

DEN

+

­EN

2.53V

CONV.

OFF

4.5V

40 Am

(pk)

Converter

Thermal

Monitor

2.875kW

50kW

50kW

APD

1.5V

& 1.2V

APDb

APDb

AUXb

AUXb

Blank

Switch

Matrix

V

DD

V

C

TPS23753

SLVS853A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................

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Pin Description

Refer to Figure 1 for component reference designators (R
for values denoted by reference (V
numerical values used in the following sections.

APD

APD forces power to come from an external adapter connected from V
switch. A resistor divider is recommended on APD when it is connected to an external adapter. The divider
provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage

Figure 2. TPS23753 Functional Block Diagram

for example). Electrical Characteristic values take precedence over any

CSMAX

for example ), and the Electrical Characteristics table

CS

to RTN by opening the hotswap

DD1

qualification assures the adapter can support the PD before the PoE current is cut off.

Product Folder Link(s): TPS23753

ADPTR-ON

is the desired adapter voltage that

Select the APD divider resistors per the following equations where V
enables the APD function as adapter voltage rises.

6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

( )

1 2 _APD APD ADPTR ON APDEN APDEN

R R V V V= ⋅ −

(

)

1 2

_

2

APD APD

ADPTR OFF APDEN APDH

APD

R R

V V V

R

+

= ⋅ −

(

)

(

)

BLNK BLNK

R k t nsΩ =

TPS23753

www.ti.com

The CLS output is disabled when a voltage above V

.............................................................................................................................................................. SLVS853A – JUNE 2008 – REVISED JUNE 2008

is applied to the APD pin.

APDEN

Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to RTN when not used.

BLNK

Blanking provides an interval between the gate drive going high and the current comparator on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparator is active, preventing undesired short duty cycles and premature current limiting.

Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a
programmable blanking period. The relationship between the desired blanking period and the programming
resistor is defined by the following equation.

Place the resistor adjacent to the BLNK pin when it is used.

CLS

Connect a resistor from CLS to V

to program the classification current per IEEE 802.3-2005 and preliminary

SS

802.3at specifications. The PD power ranges and corresponding resistor values are listed in Table 2 . The power
assigned should correspond to the maximum average power drawn by the PD during operation. The TPS23753
supports class 0 – 3 power levels.

CS

The current sense input for the dc/dc converter should be connected to the high side of the switching MOSFET ’ s
current sense resistor. The current-limit threshold, V

, defines the voltage on CS above which the GATE ON

CSMAX

time will be terminated regardless of the voltage on CTL.

(1)

(2)

(3)

The TPS23753 provides internal slope compensation to stabilize the current mode control loop. If the provided
slope is not sufficient, the effective slope may be increased by addition of R

per Figure 22 .

S

Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.

CTL

CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling V
to stop switching. Increasing V
maximum (peak) current is requested at approximately V

above V

CTL

raises the switching MOSFET programmed peak current. The

ZDC

+ (2 × V

ZDC

). The ac gain from CTL to the PWM

CSMAX

below V

CTL

causes GATE

ZDC

comparator is 0.5.
Use V

as a pull up source for CTL.

B

DEN

Connect a 24.9 k Ω resistor from DEN to V
impedance state when not in the detection voltage range. Pulling DEN to V

to provide the PoE detection signature. DEN goes to a high

DD

during powered operation causes

SS

the internal hotswap MOSFET and class regulator to turn off.

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7

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15000

( )

( )

FRS

SW

R k

f kHz

Ω =

TPS23753

SLVS853A – JUNE 2008 – REVISED JUNE 2008 ..............................................................................................................................................................

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FRS

Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor per the
following relationship.

The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin. More information is provided in the Applications section.

The FRS pin is high impedance. Keep the connections short and apart from potential noise sources.

GATE

Gate drive output for the dc/dc converter switching MOSFET.

RTN

RTN is internally connected to the drain of the PoE hotswap MOSFET, and the dc/dc controller return. RTN
should be treated as a local reference plane (ground plane) for the dc/dc controller and converter primary to
maintain signal integrity.

V

B

V

is an internal 5V control rail that should be bypassed by a 0.1 µ F capacitor to RTN. V

B

should be used to bias

B

the feedback optocoupler.

V

C

V

is the bias supply for the dc/dc controller. The MOSFET gate driver runs directly from VC. V

C

down from VC, and is the bias voltage for the rest of the converter control. A startup current source from V
V

is controlled by a comparator with hysteresis to implement a bootstrap startup of the converter. V

C

is regulated

B

DD1

must be

C

connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.22 µ F capacitor, located adjacent to the V

pin, should be connected from V

C

to RTN to bypass the

C

gate driver. A larger total capacitance is required for startup.

V

DD

Positive input power rail for PoE control that is derived from the PoE. V

should be bypassed to V

DD

with a 0.1

SS

µ F (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, should be connected
from V

V

DD1

Source of dc/dc converter startup current. Connect to V
from V

V

SS

V

SS

hotswap switch that connects it to RTN. V
local V

to V

DD

to support PoE priority operation.

DD

to protect against overvoltage transients.

SS

for most applications. V

DD

DD1

is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited

is clamped to a diode drop above RTN by the hotswap switch. A

reference plane should be used to connect the input components and the V

SS

SS

may be isolated by a diode

pin.

SS

(4)

to

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446

448

450

452

454

456

458

-40

-20

0

20

40

60 80 100

120

PoE-CurrentLimit-mA

T -JunctionTemperature-°C

J

0

1

2

3

4

5

6

7

8

0

2

4

6

8

10

I -BiasCurrent- A

VDD

m

V -PoEVoltage-V

VDD-VSS

T =125°C

J

T =25°C

J

T =-40°C

J

0

1

2

3

4

5

6

5 10 15 20 25 30 35 40 45 50 55 60

V =8.6V

VC

I -SourceCurrent-mA

VC

V -V

VDD1-RTN

T =-40°C

J

T =25°C

J

T =125°C

J

20

40

60

80

100

120

140

160

-40 -20 0 20 40 60 80 100 120

ConverterStartTime-ms

T -JunctionTemperature-°C

J

C =22 FVCm

V =10.2V

VDD1

V =19.2V

VDD1

V =35V

VDD1

0

100

200

300

400

500

600

700

800

900

1000

-40 -20 0 20 40 60 80 100 120

T -JunctionTemperature-°C

J

I

-Sinking- A

VC

m

GateOpen
V =12V

VC

500kHz

250kHz

100kHz

50kHz

V =0V

CTL

0

200

400

600

800

1000

1200

7

9 11

13

15 17

V -ControllerBiasVoltage-V

C

V -ControllerBiasCurrent- A

C

m

GateOpen
T =25°C

J

500kHz

250kHz

100kHz

50kHz

V =0V

CTL

TPS23753

www.ti.com

.............................................................................................................................................................. SLVS853A – JUNE 2008 – REVISED JUNE 2008

TYPICAL CHARACTERISTICS

DETECTION BIAS CURRENT PoE CURRENT LIMIT

CONVERTER START TIME CONVERTER STARTUP SOURCE CURRENT

vs vs

VOLTAGE TEMPERATURE

Figure 3. Figure 4.

vs vs

TEMPERATURE V

VDD1

Figure 5. Figure 6.

CONTROLLER BIAS CURRENT CONTROLLER BIAS CURRENT

TEMPERATURE VOLTAGE

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 7. Figure 8.

vs vs

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