Texas Instruments TPS2359RHHT, TPS2359 Datasheet
R
SEN SE
OUT3A
SDA
SUM3A
SUM12 A
IN3A
TPS2359
36 QFN
OUT3B
3v 3in
A1
R
SUM3B
SUM3B
R
SUM12B
SUM12 B
VDD3B
R
SEN SE
IN12B
COMMON
CIRCUITRY
3v 3in
12 V in
12 V in
IN12A
IN3B
VDD3A
AGND
GNDA
COMMON
CIRCUITRY
EN3B
VINT
EN3A
A0
A2
SCL
R
SET A
GNDB
SENMA PASSA OUT12ASETA BLKASENPA
SENMB PASSB OUT12BSETB BLKBSENPB
IRPT\
R
SUM3A
R
SUM12A
R
SET B
AdvancedMC™
12 V
3.3 V
Slot A
Slot B
AdvancedMC™
12 V
3.3 V
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
TPS2359 Full Featured Dual-Slot AdvancedMC™ Controller
1
FEATURES
2
• ATCA AdvancedMC™ Compliant
• Full Control for Two AdvancedMC™ Modules
• Independent 12-V Current Limit and Fast Trip
• 3.3-V and 12-V FET ORing for MicroTCA™
• Internal 3.3-V Current Limit and ORing
• Power Good and Fault Reporting Through I2C
• I2C Programmable Fault Times and Current
Limits
• FET Status Bits for all Channels
• 36-Pin PQFN Package
APPLICATIONS
• ATCA Carrier Boards
• MicroTCA™ Power Modules
• AdvancedMC™ Slots
• Systems Using 12 V and 3.3 V
• Base Stations
DESCRIPTION
The TPS2359 dual-slot hot-plug controllers perform
all necessary power interface functions for two
AdvancedMC™ (Advanced Mezzanine Card)
modules.
Two fully integrated 3.3-V channels provide inrush
control, over-current protection, and FET ORing. Two
12-V channels provide the same functions using
external FETs and sense resistors. The 3.3-V current
limits are factory set to AdvancedMC™ compliant
levels and the 12-V current limits are programmed
using external sense resistors. The accurate current
sense comparators of the TPS2359 satisfy the narrow
ATCA™ AdvancedMC™ current limit requirements.
TPS2359 Application Diagram
1
2 AdvancedMC, MicroTCA are trademarks of PICMG.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
ORDERING INFORMATION
DEVICE TEMPERATURE PACKAGE
TPS2359 -40 ° C to 85 ° C QFN36 TPS2359RHH
(1) Add an R suffix to the device type for tape and reel.
(2) For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI
Web site at www.ti.com .
ABSOLUTE MAXIMUM RATINGS
(1)
(1)
(2)
ORDERING INFORMATION
www.ti.com
over operating free-air temperature range (unless otherwise noted)
PARAMETER VALUE UNIT
PASSx, BLKx 0 to 30
IN12x; OUT12x; SENPx; SENMx; SETx; IRPT 0 to 17
IN3x; OUT3x; EN3x; VDDx; SUMx; SDA, SCL 0 to 5 V
AGND, GNDx -0.3 to 0.3
A0, A1, A2 0 to VINT
SUMx 5
VINT -1 to 1 mA
OUT3x Internally limited
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is
neither implied nor guaranteed. Exposure to absolute maximum rated conditions for extended periods of time may affect device
reliability.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
TEST METHOD MIN UNITS
Human Body Model (HBM) 2
Charged Device model (CDM) 0.5
DISSIPATION RATINGS
PACKAGE θ JA - Low-k ( ° C/W) θ JA - High-k ( ° C/W) TA= 85 ° C POWER RATING (mW)
36 QFN 35
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
V
IN12x
V
IN3x
V
VDD3x,3
I
OUT3x
I
SUMx
T
J
Payload power input voltage 8.5 12 15
Management power input voltage 3 3.3 4 V
Management power supply voltage 3 3.3 4
Management power output current 165 mA
Summing pin current 100 1000
PASSx pin board leakage current -1 1
VINT bypass capacitance 1 10 250 nF
Operating junction temperature range -40 125 ° C
kV
µ A
2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
TPS2359
www.ti.com
ELECTRICAL CHARACTERISTICS
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
(1)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 k Ω to ground. SUM3A = SUM3B = 3.3 k Ω to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ENABLE Inputs
Threshold voltage, falling edge 1.2 1.3 1.4 V
Hysteresis
Pullup current2 EN3x = 0 V 5 8 15
Input bias current EN3x = 5 V 1 5
3.3-V turn off time EN3x deasserts to V
12-V turn off time 20
VINT
Output voltage 0 < I
Power GOOD Outputs
Threshold voltage V
Hysteresis mV
Fault Timer
Minimum fault time 3xFT[4:0] = 12xFT[4:0] = 00001B 1
Fault time bit weight 0.5
Timer duty cycle = (fault time) / (retry period) 1.4% 1.5% 1.6%
12-V Summing node
Input referred offset – 2 2 mV
Summing threshold 12xCL[3:0] = 1111B, VPASSx = 15 V 0.66 0.675 0.69 V
Leakage current VSETx = VSENMx – 10 mV 1 µ A
12-V Current limit
Current limit threshold and measure V
Sink current in current limit V
Fast trip threshold Measure V
Fast turn-off delay
Bleed down resistance V
Bleed down threshold 75 100 130 mV
Timer start threshold V
(1) When setting an address bit to a logic 1 the pin should be connected to VINT.
(2) Not production tested.
(2)
EN3x deasserts to V
Q
= 35 nF
GATE
< 50 µ A 2 2.3 2.8 V
VINT
< 1.0 V, C
OUT3x
< 1.0 V, C
OUT12x
= 0 µ F 10
OUT
= 0 µ F,
OUT
20 50 80 mV
12xPG, falling OUT12x 10.2 10.5 10.8
3xPG, falling OUT3x 2.7 2.8 2.9
12xPG, measured at OUT12x 130
3xPG, measured at OUT3x 50
V
= 10.8 – 13.2 V, V
SENMx
mV, measure V
R
= 6.8 k Ω , R
SUMx
V
= 1 V, V
SUMx
(2)
20-mV overdrive, C
OUT
PASSx
SENPx
= 6 V 1.1 1.6 2.1 k Ω
– V
INx
– V
SETx
= 422 Ω , increase I
SETx
– V
SENPx
= 12 V, measure I
PASSx
– V
SENMx
PASSx
when fault timer starts 5 6 7 V
SENPx
SENMx
SENMx
= 0 pF, t
= V
when V
+ 50
SENMx
LOADx
= 15 47.5 50 52.5 mV
PASSx
PASSx
20 40 µ A
80 100 120 mV
p50-50
200 300 ns
µ A
µ s
ms
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2359
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 k Ω to ground. SUM3A = SUM3B = 3.3 k Ω to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNITS
12-V UVLO
UVLO rising IN12x rising 8.1 8.5 8.9
UVLO hysteresis IN12x falling 0.44 0.5 0.59
12-V BLOCKING
Turn-on threshold Measure V
Turn-off threshold Measure V
Turn-off delay
(3)
20-mV overdrive, C
12-V Gate drivers (PASSx, BLKx)
Output voltage V
Sourcing current V
Sinking current
= V
INx
OUTx
= V
IN12x
Fast turnoff, V
Sustained, V
Pulldown resistance In OTSD (at 150 ° C) 14 20 26 k Ω
Fast turnoff duration
Safety gate pulldown
Startup time
(3)
(3)
(3)
IRF3710, slew S or D 15 V in 1 ms 1.25 V
IN12x rising to PASSx and BLKx sourcing 0.25 ms
3.3-V Summing node
Summing threshold 655 675 695 mV
3.3-V Current limit
On resistance I
Current limit R
= 150 mA 290 500 m Ω
OUT3x
= 3.3 k Ω , V
SUM3x
Fast trip threshold 240 300 400
Fast turn-off delay
Bleed down resistance V
(3)
I
= 400 mA, t
OUT3x
= 1.65 V 280 400 500 Ω
OUT3x
Bleed down threshold 75 100 130 mV
3.3-V UVLO
UVLO rising IN3x rising 2.65 2.75 2.85 V
UVLO hysteresis IN3x falling 200 240 300 mV
3.3-V Blocking
Turn-on threshold Measure V
Turn-off threshold Measure V
V
= 3.3 V, V
IN3x
ORing turn-on delay 300 350 µ s
GND, 3ORON = 1. Remove 3.5 V from OUT3x.
Measure time from V
3.2 V
Fast turnoff delay
(3)
20 mV overdrive, t
(3) Not production tested.
– V
SENPx
SENPx
OUTx
– V
OUTx
= 0 pF, t
BLKx
p50-50
5 10 15
– 6 – 3 0
200 300 ns
= 10 V 21.5 23 24.5 V
= 10 V, V
OUT12x
= V
PASSx
PASSx
BLKx
= V
BLKx
= V
PASSx
= 17 V 20 30 40 µ A
BLKx
= 14 V 0.5 1 A
= 4 – 25 V 10 14 20 mA
5 10 15 ms
= 0 V 170 195 225
OUT3x
p50-50
– V
IN3x
OUT3x
– V
IN3x
OUT3x
= 3.5 V, OUT3x = 100 Ω to
OUT3x
thru 2.9 V to V
OUT3x
p50-50
=
OUT3x
5 10 15
– 6 – 3 0
750 1300 ns
250 350 ns
V
mV
mA
mV
4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
SIGNAL ANDPINNAMING
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 k Ω to ground. SUM3A = SUM3B = 3.3 k Ω to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Currents (I
All channels enabled I
All channels disabled 2.0 2.8
Thermal Shutdown
Whole-chip shutdown temperature
3.3-V channel shutdown
temperature
Hysteresis
(4)
(4)
Serial Interface (SDA, SCL, A0 – 2, IRPT
Lower logic threshold A0 – A2 0.33 0.35 0.37
Upper logic threshold A0 – A2 1.32 1.35 1.38
Input pullup resistance A0 – A2, V
Input pulldown resistance A0 – A2, V
Input open-circuit voltage IAx = 0 V 0.5 0.8 1.0
Threshold voltage, rising SDA, SCL 2.3 V
Threshold voltage, falling SDA, SCL 1.0
Hysteresis
(4)
Leakage SDA, IRPT 1 mA
(4) Not production tested.
+ I
INx
+ I
SENPx
SENMx
(4)
+ I
SETx
OUT3A
TJrising, I
TJrising, I
+ I
)
VDDx
= I
= 0 3.1 4
OUT3B
= I
OUT3A
or I
OUT3A
= 0 140 150
OUT3B
in current limit 130 140 ° C
OUT3B
Whole chip or 3.3-V channel 10
= 0 V 400 700 1000
Ax
= VINT 200 350 550
Ax
SDA, SCL 165 mV
mA
V
k Ω
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Signal and Pin Naming Convention
Product Folder Link(s): TPS2359
+
+
+
+
+
R
SEN SE
100mv
vthoc - 675 mv nominal
Q
Pump
Vcp
~25 V
Fault
Timer
Vcp
30 uA
12dis
10 us
R
SUM
6800 W
FLT
10 mv
-3 mv
SQQ
R
PG\
10 us
pgat\
ogat
ogat
OUT12xBLKxPASSxSETx SENMxSENPx
100
us
12xIN
OUT
vpg
OUT pgat\
oren
+
30 uA
R
SET
EN\
SUM12x
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
www.ti.com
DEVICE INFORMATION
TPS2359 BLOCK DIAGRAMS
Figure 1. Payload Power Channel (two channels per device)
6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
+
+
+
+
0.1 W
30 mv
vthoc - [ 675 mv nominal ]
Fault
Timer
vcpx
R
SU M
3300
FLT \ to I2C
10 mv
-3 mv
SQQ
R
PG\ to I2C
OUT3xIN3x
OUT3x
+
30 uA
245 W
Q
Pump
vcpx
~25 v
VDD3x
+
30 us
2.8 V
gat
EN3x
gat
en
en
30 us
12dis
Control
fromI
2
C
SUM3x
Selector
IN12A
en
V
INT
IN12B
IN3A
IN3B
OUT12A
OUT12B
OUT3A
OUT3B
PREREG
Trim
NVM
SDA
AGND
GNDA
2.2V
POR
por
GNDB
I2C
SCL
A0-2
IRPT\
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
Management Power Channel (two channels per device)
Common Circuitry
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2359
IN12A
SENPA
SENMA
SDA
VDD3A
12B
3A
SETA
VINT
SUM12A
IN3A
A2
SCL
SUM3A
IN12B
SENPB
SENMB
PASSB
SETB
IRPT\
BLKB
IN3B
SUM3B
OUT12B
VDD3B
OUT3A
A1
OUT3BSUM12B
BLKA
OUT12A
36 Pin QFN
PASSA
GNDB
1
6
5
4
3
2
9
8
7
10 11 12 13 14 15 16 17 18
27
22
23
24
25
26
19
20
21
36 35 34 33 32 31 30 29 28
EN3B
A0
EN3A
12A
3B
I2C
AGND
GNDA
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
www.ti.com
Top View 36-Pin QFN
8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
TPS2359 TERMINAL FUNCTIONS
PIN # NAME TYPE DESCRIPTION
1 IN12A V
DD
2 SENPA I 12A input sense
3 SETA I 12A current limit set
4 SENMA I 12A current limit sense
5 VINT I/O Bypass capacitor connection point for internal supply, pullup for A0 – A2
6 SUM12A I/O 12A summing node
7 SDA I/O Serial data input/output
8 SCL I Serial data clock
9 SUM12B I/O 12B summing node
10 BLKB O 12B blocking transistor gate drive
11 OUT12B I/O 12B output
12 GNDB GND 12B power ground
13 PASSB O 12B pass transistor gate drive
14 SENMB I 12B current limit sense
15 SETB I 12B current limit set
16 SENPB I 12B input sense
17 IN12B V
18 IN3B V
DD
DD
19 OUT3B I/O 3B output
20 A1 I I2C address programming bit, LSB+1
21 SUM3B I/O 3B summing node
22 VDD3B V
DD
23 AGND GND Analog ground
24 IRPT O Active low interrupt, asserts when a PG deasserts or when a FLT\ asserts
25 SUM3A I/O 3A summing node
26 A2 I I2C address programming bit, LSB+2
27 OUT3A I/O 3A output
28 IN3A V
29 VDD3A V
DD
DD
30 EN3B I 3B enable, active high
31 EN3A I 3A enable, active high
32 PASSA O 12A pass transistor gate drive
33 GNDA GND 12A power ground
34 OUT12A I/O 12A output
35 BLKA O 12A blocking transistor gate drive
36 A0 I I2C address programming bit, LSB
12A input
12B input
3B input
3B charge pump input
3A input
3A charge pump input
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2359
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
www.ti.com
DETAILED PIN DESCRIPTION
A0, A1, A2 These three pins select one of 27 unique I2C addresses for address of the TPS2359. Each pin may
be tied to ground, tied to the VINT pin, or left open. See TPS2359 I2C Interface section for details.
AGND Ground pin for analog circuitry inside the TPS2359.
BLKx Gate drive pin for the 12x channel BLK FET. This pin sources 30 µ A to turn the FET on. An internal clamp
prevents this pin from rising more than 14.5 V above OUT12x. Setting the ORENx bit low holds the BLKx pin
low.
EN3x Active-high enable input. Pulling this pin low turns off channel 3x by pulling the gate of the internal pass
FET to GND. An internal 200-k Ω resistor pulls this pin up to VINTwhen disconnected.
GNDx Ground pin for power circuitry associated with the 12x channel. These pins should connect to a ground
plane shared with the AGND pin.
IN12x Supply pin for channel 12x internal circuitry.
IN3x Supply pin for channel 3x internal pass FET.
IRPT Open drain output that pulls low when internal circuitry sets any of the eight status bits in Register 7.
Reading Register 7 restores IRPT to its high-Z state.
OUT12x Senses the output voltage of the channel 12x path.
OUT3x Output of the channel 3x internal pass FET.
PASSx Gate drive pin for the 12x channel PASS FET. This pin sources 30 µ A to turn the FET on. An internal
clamps prevents this pin from rising more than 14.5 V above IN12x.
SCL Serial clock input for the I2C interface. For details of the SCL line, see TPS2359 I2C Interface section.
SDA Bidirectional I2C data line. For details of the SDA line, see TPS2359 I2C Interface section for details.
SENMx Senses the voltage on the low side of the channel 12x current sense resistor.
SENPx Senses the voltage on the high side of the channel 12x current sense resistor.
SETx A resistor connected from this pin to SENPx sets the current limit level in conjunction with the current
sense resistor and the resistor connected to the SUM12x pin, as described in 12-V thresholds – setting current
limit and fast over current trip section.
SUMx A resistor connected from this pin to ground forms part of the channel x current limit. As the current
delivered to the load increases, so does the voltage on this pin. When the voltage on this pin reaches a threshold
(by default 675 mV), the current limit amplifier acts to prevent the current from further increasing.
VDD3x Supply pin for channel3x internal circuitry.
VINT This pin connects to the internal 2.35-V rail. A 0.1- µ F capacitor must be connected from this pin to ground.
One can connect the A0 – A2 pins to this supply to pull them high, but no other external circuitry should connect to
VINT.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
12V VDD vs IDD @ 25C
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
10 11 12 13 14
VDD
IDD (mA)
3V Channel ORing Turn On Threshold
8.00
9.00
10.00
11.00
12.00
-50 0 50 100 150
Temperature De grees C
mV
3V Channel ORing Turn Off Thre shold
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
-50 0 50 100 150
Temperature C Degree s
mV
12 V Fast Curr ent Limit Thres hold
50.00
50.20
50.40
50.60
50.80
51.00
-50 0 50 100 150
Temperature De grees C
mV
3.3V IDD Vs Tem pe rature
0.2
0.21
0.22
0.23
0.24
0.25
0.26
-50 0 50 100 150
Temperature Degree s C
IDD (mA)
12V Channel ORing Turn Off Thre shold
-5.0 0
-4.0 0
-3.0 0
-2.0 0
-1.00
0.00
-50 0 50 100 150
Temperature De gree C
mV
12V Cur re nt (mA) Vs Te mper ature
2
2.1
2.2
2.3
2.4
-50 0 50 100 150
Temperature Degree s C
Current (mA)
6
12V Channel ORing Turn On Thr eshold
8.00
8.50
9.00
9.50
10.00
10.50
11.0 0
11.50
12.00
-50 0 50 10 0 150
Temperature De grees C
mV
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS
Figure 2. Figure 3.
Figure 4. Figure 5.
Figure 6. Figure 7.
Figure 8. Figure 9.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS2359
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
TYPICAL CHARACTERISTICS (continued)
Figure 10. OUT3A Startup Into 22- Ω (150 mA) 150- µ F Load Figure 11. OUT3A Load Stepped from 165 mA to 240 mA
www.ti.com
Figure 12. OUT3A Short Circuit Under Full Load (165 mA) Figure 13. OUT3A Short Circuit Under Full Load (165 mA)
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Zoom View Wide View
Product Folder Link(s): TPS2359
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)
Figure 14. OUT3A Startup Into Short Circuit Figure 15. OUT12A Startup Into 500- Ω , 830- µ F Load
Figure 16. OUT12A Startup Into 80-Watt, 830- µ F Load Figure 17. OUT12A Short Circuit Under Full Load (6.7 A)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2359
Wide View
TPS2359
SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008 ................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 18. OUT12A Short Circuit Under Full Load (6.7 A) Figure 19. OUT12A Startup Into Short Circuit
Zoom View
Figure 20. OUT12A Overloaded While Supplying 6.7 A
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
TPS2359
www.ti.com
................................................................................................................................................ SLUS792A – FEBRUARY 2008 – REVISED MARCH 2008
REFERENCE INFORMATION
The TPS2359 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0
specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group
(PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication
Computing Architecture) specification originally released in December, 2002.
PICMG-AMC Highlights
• AMC - Advanced Mezzanine Cards
• Designed to Plug into ATCA Carrier Boards
• AdvancedMC™ Focuses on Low Cost
• 1 to 8 AdvancedMC™ per ATCA Carrier Board
• 3.3-V Management Power – Maximum Current Draw of 150 mA
• 12-V Payload Power – Converted to Required Voltages on AMC
• Maximum 80-W Dissipation per AdvancedMC™
• Hotswap and Current Limiting Must Be Present on Carrier Board
• For Details, see www.picmg.org/v2internal/AdvancedMC.htm
PICMG-MTCA Highlights
• MTCA – MicroTelecommunications Computing Architecture
• Architecture for Using AMCs Without an ATCA Carrier Board
• Up to 12 AMCs per System, Plus Two MCHs, Plus Two CUs
• Focuses on Low Cost
• All functions of ATCA Carrier Board Must Be Provided
• MicroTCA is Also Known as MTCA, mTCA, or uTCA For Details, see
www.picmg.org/v2internal/microTCA.htm
Control and Status Registers
Ten 8 bit registers are used to control and read the status of the TPS2359. Registers 0 and 1 control the 12A
channel and register 2 controls the 3A channel. Similarly, registers 3 and 4 control the 12B channel and register
5 controls the 3B channel. Register 6 contains eight general configuration bits. Read-only registers 7, 8, and 9
report back system status to the I2C controller. All ten registers use the I2C protocol and are organized as
follows:
Table 1. Top Level Register Functions
REG R/W SLOT VOLTAGE FUNCTION
0 R/W A 12 Set current limit, power good threshold, and OR functions of 12A.
1 R/W A 12 Set fault time, enable, and bleed down functions of 12A.
2 R/W A 3.3 Set fault time, enable, and bleed down functions of 3A.
3 R/W B 12 Set current limit, power good threshold, and OR functions of 12B.
4 R/W B 12 Set fault time, enable, and bleed down functions of 12B.
5 R/W B 3.3 Set fault time, enable, and bleed down functions of 3B.
6 R/W A, B 3.3, 12 System configuration controls.
7 R A, B 3.3, 12 Fault and PG outputs for 3A, 12A, 3B, 12B – these bits set IRPT.
8 R A, B 12 Over current and fast trip latches for 3A, 12A, 3B, 12B.
9 R A, B 3.3, 12 Channel status indicators for 3A, 12A, 3B, 12B.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2359
Loading...