Datasheet TPS2321IPWR, TPS2321IPW, TPS2321IDR, TPS2321ID, TPS2320IPWR Datasheet (Texas Instruments)

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Dual-Channel High-Side MOSFET Drivers

D

IN1: 3 V to 13 V; IN2: 3 V to 5.5 V

D

Inrush Current Limiting With dv/dt Control

D

Independent Circuit-Breaker Control With
Programmable Current Limit and Transient
Timer

D

CMOS- and TTL-Compatible Enable Input

D

Low, 5-µA Standby Supply Current ...Max

D

Available in 16-Pin SOIC and TSSOP
Package

D

–40°C to 85°C Ambient Temperature Range

D

Electrostatic Discharge Protection

applications

D

Hot-Swap/Plug/Dock Power Management

D

Hot-Plug PCI, Device Bay

D

Electronic Circuit Breaker

description

The TPS2320 and TPS2321 are dual-channel
hot-swap controllers that use external N-channel
MOSFETs as high-side switches in power
applications. Features of these devices, such as
overcurrent protection (OCP), inrush-current
control, and separation of load transients from
actual load increases, are critical requirements for
hot-swap applications.

The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Each
internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully
enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the
MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the
ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have
high peak currents during power-state transitions, to disregard transients for a programmable period.

AVAILABLE OPTIONS

PIN

PACKAGES

TAHOT-SWAP CONTROLLER DESCRIPTION

COUNT

ENABLE ENABLE

Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPW

–40°C to 85°C

Dual-channel with independent OCP 16

TPS2320ID
TPS2320IPW

TPS2321ID
TPS2321IPW

Single-channel with OCP and adjustable PG 14

TPS2330ID
TPS2330IPW

TPS2331ID
TPS2331IPW

†

The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2321IPWR).

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

typical application

NOTE: Terminal 14 is active high on TPS2321.

VREG

IN1

ISET1

ISENSE1

GATE1

DISCH1

FAULT

TIMER

DISCH2

GATE2

ISENSE2ISET2IN2

ENABLE

DGND

AGND

V2

V1

3 V – 5.5 V

3 V – 13 V

TPS2320

+

V

O1

V

O2

+

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

GATE1
GATE2

DGND

TIMER

VREG

AGND
ISENSE2
ISENSE1

DISCH1
DISCH2
ENABLE
FAULT
ISET1
ISET2
IN2
IN1

D OR PW PACKAGE

(TOP VIEW)

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

PREREG

UVLO and
Power-Up

IN1 ISET1 ISENSE1 GATE1

Clamp

Charge

Pump

75 µA

Pulldown FET
Circuit Breaker

dv/dt Rate
Protection

DISCH1

Logic

FAULT

TIMER

Second Channel

GATE2ISENSE2ISET2IN2

DISCH2

Circuit
Breaker

VREG

50-µs Deglitch

AGND

DGND

ENABLE

50 µA

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 6 I Analog ground, connects to DGND as close as possible
DGND 3 I Digital ground
DISCH1 16 O Discharge transistor 1
DISCH2 15 O Discharge transistor 2
ENABLE/ ENABLE 14 I Active low (TPS2320) or active high enable (TPS2321)
FAULT 13 O Overcurrent fault, open-drain output
GATE1 1 O Connects to gate of channel 1 high-side MOSFET
GATE2 2 O Connects to gate of channel 2 high-side MOSFET
IN1 9 I Input voltage for channel 1
IN2 10 I Input voltage for channel 2
ISENSE1 8 I Current-sense input channel 1
ISENSE2 7 I Current-sense input channel 2
ISET1 12 I Adjusts circuit-breaker threshold with resistor connected to IN1
ISET2 11 I Adjusts circuit-breaker threshold with resistor connected to IN2
TIMER 4 O Adjusts circuit-breaker deglitch time
VREG 5 O Connects to bypass capacitor, for stable operation

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel

MOSFET transistors connected to GA TE1 and GA TE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate
voltage-clamp circuitry.

ENABLE

or ENABLE – ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the

controller is enabled, both GA TE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than
5 µA.

FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V , the overcurrent channel latches off and pulls F AUL T low . The
other channel will run normally if not in overcurrent.

GA TE1, GA TE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to
each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If
desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.
These capacitors also reduce inrush current and protect the device from false overcurrent triggering during
powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V–12 V across the external
MOSFET transistors.

IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GA TE1 and GA TE2, respectively . The TPS2320/TPS2321 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation

ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2,
implement overcurrent sensing for GA TE1 and GA TE2. ISET1 and ISET2 set the magnitude of the current that
generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current
source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2,
which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load
current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled
below ISET2.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V , the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.

VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN1. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be
connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However , the voltage
on VREG must be less than 5.5 V.

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Input voltage range: V

I(IN1)

, V

I(ISENSE1)

, V

I(ISET1)

, V

I(ENABLE)

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . .

V

I(IN2)

, V

I(ISENSE2)

, V

I(ISET2)

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range: V

O(GATE1)

–0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V

O(GATE2)

–0.3 V to 22V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V

O(DISCH1)

, V

O(FAULT)

, V

O(VREG)

, V

O(DISCH2)

, V

O(TIMER)

, –0.3 V to 15V. . . . .

Sink current range: I

GATE1

, I

GATE2

, I

DISCH1

, I

DISCH2

0 mA to 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

TIMER

, I

FAUL T

0 mA to 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are respect to DGND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

PW-16 823 mW 10.98 mW/°C 329 mW 165 mW

D-16 674 mW 8.98 mW/°C 270 mW 135 mW

recommended operating conditions

MIN NOM MAX UNIT

p

V

I(IN1)

, V

I(ISENSE1)

, V

I(ISET1)

3 13

Input voltage, V

I

V

I(IN2)

, V

I(ISENSE2)

, V

I(ISET2)

3 5.5

V

VREG voltage, V

O(VREG)

, when VREG is directly connected to IN1 2.95 5.5 V

Operating virtual junction temperature, T

J

–40 100 °C

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ V

I(IN1)

≤13 V, 3 V ≤ V

I(IN2)

≤ 5.5 V (unless otherwise noted)

general

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

I(IN1)

Input current, IN1 V

I(ENABLE)

= 5 V (TPS2321), 0.5 1 mA

I

I(IN2)

Input current, IN2 V

I(ENABLE)

= 0 V (TPS2320) 75 200 µA

Standby current (sum of currents into IN1, IN2,

V

I(ENABLE)

= 0 V (TPS2321),

I

I(stby)

y(

ISENSE1, ISENSE2, ISET1, and ISET2)

V

I(ENABLE)

= 5 V (TPS2320)

5

µA

GATE1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

G(GATE1_3V)

V

I(IN1)

= 3 V 9 11.5

V

G(GATE1_4.5V)

Gate voltage

I

I(GATE1)

=

500 nA

,

DISCH1 open

V

I(IN1)

= 4.5 V 10.5 14.5

V

V

G(GATE1_10.8V)

DISCH1 oen

V

I(IN1)

= 10.8 V 16.8 21

V

C(GATE1)

Clamping voltage, GATE1
to DISCH1

9 10 12 V

I

S(GATE1)

Source current, GATE1

3 V ≤ V

I(IN1)

≤ 13.2 V, 3 V ≤ V

O(VREG)

≤ 5.5 V,

V

I(GATE1)

= V

I(IN1)

+ 6 V

10 14 20 µA

Sink current, GATE1

3 V ≤ V

I(IN1)

≤ 13.2 V, 3 V ≤ V

O(VREG)

≤ 5.5 V,

V

I(GATE1)

= V

I(IN1)

50 75 100 µA

V

I(IN1)

= 3 V 0.5

t

r(GATE1)

Rise time, GATE1 Cg to GND = 1 nF (see Note 2)

V

I(IN1)

= 4.5 V 0.6

ms

()

g

V

I(IN1)

= 10.8 V 1

V

I(IN1)

= 3 V 0.1

t

f(GATE1)

Fall time, GATE1 Cg to GND = 1 nF (see Note 2)

V

I(IN1)

= 4.5 V 0.12

ms

()

g

V

I(IN1)

= 10.8 V 0.2

GATE2

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

G(GATE2_3V)

p

V

I(IN2)

= 3 V 9 11.7

V

G(GATE2_4.5V)

Gate voltage

I

I(GATE2)

=

500 nA, DISCH2 oen

V

I(IN2)

= 4.5 V 10.5 14.7

V

V

C(GATE2)

Clamping voltage,
GATE2 to DISCH2

9 10 12 V

I

S(GATE2)

Source current,
GATE2

3 V ≤ V

I(IN2)

≤ 5.5 V, 3 V ≤ V

O(VREG)

≤ 5.5 V,

V

I(GATE2)

= V

I(IN2)

+ 6 V

10 14 20 µA

Sink current, GATE2

3 V ≤ V

I(IN2)

≤ 5.5 V, 3 V ≤ V

O(VREG)

≤ 5.5 V,

V

I(GATE2)

= V

I(IN2)

50 75 100 µA

C

to GND = 1 nF

V

I(IN2)

= 3 V 0.5

t

r(GATE2)

Rise time, GATE2

g

(see Note 2)

V

I(IN2)

= 4.5 V

0.6

ms

Cg to GND = 1 nF

V

I(IN2)

= 3 V

V

O(VREG)

= 3

V

0.1

t

f(GATE2)

Fall time, GATE2

g

(see Note 2)

V

I(IN2)

= 4.5 V 0.12

ms

NOTE 2: Specified, but not production tested.

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ V

I(IN1)

≤13 V, 3 V ≤ V

I(IN2)

≤ 5.5 V ( unless otherwise noted) (continued)

TIMER

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OT(TIMER)

Threshold voltage, TIMER 0.4 0.5 0.6 V
Charge current, TIMER V

I(TIMER)

= 0 V 35 50 65 µA

Discharge current, TIMER V

I(TIMER)

= 1 V 1 2.5 mA

circuit breaker

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IT(CB)

Undervoltage voltage, circuit breaker R

ISETx

= 1 kΩ 40 50 60 mV

I

IB(ISENSEx)

Input bias current, I

SENSEx

0.1 5 µA

V

O(GATEx)

= 4 V 400 800

Discharge current, GATE

x

V

O(GATEx)

= 1 V

25 150

mA

t

pd(CB)

Propagation (delay) time, comparator inputs to
gate output

Cg = 50 pF,
(50% to 10%)

10 mV overdrive,
C

O(timer)

= 50 pF

1.3 µs

ENABLE, active low (TPS2320)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IH(ENABLE)

High-level input voltage, ENABLE 2 V

V

IL(ENABLE

)

Low-level input voltage, ENABLE 0.8 V

R

I(ENABLE

)

Input pullup resistance,
ENABLE

See Note 3 100 200 300 kΩ

t

d_off(ENABLE)

Turnoff delay time, ENABLE

V

I(ENABLE)

increasing above stop threshold; 100

ns rise time, 20 mV overdrive (see Note 2)

60 µs

t

d_on(ENABLE)

Turnon delay time, ENABLE

V

I(ENABLE

)

decreasing below start threshold;

100 ns fall time, 20 mV overdrive (see Note 2)

125 µs

NOTES: 2. Specified, but not production tested.

3. Test IO of ENABLE

at V

I(ENABLE

)

= 1 V and 0 V, then R

I(ENABLE)

=

1V

I

O_

0V

*

I

O_

1V

ENABLE, active high (TPS2321)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IH(ENABLE)

High-level input voltage, ENABLE 2 V

V

IL(ENABLE)

Low-level input voltage, ENABLE 0.7 V

R

I(ENABLE)

Input pulldown resistance,
ENABLE

100 150 300 kΩ

t

d_on(ENABLE)

Turnon delay time, ENABLE

V

I(ENABLE)

increasing above start threshold;

100 ns rise time, 20 mV overdrive (see Note 2)

85 µs

t

d_off(ENABLE)

Turnoff delay time, ENABLE

V

I(ENABLE)

decreasing below stop threshold;

100 ns fall time, 20 mV overdrive (see Note 2)

100 µs

NOTE 2: Specified, but not production tested.

PREREG

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VREG PREREG output voltage 4.5 ≤ V

I(IN1)

≤ 13 V 3.5 4.1 5.5 V

Vdrop_PREREG PREREG dropout voltage V

I(IN1)

= 3 V 0.1 V

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C),
3 V ≤ V

I(IN1)

≤13 V, 3 V ≤ V

I(IN2)

≤ 5.5 V (unless otherwise noted) (continued)

VREG UVLO

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OT(UVLOstart)

Output threshold voltage, start 2.75 2.85 2.95 V

V

OT(UVLOstop)

Output threshold voltage, stop 2.65 2.78 V

V

hys(UVLO)

Hysteresis 50 75 mV
UVLO sink current, GATEx V

I(GATEx)

= 2 V 10 mA

FAULT output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O(sat)(FAULT)

Output saturation voltage, FAULT IO = 2 mA 0.4 V

I

lkg(FAULT)

Leakage current, FAULT V

O(FAULT)

= 13 V 1 µA

DISCH1 and DISCH2

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

DISCH

Discharge current, DISCHx V

I(DISCHx)

= 1.5 V, V

I(VIN1)

= 5 V 5 10 mA

V

IH(DISCH)

Discharge on high-level input voltage 2 V

V

IL(DISCH)

Discharge on low-level input voltage 1 V

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

I(ENABLE)

5 V/div

Load 12 Ω

V

O(GATE1)

10 V/div

V

O(DISCH1)

5 V/div

t – Time – 10 ms/div

Figure 1. Turnon Voltage Transition of

Channel 1

Load 12 Ω

t – Time – 10 ms/div

Figure 2. Turnoff Voltage Transition of

Channel 1

V

O(GATE1)

10 V/div

V

O(DISCH1)

5 V/div

V

I(ENABLE

)

5 V/div

Load 5 Ω

t – Time – 10 ms/div

Figure 3. Turnon Voltage Transition of

Channel 2

V

O(GATE2)

10 V/div

V

O(DISCH2)

5 V/div

t – Time – 10 ms/div

Load 5 Ω

Figure 4. Turnoff Voltage Transition of

Channel 2

V

O(GATE2)

10 V/div

V

O(DISCH2)

5 V/div

V

I(ENABLE

)

5 V/div

V

I(ENABLE

)

5 V/div

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t – Time – 5 ms/div

V

O(GATE1)

10 V/div

V

O(FAULT)

10 V/div

I

O(OUT1)

2 A/div

Figure 5. Channel 1 Overcurrent Response:

Enabled Into Overcurrent Load

No Capacitor
on Timer

V

O(GATE1)

10 V/div

V

O(FAULT)

10 V/div

I

O(OUT1)

2 A/div

t – Time – 1 ms/div

Figure 6. Channel 1 Overcurrent Response: an

Overcurrent Load Plugged Into the Enabled Board

No Capacitor
on Timer

V

I(ENABLE

)

5 V/div

V

I(ENABLE)

5 V/div

V

O(GATE2)

10 V/div

V

O(FAULT)

10 V/div

I

O(OUT2)

2 A/div

t – Time – 2 ms/div

Figure 7. Channel 2 Overcurrent Response:

Enabled Into Overcurrent Load

No Capacitor
on Timer

t – Time – 0.5 ms/div

V

O(GATE2)

10 V/div

V

O(FAULT)

10 V/div

I

O(OUT2)

2 A/div

Figure 8. Channel 2 Overcurrent Response: an

Overcurrent Load Plugged Into the Enabled Board

No Capacitor
on Timer

V

I(ENABLE

)

5 V/div

V

I(ENABLE)

5 V/div

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t – Time – 1 ms/div

V

O(GATE1)

10 V/div

V

O(FAULT)

10 V/div

I

O(IN1)

2 A/div

Figure 9. Channel 1 – Enabled Into Short

Circuit

No Capacitor
on Timer

t – Time – 1 ms/div

V

O(GATE2)

5 V/div

V

O(FAULT)

10 V/div

I

O(IN2)

2 A/div

Figure 10. Channel 2 – Enabled Into Short Circuit

No Capacitor
on Timer

V

I(ENABLE

)

5 V/div

V

I(ENABLE

)

5 V/div

Figure 11. Channel 1 – Hot Plug

t – Time – 5 ms/div

V

I(IN1)

10 V/div

V

O(GATE1)

10 V/div

V

O(OUT1)

10 V/div

I

O(OUT1)

1 A/div

No Capacitor
on Timer

t – Time – 1 ms/div

V

I(IN1)

10 V/div

V

O(GATE1)

10 V/div

V

O(OUT1)

10 V/div

I

O(OUT1)

1 A/div

Figure 12. Channel 1 – Hot Removal

No Capacitor
on Timer

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t – Time – 5 ms/div

V

I(IN2)

5 V/div

V

O(GATE2)

10 V/div

V

O(OUT2)

5 V/div

I

O(OUT2)

1 A/div

No Capacitor
on Timer

Figure 13. Channel 2 – Hot Plug

t – Time – 1 ms/div

V

I(IN2)

5 V/div

V

O(GATE2)

10 V/div

V

O(OUT2)

5 V/div

I

O(OUT2)

1 A/div

No Capacitor
on Timer

Figure 14. Channel 2 – Hot Removal

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 15

49

46

45

43

45678910

– Input Current 1 –

50

51

SUPPLY CURRENT (ENABLED)

vs

VOLTAGE

52

11 12 13 14

48

47

44

I

I1

Aµ

VI1 – Input Voltage 1 – V

IN2 = 5.5 V

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

Figure 16

– Input Current 2 –

SUPPLY CURRENT (ENABLED)

vs

VOLTAGE

I

I2

Aµ

VI2 – Input Voltage 2 – V

70

69.5

69

68

2.5 3 3.5 4 4.5 5 5.5

70.5

71

71.5

6

68.5

IN1 = 13 v

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

Figure 17

12

10

9

7

45678910

13

14

15

11 12 13 14

11

8

– Input Current 1 – nA

SUPPLY CURRENT (DISABLED)

vs

VOLTAGE

I

I1

VI1 – Input Voltage 1 – V

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

IN2 = 5.5 V

Figure 18

17

13

7
5

2.5 3 3.5 4 4.5 5 5.5

19

21

23

6

15

9

11

– Input Current 2 – nA

SUPPLY CURRENT (DISABLED)

vs

VOLTAGE

I

I2

VI2 – Input Voltage 2 – V

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

IN1 = 13 V

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 19

16

14

12

10

2345678

– GATE1 Output Voltage – V

18

20

GATE1 VOLTAGE

vs

INPUT VOLTAGE

22

9101112

V

O

VI1 – Input Voltage1 – V

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

C

L(GATE1)

= 1000 pF

Figure 20

C

L(GATE1)

– GATE1 Load Capacitance – nF

9

6

3

0

03 6

– GATE1 Voltage Rise Time – ms

12

15

GATE1 VOLTAGE RISE TIME

vs

GATE1 LOAD CAPACITANCE

18

912

t

r

IN1 = 12 V
TA = 25°C

Figure 21

1

0

036

– GATE1 Voltage Fall Time – ms

2

3

GATE1 VOLTAGE FALL TIME

vs

GATE1 LOAD CAPACITANCE

4

912

t

f

C

L(GATE1)

– GATE1 Load Capacitance – nF

IN1 = 12 V
TA = 25°C

Figure 22

V – GATE1 Voltage

13.5

13

12

11

14 15 16 17 18 19 20

I – GATE1 Current –

14

14.5

GATE1 OUTPUT CURRENT

vs

GATE1 VOLTAGE

15

21 22 23 24

12.5

11.5

Aµ

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

IN1 = 13 V

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 23

C

(timer)

– TIMER Capacitance – nF

6

3

0

0 0.2 0.4 0.6

– Circuit Braker Response Time –

9

CIRCUIT-BREAKER RESPONSE

vs

TIMER CAPACITANCE

12

0.8 1

t

res

sµ

IN1 = 12 V
TA = 25°C

Figure 24

CL – Load Capacitance – µF

200

160

120

0

0 100 200 300

t – Discharge Time – ms

240

280

LOAD VOLTAGE 1 DISCHARGE TIME

vs

LOAD CAPACITANCE

320

400 500

80

40

IN1 = 12 V
IO1 = 0 A
TA = 25°C

Figure 25

TA – Temperature – °C

2.8

2.78

2.74

2.7
–45–35–25–15 –5 5 15

– Reference Voltage UVLO Threshold – V

2.84

2.88

UVLO START AND STOP THRESHOLDS

vs

TEMPERATURE

2.9

45 65 75 95

2.86

2.82

2.76

2.72

25 35 55 85

V

ref

Start

Stop

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

typical application diagram

Figure 26 shows a typical dual hot-swap application. The pullup resistor at FAULT should be relatively large
(e.g., 100 kΩ) to reduce power loss, unless it is required to drive a large load.

VREG

0.1 µF

IN1 ISET1

R

ISET1

ISENSE1

R

SENSE1

GATE1

DISCH1

+

FAULT

VO1 or V

O2

FAULT

TIMER

IN2 ISET2 ISENSE2 GATE2 DISCH2

ENABLE
DGND
AGND

R

ISET2

+

V

O1

V

O2

ENABLE

1 µF ∼ 10 µF

R

SENSE2

1 µF ∼ 10 µF

3 V ∼ 13 V IN1

3 V ∼ 5.5 V IN2

TPS2321

System Board

Figure 26. Typical Dual Hot-Swap Application

input capacitor

A 0.1-µF ceramic capacitor in parallel with a 1-µF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2320/01 does not need to be mounted near the connector or to these input capacitors. For applications with
more severe power environments, a 2.2-µF, or higher, ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.

output capacitor

A 0.1-µF ceramic capacitor is recommended per load on the TPS2320/21; these capacitors should be placed
close to the external FETs and to TPS2320/21. A larger bulk capacitor is also recommended on the load. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated
by the application.

external FET

To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 1. But many other MOSFETs on the market can also be used
with TPS23xx in hot-swap systems.

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 1. Some Available N-Channel MOSFETs

CURRENT RANGE

(A)

PART NUMBER DESCRIPTION MANUFACTURER

IRF7601 N-channel, r

DS(on)

= 0.035 Ω, 4.6 A, Micro-8 International Rectifier

0 to 2

MTSF3N03HDR2 N-channel, r

DS(on)

= 0.040 Ω, 4.6 A, Micro-8 ON Semiconductor

MMSF5N02HDR2 Dual N-channel, r

DS(on)

= 0.04 Ω, 5 A, SO-8 ON Semiconductor

IRF7401 N-channel, r

DS(on)

= 0.022 Ω, 7 A, SO-8 International Rectifier

MMSF5N02HDR2 N-channel, r

DS(on)

= 0.025 Ω, 5 A, SO-8 ON Semiconductor

2 to 5

IRF7313 Dual N-channel, r

DS(on)

= 0.029 Ω, 5.2 A, SO-8 International Rectifier

SI4410 N-channel, r

DS(on)

= 0.020 Ω, 8 A, SO-8 Vishay Dale

IRLR3103 N-channel, r

DS(on)

= 0.019 Ω, 29 A, d-Pak International Rectifier

5 to 10

IRLR2703 N-channel, r

DS(on)

= 0.045 Ω, 14 A, d-Pak International Rectifier

timer

For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor
should be connected between TIMER and ground. The presence of an overcurrent condition on either channel
of the TPS2320/TPS2321 causes a 50-µA current source to begin charging this capacitor. If the over­current condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321
will latch off the offending channels and will pull the F AULT pin low. The timer capacitor can be made as large
as desired to provide additional time delay before registering a fault condition.

output-voltage slew-rate control

When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with
a current of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the
gate-to-drain capacitance Cgd of the external MOSFET capacitor to a value approximating:

dvs

dt

+

15mA

C

gd

If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.

VREG capacitor

The internal voltage regulator connected to VREG requires an external capacitor to ensure stability . A 0.1-µF
or 0.22-µF ceramic capacitor is recommended.

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

gate-drive circuitry

The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:

D

A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1
or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET
source terminals to ensure proper operation of this circuitry.

D

A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gates of the external MOSFET transistors remain at a low voltage.

D

During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS
transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V . This circuitry also helps
hold the external MOSFET transistors off when power is suddenly applied to the system.

D

During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent
condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at
4 V) from the pin. Once the gate has been pulled below approximately 1.5 V , this driver is disengaged and
the UVLO driver is enabled instead. If one channel experiences an overcurrent condition and the other does
not, then only the channel that is conducting excessive current will be turned off rapidly . The other channel
will continue to operate normally.

setting the current-limit circuit-breaker threshold

Using Channel 1 as an example, the current sensing resistor R

ISENSE1

and the current-limit-setting resistor

R

ISET1

determine the current limit of the channel, and can be calculated by the following equation:

I

LMT1

+

R

ISET1

50

10

–6

R

ISENSE1

Typically R

ISENSE1

is very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the

junction of R

ISENSE1

and ISENSE1 and the junction of R

ISENSE1

and R

ISET1

are greater than 10% of the

R

ISENSE1

value, then these resistance values should be added to the R

ISENSE1

value used in the calculation

above.
The above information and calculation also apply to Channel 2. Table 2 shows some of the current sense

resistors available in the market.

T able 2. Some Current Sense Resistors

CURRENT RANGE

(A)

PART NUMBER DESCRIPTION MANUFACTURER

0 to 1 WSL-1206, 0.05 1% 0.05 Ω, 0.25 W, 1% resistor
1 to 2 WSL-1206, 0.025 1% 0.025 Ω, 0.25 W, 1% resistor
2 to 4 WSL-1206, 0.015 1% 0.015 Ω, 0.25 W, 1% resistor
4 to 6 WSL-2010, 0.010 1% 0.010 Ω, 0.5 W, 1% resistor

Vishay Dale

6 to 8 WSL-2010, 0.007 1% 0.007 Ω, 0.5 W, 1% resistor

8 to 10 WSR-2, 0.005 1% 0.005 Ω, 0.5 W, 1% resistor

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

undervoltage lockout (UVLO)

The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from
IN1 through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV.
While the undervoltage lockout is engaged, both GA TE1 and GATE2 are held low by internal PMOS pulldown
transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have
fallen to 0 V.

single-channel operation

Some applications may require only a single external MOS transistor. Such applications should use GA TE1 and
the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the
circuitry associated with the GATE2 pin.

power-up control

The TPS2320/TPS2321 includes a 500 µs (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly , the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.

3-channel hot-swap application

Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay , where dv/dt
control of 3.3 V, 5 V , and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails and
Channel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three dif ferent voltages to
three loads while monitoring the status of two of the loads.

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

V

reg

0.1 µF

IN1 ISET1

R

ISET1

ISENSE1

R

SENSE1

GATE1

DISCH1

+

FAULT

VO1 or V

O2

FAULT

TIMER

IN2 ISET2 ISENSE2 GATE2 DISCH2

ENABLE
DGND
AGND

R

ISET2

R

g1

+

V

O1

V

O2

ENABLE

1 µF ∼ 10 µF

R

SENSE2

1 µF ∼ 10 µF

12 V IN1

3.3 V IN2

TPS2321

+

V

O3

1 µF ∼ 10 µF

5 V IN3

System Board

R

g2

Figure 27. Three-Channel Application

Figure 28 shows ramp-up waveforms of the three output voltages.

V

O1

V

O3

V

O2

– Output Voltage – 2 V/div
V

O

t – Time – 2.5 ms/div

Figure 28

TPS2320, TPS2321
DUAL HOT SWAP POWER CONTROLLER
WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TPS2320, TPS2321

DUAL HOT SWAP POWER CONTROLLER

WITH INDEPENDENT CIRCUIT BREAKER

SLVS276A – MARCH 200 – REVISED APRIL 2000

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

M

0,10

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

28

9,80

9,60

24

7,90

7,70

2016

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

8

0,19

4,30

4,50

7

0,15

14

A

1

1,20 MAX

14

5,10

4,90

8

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

0°–8°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated