TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GA TE1 and GA TE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate
voltage-clamp circuitry.
ENABLE
or ENABLE – ENABLE for TPS2300 is active low. ENABLE for TPS2301 is active high. When the
controller is enabled, both GA TE1 and GATE2 voltages will power up to turn on the external MOSFET s. When
the ENABLE pin is pulled high for TPS2300 or the ENABLE pin is pulled low for TPS2301 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V , the overcurrent channel latches off and pulls this pin low . The
other channel will run normally if not in overcurrent.
GA TE1, GA TE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to
each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If
desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.
These capacitors also reduce inrush current and protect the device from false overcurrent triggering during
powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V–12 V across the external
MOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GA TE1 and GA TE2, respectively . The TPS2300/TPS2301 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2,
implement overcurrent sensing for GA TE1 and GA TE2. ISET1 and ISET2 set the magnitude of the current that
generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current
source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2,
which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load
current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled
below ISET2.
PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1
and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage
condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense
circuit incorporates a 20-µs deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V),
PWRGDx will be active low to indicate an undervoltage condition on the power-rail voltage.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V , the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN1. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be
connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However , the voltage
on VREG must be less than 5.5 V.