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TPS2300IPW
Datasheet
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Texas Instruments TPS2301EVM-153, TPS2300IPWR, TPS2300IPW, TPS2301IPWR, TPS2301IPW Datasheet

TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
Dual-Channel High-Side MOSFET Drivers
IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
Inrush Current Limiting With dv/dt Control
Circuit-Breaker Control With Programmable Current Limit and Transient Timer
Power-Good Reporting With Transient Filter
CMOS- and TTL-Compatible Enable Input
Low, 5-µA Standby Supply Current ...Max
Available in 20-Pin TSSOP Package
–40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
applications
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
description
The TPS2300 and TPS2301 are dual-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush current control, output-power status reporting, and separation of load transients from actual load increases, are critical requirements for hot-swap applications.
The TPS2300/01 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. Each internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
PIN
TSSOP PACKAGES (PW, PWR)
TAHOT-SWAP CONTROLLER DESCRIPTION
COUNT
ENABLE ENABLE
Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPW
°
°
Dual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPW
–
40°C to 85°C
Dual-channel with independent OCP 16 TPS2320IPW TPS2321IPW Single-channel with OCP and adjustable PG 14 TPS2330IPW TPS2331IPW
†
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2301IPWR).
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
GATE1 GATE2
DGND
TIMER
VREG VSENSE2 VSENSE1
AGND ISENSE2 ISENSE1
DISCH1 DISCH2 ENABLE PWRGD1 FAULT ISET1 ISET2 PWRGD2 IN2 IN1
PW PACKAGE
(TOP VIEW)
typical application
NOTE: Terminal 18 is active high on TPS2301.
VREG
IN1
ISET1
ISENSE1
GATE1
DISCH1
VSENSE1
PWRGD1
FAULT
TIMER
VSENSE2
DISCH2
GATE2
ISENSE2
ISET2IN2
ENABLE
DGND
AGND
V2
V1
3 V – 5.5 V
3 V – 13 V
PWRGD2
TPS2300
+
V
O1
V
O2
+
TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
PREREG
UVLO and Power-Up
IN1 ISET1 ISENSE1 GATE1
Clamp
Charge
Pump
75 µA
Pulldown FET Circuit Breaker
dv/dt Rate Protection
20-µs Deglitch
DISCH1
Logic
VSENSE1
PWRGD1
FAULT
TIMER
Second Channel
PWRGD2
GATE2ISENSE2ISET2IN2
DISCH2 VSENSE2
Circuit Breaker
VREG
50-µs Deglitch
AGND
DGND
ENABLE
50 µA
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
AGND 8 I Analog ground, connects to DGND as close as possible DGND 3 I Digital ground DISCH1 20 O Discharge transistor 1 DISCH2 19 O Discharge transistor 2 ENABLE/ ENABLE 18 I Active low (TPS2300) or active high enable (TPS2301) FAULT 16 O Overcurrent fault, open-drain output GATE1 1 O Connects to gate of channel 1 high-side MOSFET GATE2 2 O Connects to gate of channel 2 high-side MOSFET IN1 11 I Input voltage for channel 1 IN2 12 I Input voltage for channel 2 ISENSE1 10 I Current-sense input channel 1 ISENSE2 9 I Current-sense input channel 2 ISET1 15 I Adjusts circuit-breaker threshold with resistor connected to IN1 ISET2 14 I Adjusts circuit-breaker threshold with resistor connected to IN2 PWRGD1 17 O Open-drain output, asserted low when VSENSE1 voltage is less than reference. PWRGD2 13 O Open-drain output, asserted low when VSENSE2 voltage is less than reference. TIMER 4 O Adjusts circuit-breaker deglitch time VREG 5 O Connects to bypass capacitor, for stable operation VSENSE1 7 I Power-good sense input channel 1 VSENSE2 6 I Power-good sense input channel 2
TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GA TE1 and GA TE2, respectively. These pins discharge the loads when the MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-clamp circuitry.
ENABLE
or ENABLE – ENABLE for TPS2300 is active low. ENABLE for TPS2301 is active high. When the
controller is enabled, both GA TE1 and GATE2 voltages will power up to turn on the external MOSFET s. When the ENABLE pin is pulled high for TPS2300 or the ENABLE pin is pulled low for TPS2301 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is sustained long enough to charge TIMER to 0.5 V , the overcurrent channel latches off and pulls this pin low . The other channel will run normally if not in overcurrent.
GA TE1, GA TE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V–12 V across the external MOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET transistors connected to GA TE1 and GA TE2, respectively . The TPS2300/TPS2301 draws its operating current from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1 channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement overcurrent sensing for GA TE1 and GA TE2. ISET1 and ISET2 set the magnitude of the current that generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2.
PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1 and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V), PWRGDx will be active low to indicate an undervoltage condition on the power-rail voltage.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V , the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current from IN1. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However , the voltage on VREG must be less than 5.5 V.
TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
VSENSE1, VSENSE2 – VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external
circuitry . If VSENSE1 senses a voltage below approximately 1.23 V , PWRGD1 is pulled low. Similarly , a voltage less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Input voltage range: V
I(IN1)
, V
I(ISENSE1)
, V
I(VSENSE1)
, V
I(VSENSE2)
, V
I(ISET1)
,
V
I(ENABLE)
–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range: V
O(GATE1)
–0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
O(GATE2)
–0.3 V to 22V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
O(DISCH1)
, V
O(PWRGD1)
, V
O(PWRGD2)
, V
O(FAULT)
, V
O(VREG)
,
V
O(DISCH2)
, V
O(TIMER)
–0.3 V to 15V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sink current range: I
GATE1
, I
GATE2
, I
DISCH1
, I
DISCH2
0 mA to 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
PWRGD1
, I
PWRGD2
, I
TIMER
, I
FAUL T
0 mA to 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW-20 1015 mW 13.55 mW/°C 406 mW 203 mW
recommended operating conditions
MIN NOM MAX UNIT
p
V
I(IN1)
, V
I(ISENSE1)
, V
I(VSENSE1)
, V
I(VSENSE2)
, V
I(ISET1)
3 13
Input voltage, V
I
V
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
3 5.5
V
VREG voltage, V
O(VREG)
, when VREG is directly connected to IN1 2.95 5.5 V
Operating virtual junction temperature, T
J
–40 100 °C
TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C), 3 V ≤ V
I(IN1)
≤13 V, 3 V ≤ V
I(IN2)
≤ 5.5 V (unless otherwise noted)
general
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
I(IN1)
Input current, IN1 V
I(ENABLE)
= 5 V (TPS2301), 0.5 1 mA
I
I(IN2)
Input current, IN2 V
I(ENABLE)
= 0 V (TPS2300) 75 200 µA
Standby current (sum of currents into IN1, IN2,
V
I(ENABLE)
= 0 V (TPS2301)
I
I(stby)
y(
ISENSE1, ISENSE2, ISET1, and ISET2)
V
I(ENABLE)
= 5 V (TPS2300)
5
µA
GATE1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
G(GATE1_3V)
V
I(IN1)
= 3 V 9 11.5
V
G(GATE1_4.5V)
Gate voltage
I
I(GATE1)
=
500 nA
,
DISCH1 open
V
I(IN1)
= 4.5 V 10.5 14.5
V
V
G(GATE1_10.8V)
DISCH1 oen
V
I(IN1)
= 10.8 V 16.8 21
V
C(GATE1)
Clamping voltage, GATE1 to DISCH1
9 10 12 V
I
S(GATE1)
Source current, GATE1
3 V ≤ V
I(IN1)
≤ 13.2 V, 3 V ≤ V
O(VREG)
≤ 5.5 V,
V
I(GATE1)
= V
I(IN1)
+ 6 V
10 14 20 µA
Sink current, GATE1
3 V ≤ V
I(IN1)
≤ 13.2 V, 3 V ≤ V
O(VREG)
≤ 5.5 V,
V
I(GATE1)
= V
I(IN1)
50 75 100 µA
V
I(IN1)
= 3 V 0.5
t
r(GATE1)
Rise time, GATE1 Cg to GND = 1 nF (see Note 2)
V
I(IN1)
= 4.5 V 0.6
ms
()
g
V
I(IN1)
= 10.8 V 1
V
I(IN1)
= 3 V 0.1
t
f(GATE1)
Fall time, GATE1 Cg to GND = 1 nF (see Note 2)
V
I(IN1)
= 4.5 V 0.12
ms
()
g
V
I(IN1)
= 10.8 V 0.2
GATE2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
G(GATE2_3V)
p
V
I(IN2)
= 3 V 9 11.7
V
G(GATE2_4.5V)
Gate voltage
I
I(GATE2)
=
500 nA, DISCH2 oen
V
I(IN2)
= 4.5 V 10.5 14.7
V
V
C(GATE2)
Clamping voltage, GATE2 to DISCH2
9 10 12 V
I
S(GATE2)
Source current, GATE2
3 V ≤ V
I(IN2)
≤ 5.5 V, 3 V ≤ V
O(VREG)
≤ 5.5 V,
V
I(GATE2)
= V
I(IN2)
+ 6 V
10 14 20 µA
Sink current, GATE2
3 V ≤ V
I(IN2)
≤ 5.5 V, 3 V ≤ V
O(VREG)
≤ 5.5 V,
V
I(GATE2)
= V
I(IN2)
50 75 100 µA
C
to GND = 1 nF
V
I(IN2)
= 3 V 0.5
t
r(GATE2)
Rise time, GATE2
g
(see Note 2)
V
I(IN2)
= 4.5 V
0.6
ms
Cg to GND = 1 nF
V
I(IN2)
= 3 V
V
O(VREG)
= 3
V
0.1
t
f(GATE2)
Fall time, GATE2
g
(see Note 2)
V
I(IN2)
= 4.5 V 0.12
ms
NOTE 2: Specified, but not production tested.
TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C), 3 V ≤ V
I(IN1)
≤13 V, 3 V ≤ V
I(IN2)
≤ 5.5 V ( unless otherwise noted) (continued)
TIMER
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OT(TIMER)
Threshold voltage, TIMER 0.4 0.5 0.6 V Charge current, TIMER V
I(TIMER)
= 0 V 35 50 65 µA
Discharge current, TIMER V
I(TIMER)
= 1 V 1 2.5 mA
circuit breaker
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT(CB)
Undervoltage voltage, circuit breaker R
ISETx
= 1 kΩ 40 50 60 mV
I
IB(ISENSEx)
Input bias current, I
SENSEx
0.1 5 µA
V
O(GATEx)
= 4 V 400 800
Discharge current, GATE
x
V
O(GATEx)
= 1 V
25 150
mA
t
pd(CB)
Propagation (delay) time, comparator inputs to gate output
Cg = 50 pF, (50% to 10%)
10 mV overdrive, C
O(timer)
= 50 pF
1.3 µs
ENABLE, active low (TPS2300)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH(ENABLE)
High-level input voltage, ENABLE 2 V
V
IL(ENABLE
)
Low-level input voltage, ENABLE 0.8 V
R
I(ENABLE
)
Input pullup resistance, ENABLE
See Note 3 100 200 300 kΩ
t
d_off(ENABLE)
Turnoff delay time, ENABLE
V
I(ENABLE)
increasing above stop threshold; 100
ns rise time, 20 mV overdrive (see Note 2)
60 µs
t
d_on(ENABLE)
Turnon delay time, ENABLE
V
I(ENABLE
)
decreasing below start threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
125 µs
NOTES: 2. Specified, but not production tested.
3. Test IO of ENABLE
at V
I(ENABLE
)
= 1 V and 0 V, then R
I(ENABLE)
=
1V
I
O_
0V
*
I
O_
1V
ENABLE, active high (TPS2301)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH(ENABLE)
High-level input voltage, ENABLE 2 V
V
IL(ENABLE)
Low-level input voltage, ENABLE 0.7 V
R
I(ENABLE)
Input pulldown resistance, ENABLE
100 150 300 kΩ
t
d_on(ENABLE)
Turnon delay time, ENABLE
V
I(ENABLE)
increasing above start threshold;
100 ns rise time, 20 mV overdrive (see Note 2)
85 µs
t
d_off(ENABLE)
Turnoff delay time, ENABLE
V
I(ENABLE)
decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100 µs
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG PREREG output voltage 4.5 ≤ V
I(IN1)
≤ 13 V 3.5 4.1 5.5 V
Vdrop_PREREG PREREG dropout voltage V
I(IN1)
= 3 V 0.1 V
TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40°C < TA < 85°C), 3 V ≤ V
I(IN1)
≤13 V, 3 V ≤ V
I(IN2)
≤ 5.5 V (unless otherwise noted) (continued)
VREG UVLO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OT(UVLOstart)
Output threshold voltage, start 2.75 2.85 2.95 V
V
OT(UVLOstop)
Output threshold voltage, stop 2.65 2.78 V
V
hys(UVLO)
Hysteresis 50 75 mV UVLO sink current, GATEx V
I(GATEx)
= 2 V 10 mA
PWRGD1 and PWRGD2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT(ISENSEx)
Trip threshold, VSENSEx V
I(VSENSEx)
decreasing 1.2 1.225 1.25 V
V
hys
Hysteresis voltage, power-good comparator
20 30 40 mV
V
O(sat)(PWRGDx)
Output saturation voltage PWRGDx IO = 2 mA 0.2 0.4 V
V
O(VREGmin)
Minimum V
O(VREG)
for valid power-good IO = 100 µA, V
O(PWRGDx)
= 1 V 1 V
I
IB
Input bias current, power-good comparator V
I(VSENSEx)
= 5.5 V 1 µA
I
lkg(PWRGDx)
Leakage current, PWRGDx V
O(PWRGDx)
= 13 V 1 µA
t
dr
Delay time, rising edge, PWRGDx
V
I(VSENSEx)
increasing,
Overdrive = 20 mV , tr = 100 ns, See Note 2
25 µs
t
df
Delay time, falling edge, PWRGDx
V
I(VSENSEx)
decreasing, Overdrive = 20 mV , tr = 100 ns, See Note 2
2 µs
NOTE 2: Specified, but not production tested.
FAULT output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O(sat)(FAULT)
Output saturation voltage, FAULT IO = 2 mA 0.4 V
I
lkg(FAULT)
Leakage current, FAULT V
O(FAULT)
= 13 V 1 µA
DISCH1 and DISCH2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
DISCH
Discharge current, DISCHx V
I(DISCHx)
= 1.5 V, V
I(VIN1)
= 5 V 5 10 mA
V
IH(DISCH)
Discharge on high-level input voltage 2 V
V
IL(DISCH)
Discharge on low-level input voltage 1 V
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