TEXAS INSTRUMENTS TPS2220A, TPS2223A, TPS2224A, TPS2226A Technical data

www.ti.com

24
23
22
21
20
19
18
17
16
15
14
13

1
2
3
4
5
6
7
8
9
10
11
12

TPS2223A, TPS2224A

DB OR PWP PACKAGE

(TOP VIEW)

5V
5V

DATA

CLOCK

LATCH

NC

12V

†

AVPP
AVCC
AVCC

GND

RESET

5V
NC
NC
SHDN
12V

†

BVPP
BVCC
BVCC
NC
OC

3.3V

3.3V

NC − No internal connection

†

Pin 7 and 20 are NC for TPS2223A.

查询TPS2220ADB供应商

CARDBUS POWER-INTERFACE SWITCHES

FOR SERIAL PCMCIA CONTROLLERS

FEATURES APPLICATIONS

• Single-Slot Switch: TPS2220A

Dual-Slot Switches: TPS2223A, TPS2224A,
TPS2226A

• Fast Current Limit Response Time

• Fully Integrated VCC and VPP Switching for

3.3 V, 5 V, and 12 V (no 12 V on TPS2223A)

• Meets Current PC Card™ Standards

• V

• 12-V and 5-V Supplies Can Be Disabled

• TTL-Logic Compatible Inputs

• Short-Circuit and Thermal Protection

• 24-Pin HTSSOP, 24- or 30-Pin SSOP

• 140-µA (Typical) Quiescent Current from

• Break-Before-Make Switching

• Power-On Reset

• 40 ° C to 85 ° C Operating Ambient Temperature

Output Selection Independent of V

pp

3.3-V Input

Range

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

• Notebook and Desktop Computers

• Bar Code Scanners

• Digital Cameras

• Set-Top Boxes

• PDAs

CC

DESCRIPTION

The TPS2223A, TPS2224A, and TPS2226A CardBus™ power-interface switches provide an integrated
power-management solution for two PC Card sockets. The TPS2220A is a single-slot option for this family of
devices. These devices allow the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. The
current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user
isolate a system fault. The switch r
requirements stated in the PC Card specification, and optimized for cost. A faster maximum current limit
response time is the only difference between the TPS2223A, TPS2224A, and TPS2226A and the TPS2223,
TPS2224, and TPS2226.

Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports independent
VPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown mode is now
supported independently on SHDN as well as in the serial interface. Optimized for lower power implementation,
the TPS2223A does not support 12-V switching to VPP. See the available options table for pin-compatible device
information.

PC Card, CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

and current-limit values have been set for the peak and average current

DS(on)

Copyright © 2002–2004, Texas Instruments Incorporated

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

TPS2223ADB, TPS2224ADB TPS2226ADB

-40 ° C to 85 ° C TPS2220ADB TPS2220APWP

(1) The DB and PWP packages are also available taped and reeled. Add R suffix to device type (e.g., TPS2223APWPR) for taped and

reeled.

T

A

–40 ° C to 85 ° C Green

(1) The marketing status values are defined as follows:

• ACTIVE: This device recommended for new designs.

• LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

• NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend

using this part in a new design.

• PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

• OBSOLETE: TI has discontinued production of the device.

(2) Eco-Status Information – Additional details including specific material content can be accessed at www.ti.com/leadfree

• N/A: Not yet available Lead (Pb)-free, for estimated conversion dates go to www.ti.com/leadfree.

• Pb-Free: TI defines "Lead (Pb)-Free" or "Pb-Free" to mean RoHS compatible, including a lead concentration that does not exceed

0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.

• Green: TI devices "Green" to mean Lead (Pb)-Free and in addition, uses package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.

Pin TPS2214, Pin

compatibles TPS2214A compatibles

SSOP(DB) STATUS

TPS2220ADBG4 Active TPS2220APWPRG4 Active
TPS2223ADBG4 Active TPS2223APWPRG4 Preview
TPS2224ADBG4 Active TPS2224APWPRG4 Preview
TPS2226ADBG4 Active TPS2226APWPRG4 Preview

PLASTIC SMALL OUTLINE PowerPAD™

DB-24 DB-30

TPS2216,
TPS2216A,
TPS2206

PLASTIC SMALL OUTLINE

TPS2223APWP,

TPS2224APWP

LEAD (PB-FREE) ORDERING INFORMATION

(1)

HTSSOP(PWP) STATUS

(1)

(PWP-24)

(1)

ECO-STATUS

(2)

2

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

I(3.3V)

V

V

I

T
T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) Not applicable for TPS2223A

Input voltage range for card power V

I

I(5V)

(2)

V

I(12V)

Logic input/output voltage –0.3 to 6 V

V

Output voltage

O

O(xVCC)

V

O(xVPP)

Continuous total power dissipation See Dissipation Rating Table

I

Output current

O

Operating virtual junction temperature range –40 to 100 ° C

J

Storage temperature range –55 to 150 ° C

stg

O(xVCC)

I

O(xVPP)

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) 260 ° C
OC sink current 10 mA

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

TPA222xA UNIT

–0.3 to 5.5 V
–0.3 to 5.5 V

–0.3 to 14 V

–0.3 to 6 V

–0.3 to 14 V

Internally Limited
Internally Limited

DISSIPATION RATING TABLE

PACKAGE

DB

(1)

24 890 mW 8.9 mW/ ° C 489 mW 356 mW
30 1095 mW 10.95 mW/ ° C 602 mW 438 mW

PWP 24 3322 mW 33.22 mW/ ° C 1827 mW 1329 mW

(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).

TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C

POWER RATING ABOVE TA= 25 ° C POWER RATING POWER RATING

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

(1)

Input voltage, V
operations. 5V and 12V are only required for V
their respective functions.

I

O

f

(clock)

t

w

t

h

t

su

t

d(latch)

t

d(clock)

T

J

Output current

Clock frequency 2.5 MHz

Pulse duration ns

Data-to-clock hold time (see Figure 2 ) 100 ns
Data-to-clock setup time (see Figure 2 ) 100 ns
Latch delay time (see Figure 2 ) 100 ns
Clock delay time (see Figure 2 ) 250 ns
Operating virtual junction temperature (maximum to be calculated at worst case PDat 85 ° C

ambient)

(1) It is understood that for V
(2) Not applicable for TPS2223A

V

I(3.3V)

is required for all circuit

I(3.3V)
I(5V)

(2)

V

I(12V)

I

at TJ= 100 ° C 1 A

O(xVCC)

I

at TJ= 100 ° C 100 mA

O(xVPP)

Data 200
Latch 250
Clock 100
Reset 100

< 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC.

I(3.3V)

3 3.6
3 5.5 V
7 13.5

–40 100 ° C

3

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS

TJ= 25 ° C, V
noted)

POWER SWITCH

r

DS(on)

I

OS

T

J

I

I

I

lkg

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.
(2) TPS2223A, TPS2224A, TPS2226A: two switches on. TPS2220A: one switch on.
(3) Specified by design; not tested in production.
(4) From application of short to 110% of final current limit.

= 5 V, V

I(5V)

PARAMETER TEST CONDITIONS

Static drain-source
on-state resistance

Output discharge
resistance

Short-circuit output current

Thermal shutdown
temperature

(2)

Current-limit response time

Input current, quiescent µA

Leakage current,
output off state

= 3.3 V, V

I(3.3V)

3.3V to xVCC

5V to xVCC

3.3V or 5V to xVPP

12V to xVPP

Discharge at xVCC I
Discharge at xVPP I

= 12 V (not applicable for TPS2223A), all outputs unloaded (unless otherwise

I(12V)

(1)

(2)

IO= 750 mA each 85 110
IO= 750 mA each, TJ= 100 ° C 110 140

(2)

IO= 500 mA each 95 130
IO= 500 mA each, TJ= 100 ° C 120 160
IO= 50 mA each 0.8 1

(2)

IO= 50 mA each, TJ= 100 ° C 1 1.3

(2)

IO= 50 mA each 2 2.5
IO= 50 mA each, TJ= 100 ° C 2.5 3.4

= 1 mA 0.5 0.7 1

O(disc)

= 1 mA 0.2 0.4 0.5

O(disc)

I

Limit (steady-state value), output pow­ered into a short circuit

Limit (steady-state value), output pow- I
ered into a short circuit,
TJ= 100 ° C

OS(xVCC)

I

OS(xVPP)
OS(xVCC)

I

OS(xVPP)

MIN TYP MAX UNIT

1 1.4 2 A

120 200 300 mA

1 1.4 2 A

120 200 300 mA

Thermal trip point Rising temperature 135
Hysteresis 10

(3) (4)

5V to xVCC = 5 V, with 100-m Ω short to GND 10
5V to xVPP = 5 V, with 100-m Ω short to GND 3

I
Normal VO(xVCC) = VO(xVPP) = 3.3 V and
operation also for RESET = 0 V

Shutdown mode I

Shutdown mode µA

I(3.3V)

I

I(5V)

I

I(12V)

I

I(3.3V)

VO(xVCC) = VO(xVPP) = Hi-z 0.1 2

I(5V)

I

I(12V)

V

= 5 V, V

O(xVCC)

V

= 12 V, V

O(xVPP)

= V

I(5V)

I(5V)

= 0 V

I(12V)

= V

= 0 V

I(12V)

TJ= 100 ° C 50

TJ= 100 ° C 50

m Ω

Ω

k Ω

° C

µs

140 200

8 12

100 180

0.3 2

0.3 2
10

10

4

www.ti.com

PARAMETER TEST CONDITIONS

LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)

(5)

I

I(/RESET)

(5)

I

I

I

V

IH

V

IL

V

O(sat)

I

lkg

Input current, logic SHDN = 0 V -50 -3 µA

High-level input voltage, logic 2 V
Low-level input voltage, logic 0.8 V
Output saturation voltage at OC IO= 2 mA 0.14 0.4 V
Leakage current at OC V

I(/SHDN)

(5)

I

I(LATCH)

I

I(CLOCK, DATA)

RESET = 5.5 V -1 1
RESET = 0 V -30 -20 -10
SHDN = 5.5 V -1 1

LATCH = 5.5 V 50
LATCH = 0 V -1 1
0 V to 5.5 V -1 1

O(/OC)

UVLO AND POR (POWER-ON RESET)

V

I(3.3V)

V

hys(3.3V)

V

I(5V)

V

hys(5V)

t

df

V

I(POR)

Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V
UVLO hysteresis voltage at VA

(6)

Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 V
UVLO hysteresis voltage at 5V
Delay time for falling response, UVLO

Input voltage, power-on reset

(6)

(6)

(6)

Delay from voltage hit (step from 3 V to 2.3 V) to
Hi-Z control (90% VGto GND)

3.3-V voltage below which POR is asserted causing a
RESET internally with all line switches open and all 1.7 V
discharge switches closed.

(5) LATCH has low-current pulldown. RESET and SHDN have low-current pullup.
(6) Specified by design; not tested in production.

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

(1)

= 5.5 V 0 1 µA

MIN TYP MAX UNIT

100 mV

100 mV

4 µs

5

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

SWITCHING CHARACTERISTICS

V

= 5 V, TA= 25 ° C, V

CC

otherwise noted)

PARAMETER

t

Output rise times

r

t

Output fall times

f

Propagation delay

t

pd

times

(1)

(3)

= 3.3 V, V

I(3.3V)

C

L(xVCC)

I

(3)

(3)

O(xVCC)

C

L(xVCC)

I

O(xVCC)

C

L(xVCC)

I

O(xVCC)

C

L(xVCC)

I

O(xVCC)

C

L(xVCC)

I

O(xVCC)

C

L(xVCC)

I

O(xVCC)

= 5 V, V

I(5V)

= 12 V (not applicable for TPS2223A) all outputs unloaded (unless

I(12)

LOAD CONDITION TEST CONDITIONS

= 0.1 µF, C

= 0 A, I

= 150 µF, C

= 0.75 A, I

= 0.1 µF, C

= 0 A, I

= 150 µF, C

= 0.75 A, I

= 0.1 µF, C

= 0 A, I

= 150 µF, C

= 0.75 A, I

O(xVPP)

O(xVPP)

O(xVPP)

= 0.1 µF,

L(xVPP)

= 0 A

= 10 µF,

L(xVPP)

= 50 mA

O(xVPP)

= 0.1 µF,

L(xVPP)

= 0 A

= 10 µF,

L(xVPP)

= 50 mA

O(xVPP)

= 0.1 µF,

L(xVPP)

= 0 A

= 10 µF,

L(xVPP)

= 50 mA

O(xVPP)

(2)

V
V
V
V
V

Discharge switches ON
V

Discharge switches ON
V
V

Latch ↑ to xVPP (12V)

= 5 V 0.9

O(xVCC)

= 12 V 0.26

O(xVPP)

= 5 V 1.1

O(xVCC)

= 12 V 0.6

O(xVPP)

= 5 V,

O(xVCC)

= 12 V,

O(xVPP)

= 5 V 2.35

O(xVCC)

= 12 V 3.9

O(xVPP)

(4)

Latch ↑ to xVPP (5V)

Latch ↑ to xVPP (3.3V) ms

Latch ↑ to xVCC (5V)

Latch ↑ to xVCC (3.3V)

Latch ↑ to xVPP (12V)

(4)

Latch ↑ to xVPP (5V)

Latch ↑ to xVPP (3.3V) ms

Latch ↑ to xVCC (5V)

Latch ↑ to xVCC (3.3V)

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

t

pdon

t

pdoff

MIN TYP MAX UNIT

0.5

0.2

2

0.62

0.77

0.51

0.75

0.52

0.3

2.5

0.3

2.8

2.2

0.8

0.8

0.6

0.8

0.6

0.6

2.5

0.5

2.6

ms

ms

(1) Refer to Parameter Measurement Information in Figure 1 .
(2) No card inserted, assumes a 0.1-µF output capacitor (see Figure 1 ).
(3) Specified by design; not tested in production.
(4) Not applicable for TPS2223A

6

www.ti.com

CS

CS

S1

S4

CS

S7

CS

S11

Control Logic
SHDN
RESET
DATA
CLOCK
LATCH

OC

GND

UVLO

POR

Current Limit

Thermal Limit

S2

S5

S3

S6

S8

S9

S10

S12

S13

S14

Discharge
Element

13

14

3.3 V

3.3 V

Power
Inputs

3.3V
1

2

24

5 V
5 V
5 V

Power
Inputs

5V

7

12 V

Power
Inputs

12V

20

12 V

21
12

3
4
5

15

9

10

AVCC

AVCC

17

18

BVCC

BVCC

8

AVPP

19

BVPP

11

Power Outputs

NOTES:A. Diagram shown for 24-pin DB package.

B. Current sense
C. The two 12-V pins must be externally connected.
D. No connections for TPS2223A.

See Note B

See Note B

See Note B

See Note B

See Note C

See Note C

See Note C

See Note D

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

FUNCTIONAL BLOCK DIAGRAM OF TPS2223A, TPS2224A and TPS2226A (see Note A)

7

www.ti.com

See Note A

See Note A

CS

S1

CS

S7

Control Logic
SHDN
RESET
DATA
CLOCK
LATCH

OC

GND

UVLO

POR

Current Limit

Thermal Limit

S2

S3

S4

S5

S6

3.3 V

5 V

5 V

12 V

AVCC

AVCC

AVPP

See Note B

NOTES:A. Current sense

B. The two 12-V pins must be externally connected.

12 V
See Note B

24
23
22
21
20
19
18
17
16
15
14
13

1
2
3
4
5
6
7
8
9
10
11
12

TPS2220A

DB OR PWP PACKAGE

(TOP VIEW)

5V
5V

DATA

CLOCK

LATCH

NC

12V

AVPP
AVCC
AVCC

GND

RESET

NC
NC
NC
SHDN
12V
NC
NC
NC
NC
OC
NC

3.3V

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

TPS2226A

DB PACKAGE

(TOP VIEW)

5V
5V

DATA

CLOCK

LATCH

NC

12V

AVPP
AVCC
AVCC
AVCC

GND

NC

RESET

3.3V

5V
NC
NC
NC
NC
SHDN
12V
BVPP
BVCC
BVCC
BVCC
NC
OC

3.3V

3.3V

NC - No internal connection

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

FUNCTIONAL BLOCK DIAGRAM OF TPS2220A

8

PIN ASSIGNMENTS

www.ti.com

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

Terminal Functions

TERMINAL

NAME

3.3V 13 13, 14 13, 14 15, 16, 17 I 3.3-V input for card power and chip power
5V 1, 2 1, 2, 24 1, 2, 24 1, 2, 30 I 5-V input for card power

12V 7, 20 NA 7, 20 7, 24 I

AVCC 9, 10 9, 10 9, 10 9, 10, 11 O

AVPP 8 8 8 8 O

BVCC -- 17, 18 17, 18 20, 21, 22 O

BVPP -- 19 19 23 O
GND 11 11 11 12 Ground
OC 15 15 15 18 O

SHDN 21 21 21 25 I

RESET 12 12 12 14 I
CLOCK 4 4 4 4 I Logic-level clock for serial data word

DATA 3 3 3 3 I Logic-level serial data word
LATCH 5 5 5 5 I Logic-level latch for serial data word, internal pulldown

NC 17, 18, 19, 26, 27, 28, No internal connection

TPS2220A TPS2223A TPS2224A TPS2226A

6, 14, 16, 6, 13, 19,

22, 23, 24 29

6, 7, 16, 6, 16, 22,

20, 22, 23 23

NO. I/O DESCRIPTION

12-V input for card power (xVPP). The two 12-V pins must be
externally connected.

Switched output that delivers 3.3 V, 5 V, ground or high impedance to
card

Switched output that delivers 3.3 V, 5 V, 12 V, ground or high
impedance to card (12 V not applicable to TPS2223A)

Switched output that delivers 3.3 V, 5 V, ground or high impedance to
card

Switched output that delivers 3.3 V, 5 V, 12 V, ground or high
impedance to card (12 V not applicable for TPS2223A)

Open-drain overcurrent reporting output that goes low when an
overcurrent condition exists. An external pullup is required.

Hi-Z (open) all switches. Identical function to serial D8. Asynchronous
active-low command, internal pullup

Logic-level RESET input active low. Asynchronous active-low com­mand, internal pullup

TPS2220A, TPS2223A
TPS2224A, TPS2226A

9

www.ti.com

50%

LATCH

V

DD

GND

10%

90%

t

pd(on)

GND

V

O(xVPP)

Propagation Delay (xVPP)

50%

LATCH

V

DD

GND

10%

90%

t

pd(on)

GND

V

O(xVCC)

Propagation Delay (xVCC)

10%

90%

t

r

GND

V

O(xVPP)

Rise/Fall Time (xVPP)

t

f

10%

90%

t

r

GND

V

O(xVCC)

Rise/Fall Time (xVCC)

t

f

50%

V

DD

GND

10%

90%

t

on

GND

V

O(xVCC)

Turnon/off Time (xVCC)

xVPP

VOLTAGE WAVEFORMS

LOAD CIRCUIT (xVPP)

I

O(xVPP)

xVCC

50%

LATCH

V

DD

GND

10%

90%

t

on

GND

V

O(xVPP)

Turnon/off Time (xVPP)

I

O(xVCC)

t

pd(off)

t

pd(off)

t

off

t

off

LOAD CIRCUIT (xVCC)

V

I(12V/5V/3.3V)

V

I(5V/3.3V)

V

I(12V/5V/3.3V)

V

I(5V/3.3V)

V

I(12V/5V/3.3V)

V

I(5V/3.3V)

LATCH

D10

D9

D8 D7

D6

D5

D4 D3

D2

DATA

LATCH

CLOCK

D1

D0

Data Setup Time Data Hold Time Latch Delay Time

Clock Delay Time

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Circuits and Voltage Waveforms

NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next

10

positive edge of the clock. For definition of D0 to D10, see the control logic table.

Figure 2. Serial-Interface Timing for TPS2226A

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

PARAMETER MEASUREMENT INFORMATION (continued)
Table of Graphs

Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3
Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4
OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5
OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6
xVCC Turnon propagation delay time (C
xVCC Turnoff propagation delay time (C
xVPP Turnon propagation delay time (C
xVPP Turnoff propagation delay time (C
xVCC Turnon propagation delay time (T
xVCC Turnoff propagation delay time (T
xVPP Turnon propagation delay time (T
xVPP Turnoff propagation delay time (T
xVCC Rise time (C
xVCC Fall time (C
xVPP Rise time (C
xVPP Fall time (C
xVCC Rise time (T
xVCC Fall time (T
xVPP Rise time (T
xVPP Fall time (T

= 150 µF) vs Junction temperature 15

L

= 150 µF) vs Junction temperature 16

L

= 10 µF) vs Junction temperature 17

L

= 10 µF) vs Junction temperature 18

L

= 25 ° C) vs Load capacitance 19

J

= 25 ° C) vs Load capacitance 20

J

= 25 ° C) vs Load capacitance 21

J

= 25 ° C) vs Load capacitance 22

J

= 150 µF) vs Junction temperature 7

L

= 150 µF) vs Junction temperature 8

L

= 10 µF) vs Junction temperature 9

L

= 10 µF) vs Junction temperature 10

L

= 25 ° C) vs Load capacitance 11

J

= 25 ° C) vs Load capacitance 12

J

= 25 ° C) vs Load capacitance 13

J

= 25 ° C) vs Load capacitance 14

J

FIGURE

11

www.ti.com

1 2 3 4 5

t − Time − ms

0

V

O(/OC)

2 V/div

I

O(xVPP)

2 A/div

100 200 300 400 500

t − Time − µs

0

V

O(/OC)

5 V/div

I

O(VCC)

5 A/div

V

IN(5V)

2 V/div

10 20 30 40 50

t − Time − ms

0

V

O(/OC)

5 V/div

I

O(xVCC)

1 A/div

2 4 6 8 10

t − Time − ms

0

V

O(/OC)

5 V/div

I

O(xVPP)

100 mA/div

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

SHORT-CIRCIUT RESPONSE, SHORT-CIRCIUT RESPONSE,

SHORT APPLIED TO POWERED-ON 5-V SHORT APPLIED TO POWERED-ON 12-V

xVCC-SWITCH OUTPUT xVPP-SWITCH OUTPUT

Figure 3. Figure 4.

OC RESPONSE WITH RAMPED OC RESPONSE WITH RAMPED

OVERCURRENT-LIMIT LOAD ON 5-V OVERCURRENT-LIMIT LOAD ON 12-V

xVCC-SWITCH OUTPUT xVPP-SWITCH OUTPUT

Figure 5. Figure 6.

12

www.ti.com

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

−50 −20 10 40 70 100

xVCC = 5 V
IO = 0.75 A
C

L

= 150 µF

− Turnon Propagation Delay T ime, xVCC − ms

t

pd(on)

TJ − Junction Temperature − °C

2.25

2.3

2.35

2.4

2.45

2.5

2.55

2.6

−50 −20 10 40 70 100

xVCC = 5 V
IO = 0.75 A
CL = 150 µF

t

pd(off)

TJ − Junction Temperature − °C

− Turnoff Propagation Delay T ime, xVCC − ms

0

0.5

1

1.5

2

2.5

3

−50 −20 10 40 70 100

t

pd(on)

TJ − Junction Temperature − °C

xVPP = 12 V
IO = 0.05 A
CL = 10 µF

− Turnon Propagation Delay T ime, xVPP − ms

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

−50 −20 10 40 70 100

− Turnoff Propagation Delay T ime, xVCC − ms

t

pd(off)

TJ − Junction Temperature − °C

xVCC = 12 V
IO = 0.05 A
CL = 10 µF

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

TURNON PROPAGATION DELAY TIME, xVCC TURNOFF PROPAGATION DELAY TIME, xVCC

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

TURNON PROPAGATION DELAY TIME, xVPP TURNON PROPAGATION DELAY TIME, xVPP

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 7. Figure 8.

vs vs

Figure 9. Figure 10.

13

www.ti.com

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1 1 10 100 1000

− Turnon Propagation Delay T ime, xVCC − ms

t

pd(on)

xVCC = 5 V
IO = 0.75 A
TJ = 25°C

CL − Load Capacitance − µF

2.25

2.3

2.35

2.4

2.45

2.5

2.55

0.1 1 10 100 1000

xVCC = 5 V
IO = 0.75 A
TJ = 25°C

CL − Load Capacitance − µF

t

pd(off)

− Turnoff Propagation Delay T ime, xVCC − ms

1.95

2

2.05

2.1

2.15

2.2

2.25

0.1 1 10

− Turnon Propagation Delay T ime, xVPP − ms

t

pd(on)

xVPP = 12 V
IO = 0.05 A
TJ = 25°C

CL − Load Capacitance − µF

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1 1 10

− Turnoff Propagation Delay T ime, xVPP − ms

t

pd(off)

xVPP = 12 V
IO = 0.05 A
TJ = 25°C

CL − Load Capacitance − µF

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

TURNON PROPAGATION DELAY TIME, xVCC TURNON PROPAGATION DELAY TIME, xVCC

LOAD CAPACITANCE LOAD CAPACITANCE

TURNON PROPAGATION DELAY TIME, xVPP TURNON PROPAGATION DELAY TIME, xVPP

LOAD CAPACITANCE LOAD CAPACITANCE

vs vs

Figure 11. Figure 12.

vs vs

14

Figure 13. Figure 14.

www.ti.com

2.34

2.35

2.36

2.37

2.38

2.39

2.4

2.41

−50 −20 10 40 70 100

− Fall Time xVCC − ms

t

f

TJ − Junction Temperature − °C

xVCC = 5 V
IO = 0.75 A
CL = 150 µF

1.04

1.06

1.08

1.1

1.12

1.14

1.16

1.18

1.2

1.22

−50 −20 10 40 70 100

− Rise Time, xVCC − ms

t

r

TJ − Junction Temperature − °C

xVCC = 5 V
IO = 0.75 A
CL = 150 µF

0.575

0.58

0.585

0.59

0.595

0.6

0.605

−50 −20 10 40 70 100

− Rise Time xVPP − ms

t

r

TJ − Junction Temperature − °C

xVPP = 12 V
IO = 0.05 A
CL = 10 µF

3.85

3.9

3.95

4

4.05

4.1

4.15

−50 −20 10 40 70 100

− Fall Time, xVPP − ms

t

f

TJ − Junction Temperature − °C

xVPP = 12 V
IO = 0.05 A
CL = 10 µF

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

RISE TIME, xVCC FALL TIME, xVCC

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

TPS2220A, TPS2223A
TPS2224A, TPS2226A

Figure 15. Figure 16.

RISE TIME, xVPP FALL TIME, xVPP

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 17. Figure 18.

15

www.ti.com

0

0.5

1

1.5

2

2.5

0.1 1 10 100 1000

− Fall Time xVCC − ms

t

f

xVCC = 5 V
IO = 0.75 A
TJ = 25°C

CL − Load Capacitance − µF

0

0.2

0.4

0.6

0.8

1

1.2

0.1 1 10 100 1000

− Rise Time, xVCC − ms

t

r

xVCC = 5 V
IO = 0.75 A
TJ = 25°C

CL − Load Capacitance − µF

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

0.1 1 10

− Fall Time, xVPP − ms

t

f

xVPP = 12 V
IO = 0.05 A
TJ = 25°C

CL − Load Capacitance − µF

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1 1 10

− Rise Time, xVPP − ms

t

r

xVPP = 12 V
IO = 0.05 A
TJ = 25°C

CL − Load Capacitance − µF

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

RISE TIME, xVCC FALL TIME, xVCC

LOAD CAPACITANCE LOAD CAPACITANCE

vs vs

16

Figure 19. Figure 20.

RISE TIME, xVPP FALL TIME, xVPP

vs vs

LOAD CAPACITANCE LOAD CAPACITANCE

Figure 21. Figure 22.

www.ti.com

0

20

40

60

80

100

120

140

160

180

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

I

I

− Input Current, xVCC = 3.3 V − Aµ

0

2

4

6

8

10

12

14

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

I

I

− Input Current, xVCC = 5 V − Aµ

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Input current, xVCC = 3.3 V 23

I

r

V

I

Input current, xVCC = 5 V vs Junction temperature 24

I

Input current, xVPP = 12 V 25
Static drain-source on-state resistance, 3.3 V to xVCC switch 26
Static drain-source on-state resistance, 5 V to xVCC switch vs Junction temperature 27

DS(on)

Static drain-source on-state resistance, 12 V to xVPP switch 28
xVCC switch voltage drop, 3.3-V input 29
xVCC switch voltage drop, 5-V input vs Load current 30

O

xVPP switch voltage drop, 12-V input 31
Short-circuit current limit, 3.3 V to xVCC 32
Short-circuit current limit, 5 V to xVCC vs Junction temperature 33

OS

Short-circuit current limit, 12 V to xVPP 34

INPUT CURRENT, xVCC = 3.3 V INPUT CURRENT, xVCC = 5 V

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 23. Figure 24.

17

www.ti.com

0

0.02

0.04

0.06

0.08

0.1

0.12

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

Ω

r

DS(on)

− Static Drain-Source On-State Resistance,

3.3 V to xVCC Switch −

0

20

40

60

80

100

120

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

I

I

− Input Current, xVPP = 12 V − Aµ

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

Ω

r

DS(on)

− Static Drain-Source On-State Resistance,

5 V to xVCC Switch −

0

0.5

1

1.5

2

2.5

3

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

Ω

r

DS(on)

− Static Drain-Source On-State Resistance,

12 V to xVPP Switch −

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

INPUT CURRENT, xVPP = 12 V 3.3 V TO xVCC SWITCH

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 25. Figure 26.

STATIC DRAIN-SOURCE ON-STATE RESISTANCE, STATIC DRAIN-SOURCE ON-STATE RESISTANCE,

5 V TO xVCC SWITCH 12 V TO xVPP SWITCH

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

STATIC DRAIN-SOURCE ON-STATE RESISTANCE,

18

Figure 27. Figure 28.

www.ti.com

0

0.02

0.04

0.06

0.08

0.1

0.12

0 0.2 0.4 0.6 0.8 1

TJ = −40°C

TJ = 85°C

TJ = 100°C

IL − Load Current − A

− xVCC Switch Voltage Drop, 3.3-V Input − VV
O

TJ = 25°C

TJ = 0°C

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 0.2 0.4 0.6 0.8 1

IL − Load Current − A

− xVCC Switch Voltage Drop, 5-V Input − VV
O

TJ = −40°C

TJ = 85°C

TJ = 100°C

TJ = 25°C

TJ = 0°C

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 0.01 0.02 0.03 0.04 0.05

IL − Load Current − A

− xVPP Switch V oltage Drop, 12-V Input − VV

O

TJ = −40°C

TJ = 85°C

TJ = 100°C

TJ = 25°C

TJ = 0°C

1.355

1.36

1.365

1.37

1.375

1.38

1.385

1.39

1.395

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

I

OS

− Short-Circuit Current Limit, 3.3 V to xVCC − A

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT xVCC SWITCH VOLTAGE DROP, 5-V INPUT

xVPP SWITCH VOLTAGE DROP, 12-V INPUT SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC

vs vs

LOAD CURRENT LOAD CURRENT

Figure 29. Figure 30.

vs vs

LOAD CURRENT JUNCTION TEMPERATURE

Figure 31. Figure 32.

19

www.ti.com

1.385

1.39

1.395

1.4

1.405

1.41

1.415

1.42

1.425

1.43

1.435

−50 −20 10 40 70 100
TJ − Junction Temperature − °C

I

OS

− Short-Circuit Current Limit, 5 V to xVCC − A

0.19

0.192

0.194

0.196

0.198

0.2

0.202

0.204

0.206

0.208

−50 −20 10 40 70 100

xVPP = 12 V

TJ − Junction Temperature − °C

I

OS

− Short-Circuit Current Limit, 12 V to xVPP − A

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 33. Figure 34.

20

www.ti.com

VDS V

O(reg)–VPS(reg)–VPCB

IOmax 

V

DS

r

DS(on)

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

APPLICATION INFORMATION

OVERVIEW

PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in
cards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and
hard-disk versions were soon available. As the number of PC Card applications grew, the engineering
community quickly recognized the need for a standard to ensure compatibility across platforms. Therefore, the
PCMCIA (Personal Computer Memory Card International Association) was established, comprising members
from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the
plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible.

PC CARD POWER SPECIFICATION

System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the 68 terminals of the PC Card connector. This power interface consists of two V
ground terminals. Multiple V
V

terminals were originally specified as separate signals, but are normally tied together in the host to form a

pp

single node to minimize voltage losses. Card primary power is supplied through the V
programming and erase voltage is supplied through the V

and ground terminals minimize connector-terminal and line resistance. The two

CC

terminals. Cardbus cards of today typically do not

pp

CC

use 12 V, which is now more of an optional requirement in the host.

CC

, two V

, and four

pp

terminals; flash-memory

DESIGNING FOR VOLTAGE REGULATION

The current PCMCIA specification for output voltage regulation, V
typical PC power-system design, the power supply has an output-voltage regulation, V
Also, a voltage drop from the power supply to the PC Card results from resistive losses, V
and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50
mV) of the output voltage. Therefore, the allowable voltage drop, V
and TPS2226A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and
connector resistive drops:

Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for
output voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting the
voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage
drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of
the device. Therefore, the maximum output current, IOmax, that can be delivered to the PC Card in regulation is
the allowable voltage drop across the IC, divided by the output-switch resistance.

The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card
specification within regulation over the operating temperature range. The xVPP outputs of the device have been
designed to deliver 100 mA continuously.

, of the 5-V output is 5% (250 mV). In a

O(reg)

, for the TPS2220A, TPS2223A, TPS2224A,

DS

PS(reg)

PCB

, of 2% (100 mV).

, in the PCB traces

OVERCURRENT AND OVERTEMPERATURE PROTECTION

PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that can lead to power-supply or PCB trace damage. Even extremely robust
systems can undergo rapid battery discharge into a damaged PC Card, resulting in the sudden and unacceptable
loss of system power. In comparison, the reliability of fused systems is poor because blown fuses require
troubleshooting and repair, usually by the manufacturer.

The TPS2220A, TPS2223A, TPS2224A, and TPS2226A take a two-pronged approach to overcurrent protection,
which is designed to activate if an output is shorted or when an overcurrent condition is present when switches
are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike

21

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage and
power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current
generates an error signal that limits the output current of only the affected output, preventing damage to the host.
Each xVCC output overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 100
mA to 250 mA, typically around 200 mA.

Second, when an overcurrent condition is detected, the TPS2220A, TPS2223A, TPS2224A, and TPS2226A
assert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics
and/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed its
maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the
device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal
limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings.

During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current
into a large load capacitance, faulty card, or connector.

12-V SUPPLY NOT REQUIRED

Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which
requires that power be present at all times. The TPS2220A, TPS2224A and TPS2226A offer considerable power
savings by using an internal charge pump to generate the required higher gate drive voltages from the 3.3-V
input. Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot,
thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply
current demanded from the 3.3-V input. When 12 V is supplied and requested at the VPP output, a voltage
selection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is
automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this
feature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up rate
of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which
quiescent current drops to a maximum of 1 µA.

VOLTAGE-TRANSITIONING REQUIREMENT

PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2220A, TPS2223A, TPS2224A, and TPS2226A meet all combinations of
power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V
systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA
specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before
applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V
charge and functions as a power reset. PC Card specification requires that V
Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance
because of possible high-impedance isolation by power-management schemes. The devices include discharge
transistors on all xVCC and xVPP outputs to meet the specification requirement.

be discharged within 100 ms. PC

CC

SHUTDOWN MODE

In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the
xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced
to 1 µA or less to conserve battery power.

POWER-SUPPLY CONSIDERATIONS

These switches have multiple pins for each 3.3-V (except for TPS2220A) and 5-V power input and for the
switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are
connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and
power loss. It is recommended that all input and output power pins be paralleled for optimum operation.

To increase the noise immunity of the TPS2220A, TPS2223A, TPS2224A, and TPS2226A, the power-supply
inputs should be bypassed with at least a 4.7-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to

22

www.ti.com

PD r

DS(on)

 I

2

T

J





PD R

JA



 T

A

where:

R

θJA

is the inverse of the derating factor given in the dissipation rating table.

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

0.1-µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-µF (or
larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should
be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents
can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable
performance. Similarly, no pin should be taken below -0.3 V.

RESET INPUT

To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be
reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground.
A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance,
permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closes
internal ground switches S1, S4, S7, and S11 with all other switches left open. The TPS2220A, TPS2223A,
TPS2224A, and TPS2226A remain in the low-impedance output state until the signal is deasserted and further
data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for
direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal
150-k Ω pullup resistor.

CALCULATING JUNCTION TEMPERATURE

The switch resistance, r
is dependent on both r
through Figure 28 , using an initial temperature estimate about 30 ° C above ambient. Then, calculate the power
dissipation for each switch, using the formula:

, is dependent on the junction temperature, TJ, of the die. The junction temperature

DS(on)

and the current through the switch. To calculate TJ, first find r

DS(on)

DS(on)

from Figure 26

Next, sum the power dissipation of all switches and calculate the junction temperature:

Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.

LOGIC INPUTS AND OUTPUTS

The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive
edge of the clock (see Figure 2 ). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the
latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs.

The serial interface of the device is compatible with serial-interface PCMCIA controllers.
An overcurrent output ( OC) is provided to indicate an overcurrent or overtemperature condition in any of the

xVCC and xVPP outputs as previously discussed.

23

www.ti.com

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

TPS2220A, TPS2223A, TPS2224A, and TPS226A CONTROL LOGIC

xVPP

AVPP CONTROL SIGNALS BVPP CONTROL SIGNALS

D8 ( SHDN) D0 D1 D9 D8 ( SHDN) D4 D5 D10

1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X 12 V
1 1 1 X Hi-Z 1 1 1 X Hi-Z
0 X X X Hi-Z 0 X X X Hi-Z

(1) The output V_xVPP is Hi-Z for TPS2223A.

xVCC

AVCC CONTROL SIGNALS BVCC CONTROL SIGNALS

D8

( SHDN)

1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z

D3 D2 D8 ( SHDN) D6 D7

OUTPUT OUTPUT

V_AVPP V_BVPP

(1)

OUTPUT OUTPUT
V_AVCC V_BVCC

1 1 0 X 12 V

(1)

24

www.ti.com

†

Maximum recommended output capacitance for xVCC is 220 µF including card capacitance, and for xVPP is 10 µF, without OC glitch when
switches are powered on.

TPS2226A

V

CC

BVPP

BVCC

BVCC

AVPP

AVCC
AVCC

LATCH

CLOCK

DATA

OC

RESET

V

CC

0.1 µF

†

0.1 µF

†

V

pp1

V

pp2

PC Card

Connector A

V

CC

V

CC

0.1 µF

†

0.1 µF

†

V

pp1

V

pp2

PC Card

Connector B

DATA
CLOCK

LATCH

GPI/O

Controller

From PCI or
System RST

12 V

3.3 V

5 V

12 V

3.3 V

5 V

12 V

3.3 V

3.3 V

5 V

0.1 µF

0.1 µF

0.1 µF

4.7 µF

4.7 µF

4.7 µF

5 V

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

ESD PROTECTIONS (see Figure 35 )

All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.

Figure 35. Detailed Interconnections and Capacitor Recommendations

25

www.ti.com

NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.

TPS2226A

or

TPS2224A

BVPP

BVCC

BVCC

BVCC

†

AVPP

AVCC

†

AVCC

AVCC

LATCH

CLOCK

DATA

OC

RESET

3.3 V

5 V

12 V

3.3 V

†

5 V

12 V

3.3 V

3.3 V

5 V
5 V

SHDN

0.1 µF

0.1 µF1 µF

0.1 µF4.7 µF

EN

REF

SS

COMP

TPS6734

VCC

FB

OUT

GND

1

2

3

4

L1
18 µH

8

7

6

5

R1

10 kΩ

Enable

(see Note A)

C1

33 µF

20 V

C2

0.01 µF

12 V

D1

33 µF, 20 V

C4

0.001 µF

3.3 V or 5 V

+

C1

+

†

Not on TPS2224A

TPS2220A, TPS2223A
TPS2224A, TPS2226A

SLVS428B – MAY 2002 – REVISED SEPTEMBER 2004

12-V FLASH MEMORY SUPPLY

The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V.
The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply
current, wider operating input-voltage range, and higher output currents. As shown in Figure 36 , the only external
components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and
a small capacitor for loop compensation. The entire converter occupies less than 0.7 in
implemented with surface-mount components. An enable input is provided to shut the converter down and
reduce the supply current to 3 µA when 12 V is not needed.

The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7- Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for
external use. For additional information, see the TPS6734 data sheet (SLVS127 ).

2

of PCB space when

26

Figure 36. TPS2224A and TPS2226A with TPS6734 12-V, 120-mA Supply

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

5,60
5,00

M

8,20
7,40

Seating Plane

0,10

0,25
0,09

0°–ā8°

Gage Plane

0,25

0,95
0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2004, Texas Instruments Incorporated