Texas Instruments TPS2114PW, TPS2115PW Schematic [ru]

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1
2
3
4

8
7
6
5

STAT

D0
D1

ILIM

IN1
OUT
IN2
GND

PW PACKAGE

(TOP VIEW)

STAT
D0
D1
ILIM

IN1

OUT

IN2

GND

1
2
3
4

8
7
6
5

TPS2115PW

0.1 µF

0.1 µF

C

L

R

L

IN1: 2.8 - 5.5 V

IN2: 2.8 - 5.5 V

R

ILIM

Switch Status

R1

AUTOSWITCHING POWER MULTIPLEXER

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

FEATURES

• Available in a TSSOP-8 Package

• Two-Input, One-Output Power Multiplexer

With Low r

Switches:

DS(on)

– 84 mΩ Typ (TPS2115)
– 120 mΩ Typ (TPS2114)

• Reverse and Cross-Conduction Blocking

• Wide Operating Voltage Range: 2.8 V to 5.5 V

• Low Standby Current: 0.5 µA Typical

• Low Operating Current: 55 µA Typical

APPLICATIONS

• PCs

• PDAs

• Digital Cameras

• Modems

• Cell phones

• Digital Radios

• MP3 Players

• Adjustable Current Limit

• Controlled Output Voltage Transition Times,

Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance

• CMOS and TTL Compatible Control Inputs

• Manual and Auto-Switching Operating Modes

• Thermal Shutdown

DESCRIPTION

The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a
battery and a wall adapter, each operating at 2.8-5.5 V and delivering up to 1 A. The TPS211x family includes
extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current
control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features
greatly simplify designing power multiplexer applications.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TYPICAL APPLICATION

Copyright © 2002–2004, Texas Instruments Incorporated

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TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

FEATURE TPS2110 TPS2111 TPS2112 TPS2113 TPS2114 TPS2115

Current limit adjustment range 0.31-0.75A 0.63-1.25A 0.31-0.75A 0.63-1.25A 0.31-0.75A 0.63-1.25A

Switching modes

Switch status output No No Yes Yes Yes Yes
Package TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8

T

A

-40°C to 85°C TSSOP-8 (PW)

(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2114PWR) to indicate tape and reel.

PACKAGE DISSIPATION RATINGS

PACKAGE

TSSOP-8 (PW) 3.87 mW/°C 386.84 mW 212.76 mW 154.73 mW

Manual Yes Yes No No Yes Yes
Automatic Yes Yes Yes Yes Yes Yes

ORDERING INFORMATION

PACKAGE ORDERING NUMBER

TPS2114PW 2114
TPS2115PW 2115

DERATING FACTOR TA≤ 25°C TA= 70°C TA= 85°C

ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING

(1)

MARKINGS

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

V

I

V

O

I

O

I

O

T

J

T

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND.

Input voltage range IN1, IN2, D0, D1, ILIM
Output voltage range
Output sink current STAT 5 mA

Continuous output current

Continuous total power dissipation See Dissipation Rating Table
Operating virtual junction temperature range -40°C to 125°C
Storage temperature range -65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(2)

OUT, STAT -0.3 V to 6 V

TPS2114 0.9 A
TPS2115 1.5 A

(1)

TPS2114, TPS2115

(2)

-0.3 V to 6 V

2

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TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

V

≥ 2.8 V 1.5 5.5

V

I

V

I

V

I

I

O(OUT)

T

J

Input voltage at IN1 V

Input voltage at IN2 V

Input voltage at D0, D1 0 5.5 V

Current limit adjustment range A

Operating virtual junction temperature -40 125 °C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Human body model 2 kV
CDM 500 V

ELECTRICAL CHARACTERISTICS

over recommended operating junction temperature range, V

PARAMETER TEST CONDITIONS UNIT

POWER SWITCH

TJ= 25°C,
IL= 500 mA

Drain-source on-state

(1)

r

DS(on)

(1) The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific

resistance (INx-OUT)

TJ= 125°C,
IL= 500 mA

case, the lower supply voltge has no effect on the IN1 and IN2 switch on-resistances.

I(IN2)

V

< 2.8 V 2.8 5.5

I(IN2)

V

≥ 2.8 V 1.5 5.5

I(IN1)

V

< 2.8 V 2.8 5.5

I(IN1)

TPS2114 0.31 0.75
TPS2115 0.63 1.25

MIN MAX UNIT

= V

I(IN1)

I(IN2)

= 5.5 V, R

= 400 Ω (unless otherwise noted)

(ILIM)

TPS2114 TPS2115

MIN TYP MAX MIN TYP MAX

V

= V

I(IN1)

V

I(IN1)

V

I(IN1)

V

I(IN1)

V

I(IN1)

V

I(IN1)

= 5.0 V 120 140 84 110

I(IN2)

= V

= 3.3 V 120 140 84 110 mΩ

I(IN2)

= V

= 2.8 V 120 140 84 110

I(IN2)

= V

= 5.0 V 220 150

I(IN2)

= V

= 3.3 V 220 150 mΩ

I(IN2)

= V

= 2.8 V 220 150

I(IN2)

3

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TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS UNIT

LOGIC INPUTS (D0 AND D1)

V

IH

V

IL

High-level input voltage 2 V
Low-level input voltage 0.7 V

Input current at D0 or D1 µA

D0 or D1 = High, sink current 1
D0 or D1 = Low, source current 0.5 1.4 5

SUPPLY AND LEAKAGE CURRENTS

D1 = High, D0 = Low (IN1 active), V
V

I(IN2)

= 3.3 V, I

= 0 A

O(OUT)

D1 = High, D0 = Low (IN1 active), V
V

= 5.5 V, I

Supply current from IN1 (operating) µA

I(IN2)

D0 = D1 = Low (IN2 active), V
V

= 3.3 V, I

I(IN2)

D0 = D1 = Low (IN2 active), V
V

= 5.5 V, I

I(IN2)

= 0 A

O(OUT)

I(IN1)

= 0 A

O(OUT)

I(IN1)

= 0 A

O(OUT)

D1 = High, D0 = Low (IN1 active), V
V

I(IN2)

= 3.3 V, I

= 0 A

O(OUT)

D1 = High, D0 = Low (IN1 active), V
V

= 5.5 V, I

Supply current from IN2 (operating) µA

I(IN2)

D0 = D1 = Low (IN2 active), V
V

= 3.3 V, I

I(IN2)

D0 = D1 = Low (IN2 active), V
V

= 5.5 V, I

I(IN2)

D0 = D1 = High (inactive), V
V

= 3.3 V, I

Quiescent current from IN1 (STANDBY) µA

I(IN2)

D0 = D1 = High (inactive), V
V

= 5.5 V, I

I(IN2)

D0 = D1 = High (inactive), V
V

= 3.3 V, I

Quiescent current from IN2 (STANDBY) µA

I(IN2)

D0 = D1 = High (inactive), V
V

= 5.5 V, I

I(IN2)

Forward leakage current from IN1 D0 = D1 = High (inactive), V
(measured from OUT to GND) V

= 0 V (shorted), TJ= 25°C

O(OUT)

Forward leakage current from IN2 D0 = D1= High (inactive), V
(measured from OUT to GND) V

= 0 V (shorted), TJ= 25°C

O(OUT)

Reverse leakage current to INx D0 = D1 = High (inactive), V
(measured from INx to GND) V

O(OUT)

= 5.5 V, TJ= 25°C

= 0 A

O(OUT)

= 0 A

= 0 A

= 0 A

= 0 A

= 0 A

I(IN2)

I(IN1)

I(IN1)

I(IN1)

I(IN1)

I(IN1)

I(IN1)

I(IN1)

= 5.5 V, IN1 open,

I(INx)

= 0 A

O(OUT)

O(OUT)

O(OUT)

O(OUT)

O(OUT)

O(OUT)

I(IN1)

I(IN1)

= 5.5 V,

= 3.3 V,

I(IN1)

I(IN1)

= 5.5 V,

= 3.3 V,

= 5.5 V,

= 3.3 V,

= 5.5 V,

= 3.3 V,

= 5.5 V, IN2 open,

= 0 V,

= 5.5 V,

= 3.3 V,

= 5.5 V,

= 3.3 V,

CURRENT LIMIT CIRCUIT

R

= 400 Ω 0.51 0.63 0.80

(ILIM)

R

= 700 Ω 0.30 0.36 0.50

(ILIM)

R

= 400 Ω 0.95 1.25 1.56

(ILIM)

R

= 700 Ω 0.47 0.71 0.99

(ILIM)

Time for short-circuit output current to settle within
10% of its steady state value.

= 0 V, I

I(ILIM)

= 0 A -15 0 µA

O(OUT)

Current limit
accuracy

t

d

TPS2114

TPS2115

Current limit settling time

(1)

Input current at ILIM V

(1) Not tested in production.

TPS2115

MIN TYP MAX

55 90

1 12

75

1

1

75

1 12

55 90

0.5 2

1

1

0.5 2

0.1 5 µA

0.1 5 µA

0.3 5 µA

1 ms

A

4

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TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS UNIT

UNDERVOLTAGE LOCKOUT

IN1 and IN2 UVLO V

IN1 and IN2 UVLO hysteresis

Internal V

Internal V

UVLO (the higher of IN1 and IN2) V

DD

UVLO hysteresis

DD

UVLO deglitch for IN1, IN2

(2)

(2)

(2)

Falling edge 1.15 1.25
Rising edge 1.30 1.35

Falling edge 24 2.53
Rising edge 2.58 2.8

Falling edge 110 µs

REVERSE CONDUCTION BLOCKING

∆V

O(I_block)

Minimum output-to-input voltage V supply through a series 1-kΩ resistor. Let
difference to block switching D0 = low. Slowly decrease the supply voltage until

D0 = D1 = high, V

= 3.3 V. Connect OUT to a 5

I(INx)

OUT connects to IN1.

THERMAL SHUTDOWN

Thermal shutdown threshold
Recovery from thermal shutdown
Hysteresis

(2)

(2)

(2)

TPS211x is in current limit. 135
TPS211x is in current limit. 125 °C

IN2-IN1 COMPARATORS

Hysteresis of IN2-IN1 comparator 0.1 0.2 V
Deglitch of IN2-IN1 comparator, (both↑↓ )

(2)

STAT OUTPUT

Leakage current V
Saturation voltage I

= 5.5 V 0.01 1 µA

O(STAT)

= 2 mA, IN1 switch is on 0.13 0.4 V

I(STAT)

Deglitch time (falling edge only) 150 µs

(2) Not tested in production.

TPS2115

MIN TYP MAX

30 57 65 mV

30 50 75 mV

80 100 120 mV

10

90 150 220 µs

5

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TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

SWITCHING CHARACTERISTICS

over recommended operating junction temperature range, V

PARAMETER TEST CONDITIONS UNIT

POWER SWITCH

Output rise time from an

t

r

t

f

t

t

t

PLH1

t

PHL1

t

PLH2

t

PHL2

(1)

enable

Output fall time from a

(1)

disable

Transition time

Turnon propagation delay CL= 10 µF,
from enable

Turnoff propagation delay CL= 10 µF,
from a disable

Switch-over rising CL= 10 µF,
propagation delay

Switch-over falling CL= 10 µF,
propagation delay

(1)

(1)

(1)

(1)

(1)

V

= V

I(IN1)

V

I(IN1)

= 5 V IL= 500 mA, 0.5 1.0 1.5 1 1.8 3 ms

I(IN2)

= V

= 5 V IL= 500 mA, 0.35 0.5 0.7 0.5 1 2 ms

I(IN2)

IN1 to IN2 transition, TJ= 125°C,
V

= 3.3 V, CL= 10 µF, 40 60 40 60

I(IN1)

V

= 5 V IL= 500 mA [Measure

I(IN2)

IN2 to IN1 transition,
V

= 5 V, 40 60 40 60

I(IN1)

V

= 3.3 V

I(IN2)

V

= V

I(IN1)

Measured from enable 0.5 1 ms
to 10% of V

V

I(IN1)

Measured from disable 3 5 ms
to 90% of V

= 5 V,

I(IN2)

O(OUT)

= V

= 5 V,

I(IN2)

O(OUT)

Logic 1 to Logic 0 tran­sition on D1,
V

= 1.5 V,

I(IN1)

V

= 5 V, 0.17 1 0.17 1 ms

I(IN2)

V

= 0 V,

I(D0)

Measured from D1 to
10% of V

O(OUT)

Logic 0 to Logic 1 tran­sition on D1,
V

= 1.5 V,

I(IN1)

V

= 5V, 2 3 10 2 5 10 ms

I(IN2)

V

= 0 V, Measured

I(D0)

from D1 to 90% of
V

O(OUT)

= V

I(IN1)

I(IN2)

TJ= 25°C, CL= 1 µF,
See Figure 1 (a)

TJ= 25°C, CL= 1 µF,
See Figure 1(a)

transition time as
10-90% rise time or
from 3.4 V to 4.8 V
on V
See Figure 1 (b)

],

O(OUT)

TJ= 25°C,
IL= 500 mA,

SeeFigure 1 (a)
TJ= 25°C,

IL= 500 mA,
See Figure 1 (a)

TJ= 25°C,
IL= 500 mA,

See Figure 1 (c)

TJ= 25°C,
IL= 500 mA,

See Figure 1 (c)

= 5.5 V, R

= 400 Ω (unless otherwise noted)

(ILIM)

TPS2114 TPS2115

MIN TYP MAX MIN TYP MAX

µs

(1) Not tested in production.

6

TRUTH TABLE

D1 D0 V

0 0 X Hi-Z IN2
0 1 No 0 IN1
0 1 Yes Hi-Z IN2
1 0 X 0 IN1
1 1 X 0 Hi-Z

(1) The under-voltage lockout circuit causes the output OUT to go Hi-Z

if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal V

> V

I(IN2)

I(IN1)

STAT OUT

UVLO.

DD

(1)

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Q2 is ON

1

STAT

Control

Logic

D1

D0

UVLO (IN1)

UVLO (IN2)

UVLO (VDD)

Q2 is ON

Q1 is ON

_

+

_

+

+

0.6 V

EN2

EN1

Cross-Conduction
Detector

_
+

Q2

Q1

Charge

Pump

0.5 V

TPS2114: k = 0.2%
TPS2115: k = 0.1%

k* I

O(OUT)

_

+

V

O(OUT)

> V

I(INx)

+

100 mV

_

+

I

O(OUT)

Vf = 0 V

EN1

IN2
IN1

7

4

OUT

ILIM

Internal V

DD

Vf = 0 V

V

DD

ULVO

Thermal

Sense

1 µA

IN2

ULVO

1 µA

IN1

ULVO

8

6

2
3

5

IN1

IN2

D0
D1

GND

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

Terminal Functions

TERMINAL

NAME NO.

D0 2 I TTL and CMOS compatible input pins. Each pin has a 1-µA pullup resistor. The truth table shown above illustrates
D1 3 I
GND 5 I Ground
IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and

IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold

ILIM 4 I A resistor R

OUT 7 O Power switch output
STAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is

FUNCTIONAL BLOCK DIAGRAM

I/O DESCRIPTION

the functionality of D0 and D1.

at least one supply exceeds the internal V

and at least one supply exceeds the internal V

from ILIM to GND sets the current limit ILto 250/R

TPS2115, respectively.

(ILIM)

Hi-Z (i.e., EN is equal to logic 0).

UVLO.

DD

UVLO.

DD

and 500/R

(ILIM)

for the TPS2114 and

(ILIM)

7

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0 V

10%

90%

Switch Enabled

Switch Off

Switch Off

90%

10%

3.3 V

5 V

Switch #1 Enabled

Switch #2 Enabled

4.8 V

3.4 V

DO-D1

1.5 V

1.85 V

4.65 V

Switch #2 EnabledSwitch #1 Enabled Switch #1 Enabled

5 V

t

r

t

f

t

PLH1

t

PHL1

V

O(OUT)

t

t

V

O(OUT)

V

O(OUT)

DO-D1

t

PLH2

t

PHL2

(a)

(b)

(c)

DO-D1

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

PARAMETER MEASUREMENT INFORMATION

Figure 1. Propagation Delays and Transition Timing Waveforms

8

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V

I(DO)

V

I(D1)

V

O(OUT)

t - Time - 1 ms/div

2V/Div

2V/Div

2V/Div

STAT
D0

D1

ILIM

IN1

OUT
IN2

GND

1

2
3
4

8
7

6
5

TPS2115PW

0.1 µF

0.1 µF

50 Ω

5 V

3.3 V

400 Ω

f = 28 Hz

78% Duty Cycle

Output Switchover Response Test Circuit

OUTPUT SWITCHOVER RESPONSE

NC

1
µF

t − Time − 2 ms/div

V

I(DO)

V

I(D1)

V

O(OUT)

2V/Div

2V/Div

2V/Div

STAT
D0

D1

ILIM

IN1

OUT

IN2

GND

1
2

3
4

8
7

6
5

TPS2115PW

0.1 µF

0.1 µF

50 Ω

5 V

3.3 V

400 Ω

f = 28 Hz

78% Duty Cycle

1
µF

OUTPUT TURNON RESPONSE

Output Turnon Response Test Circuit

NC

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

TYPICAL CHARACTERISTICS

Figure 2.

Figure 3.

9

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CL = 1 µF

CL = 0 µF

t - Time - 40 µs/div

V

I(DO)

V

I(D1)

V

O(OUT)

2V/Div

2V/Div

2V/Div

Output Switchover Voltage Droop Test Circuit

OUTPUT SWITCHOVER VOLTAGE DROOP

STAT
D0

D1

ILIM

IN1

OUT

IN2

GND

1

2
3
4

8
7

6
5

TPS2115PW

0.1 µF

0.1 µF

50 Ω

400 Ω

f = 580 Hz

90% Duty Cycle

5 V

NC

0 µF

C

L

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

TYPICAL CHARACTERISTICS (continued)

Figure 4.

10

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0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0.1 1 10 100

RL = 10 Ω

RL = 50 Ω

VI = 5 V

- Output Voltage Droop - V

CL - Load Capacitance - µF

OUTPUT SWITCHOVER VOLTAGE DROOP

vs

LOAD CAPACITANCE

D0
D1
VSNS
ILIM

IN1

OUT

IN2

GND

1
2
3
4

8
7
6
5

TPS2115PW

0.1 µF

0.1 µF

V

I

400 Ω

0.1 µF 1 µF 10 µF 47 µF 100 µF

50 Ω 10 Ω

f = 28 Hz

50% Duty Cycle

Output Switchover Voltage Droop Test Circuit

O(OUT)

∆V

NC

TYPICAL CHARACTERISTICS (continued)

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

Figure 5.

11

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0

50

100

150

200

250

300

0 20 40 60 80 100

VI = 5 V

VI = 3.3 V

Inrush Current - mA

CL - Load Capacitance - µF

INRUSH CURRENT

vs

LOAD CAPACITANCE

STAT
D0
D1
ILIM

IN1

OUT

IN2

GND

1
2
3
4

8
7
6
5

TPS2115PW

0.1 µF

0.1 µF

V

I

400 Ω

0.1 µF 47 µF10 µF

50 Ω

To Oscilloscope

1 µF 100 µF

f = 28 Hz

90% Duty Cycle

Output Capacitor Inrush Current Test Circuit

I

I

-

NC

NC

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

TYPICAL CHARACTERISTICS (continued)

Figure 6.

12

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−50 0 50 100 150
TJ − Junction Temperature − °C

60

80

100

120

140

160

180

TPS2114

TPS2115

− Switch On-Resistance − mΩ

r

DS(on)

2 3 4 5 6

V

I(INx)

− Supply Voltage − V

80

85

90

95

100

105

110

115

120

TPS2114

TPS2115

− Switch On-Resistance − mΩ

r

DS(on)

40

42

44

46

48

50

52

54

56

58

60

2 3 4 5 6

V

I(IN1)

− Supply Voltage − V

I(IN1)

− IN1 Supply Current −

Aµ

IN1 Switch is ON
V

I(IN2)

= 0 V,

I

O(OUT)

= 0 A

I

0.82

0.84

0.86

0.88

0.90

0.92

0.94

0.96

2 3 4 5 6

I(IN1)

Aµ

V

I(IN1)

− IN1 Supply Voltage − V

Device Disabled
V

I(IN2)

= 0 V

I

O(OUT)

= 0 A

I − IN1 Supply Current −

TYPICAL CHARACTERISTICS (continued)

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE

vs vs

JUNCTION TEMPERATURE SUPPLY VOLTAGE

Figure 7. Figure 8.

IN1 SUPPLY CURRENT IN1 SUPPLY CURRENT

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 9. Figure 10.

13

www.ti.com

0

10

20

30

40

50

60

70

80

−50 0 50 100 150

I

I(IN1)

I

I(IN2)

TJ − Junction Temperature − °C

IN1 Switch is ON
V

I(IN1)

= 5.5 V,

V

I(IN2)

= 3.3 V

I

O(OUT)

= 0 A

I(INx)

Supply Current − − Aµ

I

0

0.2

0.4

0.6

0.8

1

1.2

−50 0 50 100 150

I

I(IN1)

= 5.5 V

I

I(IN2) =

3.3 V

Device Disabled

TJ − Junction Temperature − °C

I(INx)

Supply Current − − Aµ

V

I(IN1)

= 5.5 V

V

I(IN2)

= 3.3 V

I

O(OUT)

= 0 A

I

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT SUPPLY CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 11. Figure 12.

14

www.ti.com

STAT
D0
D1
ILIM

IN1

OUT

IN2

GND

1
2
3
4

8
7
6
5

TPS2115PW

0.1 µF

C2

0.1 µF

C

L

R

L

IN1: 2.8 - 5.5 V

IN2: 2.8 - 5.5 V

R

ILIM

NC

Switch Status

R1

STAT
D0
D1
ILIM

IN1

OUT

IN2

GND

1
2
3
4

8
7
6
5

TPS2115PW

0.1 µF

0.1 µF

C

L

R

L

IN1: 2.8 - 5.5 V

IN2: 2.8 - 5.5 V

R

ILIM

Switch Status

R1

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

APPLICATION INFORMATION

The circuit in Figure 13 allows one or two battery packs to power a system. Two battery packs allow a longer run
time. The TPS2114/5 cycles between the battery packs until both packs are drained.

Figure 13. Running a System From Two Battery Packs

In Figure 14 , the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.

Figure 14. Manually Switching Power Sources

15

www.ti.com

TPS2114
TPS2115

SLVS447A – DECEMBER 2002 – REVISED MARCH 2004

DETAILED DESCRIPTION

AUTO-SWITCHING MODE

D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.

MANUAL SWITCHING MODE

D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.

N-CHANNEL MOSFETs

Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turnon of a FET
switch if the output voltage is greater than the input voltage.

CROSS-CONDUCTION BLOCKING

The switching circuitry ensures that both power switches never conduct at the same time. A comparator monitors
the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of
the other FET is below the turnon threshold voltage.

REVERSE-CONDUCTION BLOCKING

When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow
back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x
does not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.
Once a supply has been connected to the output, it remains connected regardless of output voltage.

CHARGE PUMP

The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.

CURRENT LIMITING

A resistor R
TPS2115, respectively. Setting resistor R

from ILIM to GND sets the current limit to 250/ R

(ILIM)

equal to zero is not recommended as that disables current limiting.

(ILIM)

and 500/R

(ILIM)

for the TPS2114 and

(ILIM)

OUTPUT VOLTAGE SLEW-RATE CONTROL

The TPS2114/5 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
adversely effect the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like
pit the connector power contacts, when hot plugging a load like a PCI card. The TPS2114/5 slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.

16

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status

TPS2114PW ACTIVE TSSOP PW 8 150 Green (RoHS

TPS2114PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS

TPS2115PW ACTIVE TSSOP PW 8 150 Green (RoHS

TPS2115PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS

TPS2115PWR ACTIVE TSSOP PW 8 2000 Green (RoHS

TPS2115PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2114

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2114

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2115

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2115

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2115

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2115

Op Temp (°C) Top-Side Markings

(4)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

11-Apr-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jun-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TPS2115PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jun-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2115PWR TSSOP PW 8 2000 367.0 367.0 35.0

Pack Materials-Page 2

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