Texas Instruments TPS2101DR, TPS2101DBVT, TPS2101DBVR, TPS2100DR, TPS2101D Datasheet

TPS2100, TPS2101

V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Dual-Input, Single-Output MOSFET Switch
With No Reverse Current Flow (No Parasitic
Diodes)

D

IN1 . . . 250-mΩ, 500-mA N-Channel;
16-µA Max Supply Current

D

IN2 . . . 1.3-Ω, 10-mA P-Channel;

1.5-µA Max Supply Current (V

AUX

Mode)

D

Advanced Switch Control Logic

D

CMOS- and TTL-Compatible Enable Input

D

Controlled Rise, Fall, and Transition Times

D

2.7-V to 4 V Operating Range

D

SOT-23-5 and SOIC-8 Package

D

–40°C to 70°C Ambient Temperature Range

D

2-kV Human-Body-Model, 750-V CDM,
200-V Machine-Model Electrostatic­Discharge Protection

typical applications

D

Notebook and Desktop PCs

D

Palmtops and PDAs

description

The TPS2100 and TPS2101 are dual-input, single-output power switches designed to provide uninterrupted
output voltage when transitioning between two independent power supplies. Both devices combine one
n-channel (250 mΩ) and one p-channel (1.3 Ω) MOSFET with a single output. The p-channel MOSFET (IN2)
is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET
(IN1) is used with a main power supply that delivers higher current required for normal operation. Low
on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation
and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to

0.75 µA to decrease the demand on the standby power supply . The MOSFETs in the TPS2100 and TPS2101
do not have the parasitic diodes, found in discrete MOSFETs, which allow the devices to prevent back-flow
current when the switch is off.

DBV PACKAGE

(TOP VIEW)

GND

IN2

IN1

OUT

EN

GND

IN2

IN1

OUT

EN

DBV PACKAGE

(TOP VIEW)

TPS2100

TPS2101

NC – No internal connection

Figure 2. V

AUX

CardBus Implementation

PCI12xx / PCI14xx

CardBus Controller

PCI Bus

V

AUX

3.3 V

VGA TPS210x

V

CC

D3-STAT

1
2
3
4

8
7
6
5

IN2

GND

EN
NC

OUT
OUT
NC
IN1

D PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

IN2

GND

EN

NC

OUT
OUT
NC
IN1

1
2
3

5

4

1
2
35 4

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Typical Dual-Input Single-Output

Application

TPS2100

IN1
IN2

EN

3.3 V V

CC

3.3 V V

AUX

D3 or PME Status

Control Signal

Hold-Up

Capacitor

Controller
(CardBus,

1394,

PCI,

et al.)

3.3 V

TPS2100, TPS2101
V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

T

J

DEVICE ENABLE

SOT-23-5

(DBV)

†

SOIC-8

(D)

°

°

TPS2100 EN TSP2100DBV

†

TPS2100D

–

40°C to 85°C

TPS2101 EN TPS2101DBV

†

TPS2101D

Both packages are available left-end taped and reeled. Add an R suffix to the D device type
(e.g., TPS2101DR).

†

Add T (e.g., TPS2100DBVT) to indicate tape and reel at order quantity of 250 parts.
Add R (e.g., TPS2100DBVR) to indicate tape and reel at order quantity of 3000 parts.

TPS2100 functional block diagram

V

CC

Select

Charge

Pump

Driver

GND

OUT

SW2

1.3 Ω

SW1

250 mΩ

Pullup
Circuit

Driver

IN1

EN

IN2

Discharge
Circuit

TPS2101 functional block diagram

V

CC

Select

Charge

Pump

Driver

GND

OUT

SW2

1.3 Ω

SW1

250 mΩ

Driver

IN1

EN

IN2

Pulldown

Circuit

Discharge
Circuit

TPS2100, TPS2101

V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

TPS2100 TPS2101

VIN1 VIN2 EN OUT VIN1 VIN2 EN OUT

0 V 0 V XX GND 0 V 0 V XX GND
0 V 3.3 V L GND 0 V 3.3 V H GND

3.3 V 3.3 V L VIN1 3.3 V 3.3 V H VIN1

3.3 V 0 V L VIN1 3.3 V 0 V H VIN1
0 V 3.3 V H VIN2 0 V 3.3 V L VIN2

3.3 V 0 V H VIN2 3.3 V 0 V L VIN2

3.3 V 3.3 V H VIN2 3.3 V 3.3 V L VIN2

XX = don’t care

Terminal Functions

TERMINAL

NO.

NAME

TPS2100 TPS2101

I/O

DESCRIPTION

DBV D DBV D

EN 1 3 Active-high enable for IN1-OUT switch
EN 1 3 I Active-low enable for IN1-OUT switch

GND 2 2 2 2 I Ground

IN1 5 5 5 5 I Main Input voltage, NMOS drain (250 mΩ)
IN2 3 1 3 1 I Auxilliary input voltage, PMOS drain (1.3 Ω)

OUT 4 7, 8 4 7, 8 O Power switch output

NC 4, 6 4, 6 No connection

detailed description

power switches

n-channel MOSFET

The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 3.3-V input voltage,
and is configured as a high-side switch.

p-channel MOSFET

The IN2-OUT p-channel MOSFET power switch with typical on-resistance of 1.3 Ω at 3.3-V input voltage and
is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to
less than 1.5 µA.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.

driver

The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. T o limit large current surges
and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that
controls the rise times and fall times of the output voltage.

TPS2100, TPS2101
V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

enable

The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN

(TPS2100) or logic
low is present on EN (TPS2101). A logic low input on EN (TPS2100) or logic high on EN (TPS2101) restores
bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible
with both TTL and CMOS logic levels.

the V

AUX

application for CardBus controllers

The PC Card specification requires the support of V

AUX

to the CardBus controller as well as to the PC Card

sockets. Both are 3.3-V requirements; however the CardBus controller’s current demand from the V

AUX

supply
is limited to 10 µA, whereas the PC Card may consume as much as 200 mA. In either implementation, if support
of a wake-up event is required, the controller and the socket will transition from the 3.3-V VCC rail to the 3.3-V
V

AUX

rail when the equipment moves into a low power mode such as D3. The transition from VCC to V

AUX

needs

to be seamless in order to maintain all memory and register information in the system. If V

AUX

is not supported,

the system will lose all register information when it transitions to the D3 state.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Input voltage range, V

I(IN1)

(see Note1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I(IN2)

(see Note1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI at EN or EN –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O(IN1

) 700 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O(IN2)

70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Machine model 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Charged device model (CDM) 750 V. . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA < 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DBV 309 mW 3.1 mW/°C 170 mW 123 mW

D 568 mW 5.7 mW/°C 313 mW 227 mW

recommended operating conditions

MIN MAX UNIT

Input voltage, V

I(INx)

2.7 4 V
Input voltage, VI at EN and EN 0 4 V
Continuous output current, I

O(IN1)

500 mA

Continuous output current, I

O(IN2)

100‡mA

Operating virtual junction temperature, T

J

–40 85 °C

‡

The device can deliver up to 220 mA at I

O(IN2)

. However, operation at the higher current levels will result in greater voltage drop across the device,

and greater voltage droop when switching between IN1 and IN2.

TPS2100, TPS2101

V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range,
V

I(IN1)

= V

(IN2)

= 3.3 V, IO = rated current (unless otherwise noted)

power switch

PARAMETER

TEST

CONDITIONS

†

MIN TYP MAX UNIT

TJ = 25°C 250

IN1-OUT

TJ = 85°C 300 375

mΩ

r

DS(on)

On-state resistance

TJ = 25°C 1.3

IN2-OUT

TJ = 85°C 1.5 2.1

Ω

†

Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal effects must be taken into account separately.

enable input (EN and EN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IH

High-level input voltage 2.7 V ≤ V

I(INx)

≤ 4 V 2 V

V

IL

Low-level input voltage 2.7 V ≤ V

I(INx)

≤ 4 V 0.8 V

p

TPS2100 EN = 0 V or EN = V

I(INx)

–0.5 0.5 µA

IIInput current

TPS2101 EN = 0 V or EN = V

I(INx)

–0.5 0.5 µA

supply current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EN = H

,

TJ = 25°C 0.75

EN H,

IN2 selected

–40°C ≤ TJ ≤ 85°C 1.5

µ

A

TPS2100

EN = L

,

TJ = 25°C 10

pp

EN L,

IN1 selected

–40°C ≤ TJ ≤ 85°C 16

µ

A

IISupply current

EN = L,

TJ = 25°C 0.75

,

IN2 selected

–40°C ≤ TJ ≤ 85°C 1.5

µ

A

TPS2101

EN = H,

TJ = 25°C 10

,

IN1 selected

–40°C ≤ TJ ≤ 85°C 16

µ

A

TPS2100, TPS2101
V

AUX

POWER-DISTRIBUTION SWITCHES

SLVS197C – JUNE 1999 – REVISED APRIL 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, TJ = 25°C, V

I(IN1)

= V

I(IN2)

= 3.3 V (unless otherwise noted)

†

PARAMETER TEST CONDITIONS

†

MIN TYP MAX UNIT

CL = 1 µF, IL = 500 mA 830

IN1-OUT V

I(IN2)

= 0

CL = 10 µF, IL = 500 mA 840

p

()

CL = 1 µF, IL = 10 mA 640

trOutput rise time

CL = 1 µF, IL = 10 mA 5.5

µ

s

IN2-OUT V

I(IN1)

= 0

CL = 10 µF, IL = 10 mA 70

()

CL = 1 µF, IL = 1 mA 5.5
CL = 1 µF, IL = 500 mA 8

IN1-OUT V

I(IN2)

= 0

CL = 10 µF, IL = 500 mA 93

p

()

CL = 1 µF, IL = 10 mA 23

tfOutput fall time

CL = 1 µF, IL = 10 mA 690

µ

s

IN2-OUT V

I(IN1)

= 0

CL = 10 µF, IL = 10 mA 6900

()

CL = 1 µF, IL = 1 mA 6900

p

p

IN1-OUT V

I(IN2)

= 0

75

t

PLH

Propagation delay time, low-to-high output

IN2-OUT V

I(IN1)

= 0

C

L

= 10 µF,

I

L

= 10

mA

2

µ

s

p

p

IN1-OUT V

I(IN2)

= 0

3

t

PHL

Propagation delay time, high-to-low output

IN2-OUT V

I(IN1)

= 0

C

L

= 10 µF,

I

L

= 10

mA

370

µ

s

†

All timing parameters refer to Figure 3.