Texas Instruments TPS2061D, TPS2061DBV, TPS2061DGN, TPS2062D, TPS2062DGN Schematic [ru]

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TPS2062/TPS2066

D ANDDGNPACKAGE

(TOP VIEW)

†

AllEnableInputs Are ActiveHighForTPS2065,TPS2066,andTPS2067

GND

TPS2063/TPS2067

DPACKAGE (TOP VIEW)

TPS2061/TPS2065

D ANDDGNPACKAGE

(TOP VIEW)

2 3 4 5 6 7

16 15 14

13 12 11 10

IN1

GND

IN2

OC1 OUT1 OUT2

OUT3 NC

GND

IN IN

OUT

OUT OUT

GND

OC1 OUT1 OUT2

OC2

OC3

OC2

1 2 3 4

8 7 6 5

1 2 3 4

8 7 6 5

EN3

†

EN1

†

EN1

†

EN2

†

EN2

†

GND

OUT

TPS2061/TPS2065

DBVPACKAGE

(TOP VIEW)

†

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES

Check for Samples: TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

FEATURES

• 70-mΩ High-Side MOSFET

• 1-A Continuous Current

APPLICATIONS

• Heavy Capacitive Loads

• Short-Circuit Protections

• Thermal and Short-Circuit Protection

• Accurate Current Limit (1.1 A min, 1.9 A max)

• Operating Range: 2.7 V to 5.5 V

• 0.6-ms Typical Rise Time

• Undervoltage Lockout

• Deglitched Fault Report (OC)

• No OC Glitch During Power Up

• 1-μA Maximum Standby Supply Current

• Bidirectional Switch

• Ambient Temperature Range: -40°C to 85°C

• Built-in Soft-Start

• UL Listed - File No. E169910

DESCRIPTION

The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches for power-distribution systems that require multiple power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V.

2PowerPAD is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1.5 A typically.

AVAILABLE OPTION AND ORDERING INFORMATION

RECOMMEND TYPICAL PACKAGED

ED SHORT- DEVICES

-40°C to 85°C 1 A 1.5 A

(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2062DR). (2) The printed circuit board layout is important for control of temperature rise when operated at high ambient temperatures.

ENABLE

Active low TPS2061DGN TPS2061D -

Active high TPS2065DGN TPS2065D -

Active low TPS2062DGN TPS2062D -

Active high TPS2066DGN TPS2066D -

Active low - TPS2063D -

Active high - TPS2067D -

Active low - - TPS2061DBV

Active high - - TPS2065DBV

MAXIMUM CIRCUIT NUMBER OF

CONTINUOUS CURRENT SWITCHES

LOAD LIMIT

CURRENT AT 25°C

Single

Dual

Triple

Single

MSOP (DGN) SOIC (D) SOT23 (DBV)

spacer

ORDERING INFORMATION

-40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) The printed circuit board layout is important for control of temperature rise when operated at high ambient temperatures.

SOIC(D)

TPS2061DG4 Active TPS2061DGNG4 Active - TPS2062DG4 Active TPS2062DGNG4 Active - TPS2065DG4 Active TPS2065DGNG4 Active - TPS2066DG4 Active TPS2066DGNG4 Active - -

(1)

- - - - TPS2061DBV Active

- - - - TPS2065DBV Active

STATUS MSOP (DGN)

(1)

STATUS SOT23 (DBV)

(1)

(2)

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(2)

STATUS

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

, V

I(IN)

O(OUT)

I(EN)

I(OCx)

(2)

, V

(2)

I(EN)

O(OUT)

, V , V

, I

O(OUTx) I(ENx)

O(OUTx)

, V

I(ENx)

Human body model 2 kV Charge device model (CDM) 500 V

Input voltage range, V Output voltage range, V Input voltage range, V Voltage range, V

I(OC)

Continuous output current, I Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, T

Electrostatic discharge (ESD) protection

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND.

(1)

UNIT

-0.3 V to 6 V

Internally limited

-40°C to 150°C

DISSIPATING RATING TABLE

PACKAGE

(1)

D-8

(2)

DGN-8

(1)

D-16

(3)

DBV-5

(1) Power ratings are based on the low-k board (1 signal, 1 layer). (2) Power ratings are based on the high-k board (2 signal, 2 plane) with PowerPAD™ vias to the internal ground plane. (3) Lower ratings are for low-k printed circuit board layout (single -sided). Higher ratings are for enhanced high-k layout, (2 signal, 2 plane)

with a 1mm2copper pad on pin 2 and 2 vias to the ground plane.

TA≤ 25°C DERATING FACTOR TA= 70°C TA= 85°C

POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING

585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW

1712.3 mW 17.123 mW/°C 941.78 mW 684.33 mW

898.47 mW 8.9847 mW/°C 494.15 mW 359.38 mW 285 mW 2.85 mW/°C 155 mW 114 mW 704 mW 7.04 mW/°C 387 mW 281 mW

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Input voltage, V Input voltage, V Continuous output current, I

I(IN) I(EN)

, V

I(EN)

, V

O(OUT)

I(ENx)

, V

I(ENx)

, I

O(OUTx)

Operating virtual junction temperature, T

2.7 5.5 V 0 5.5 V 0 1 A

-40 125 °C

ELECTRICAL CHARACTERISTICS

over recommended operating junction temperature range, V otherwise noted)

PARAMETER TEST CONDITIONS

POWER SWITCH

Static drain-source on-state resistance, 5-V operation V

DS(on)

and 3.3-V operation Static drain-source on-state

resistance, 2.7-V V operation

Rise time, output

Fall time, output

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

= 5 V or 3.3 V, IO= 1 A, -40°C ≤ TJ≤ 125°C 70 135 mΩ

I(IN)

= 2.7 V, IO= 1 A, -40°C ≤ TJ≤ 125°C 75 150 mΩ

I(IN)

= 5.5 V 0.6 1.5

I(IN)

= 2.7 V 0.4 1

I(IN)

= 5.5 V 0.05 0.5

I(IN)

= 2.7 V 0.05 0.5

I(IN)

= 5.5 V, IO= 1 A, V

I(IN)

(1)

CL= 1 μF, RL= 5 Ω, TJ= 25°C ms

I(ENx)

= 0 V, or V

= 5.5 V (unless

I(ENx)

MIN TYP MAX UNIT

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating junction temperature range, V otherwise noted)

PARAMETER TEST CONDITIONS

ENABLE INPUT EN OR EN

off

CURRENT LIMIT

OC_TRIP

SUPPLY CURRENT (TPS2061, TPS2065)

Supply current, low-level output μA

Supply current, high-level output μA

Leakage current -40°C ≤ TJ≤ 125°C 1 μA Reverse leakage current V

SUPPLY CURRENT (TPS2062, TPS2066)

Supply current, low-level output μA

Supply current, high-level output μA

Leakage current -40°C ≤ TJ≤ 125°C 1 μA Reverse leakage current V

SUPPLY CURRENT (TPS2063, TPS2067)

Supply current, low-level output No load on OUT, V

Supply current, high-level output No load on OUT, V

Leakage current -40°C ≤ TJ≤ 125°C 1 μA Reverse leakage current V

UNDERVOLTAGE LOCKOUT

Low-level input voltage, IN 2 2.5 V Hysteresis, IN TJ= 25°C 75 mV

OVERCURRENT OC1 and OC2

Output low voltage, V Off-state current V OC deglitch OCx assertion or deassertion 4 8 15 ms

THERMAL SHUTDOWN

Thermal shutdown threshold 135 °C Recovery from thermal shutdown 125 °C Hysteresis 10 °C

(2) The thermal shutdown only reacts under overcurrent conditions.

High-level input voltage 2.7 V ≤ V Low-level input voltage 2.7 V ≤ V Input current V

I(ENx)

≤ 5.5 V 2

I(IN)

≤ 5.5 V 0.8

I(IN)

= 0 V or 5.5 V, V

I(ENx)

Turnon time CL= 100 μF, RL= 5 Ω 3 Turnoff time CL= 100 μF, RL= 5 Ω 10

= 5 V, OUT connected to GND,

Short-circuit output current A

Overcurrent trip threshold V

I(IN)

device enabled into short-circuit

= 5 V, current ramp (≤ 100 A/s) on OUT A

I(IN)

No load on OUT, V or V

= 0 V

I(ENx)

No load on OUT, V or V

= 5.5 V

I(ENx)

= 5.5 V,

= 0 V,

OUT connected to ground, V or V

= 0 V

I(EN)

= 5.5 V, IN = ground TJ= 25°C 0 μA

I(OUTx)

No load on OUT, V or V

= 0 V

I(ENx)

No load on OUT, V or V

= 5.5 V

I(ENx)

= 5.5 V,

= 0 V,

OUT connected to ground, V or V

= 0 V

I(ENx)

= 5.5 V, IN = ground TJ= 25°C 0.2 μA

I(OUTx)

= 0 V μA

I(ENx)

= 5.5 V μA

I(ENx)

OUT connected to ground, V or V

= 0 V

I(ENx)

= 5.5 V, INx = ground TJ= 25°C 0.2 μA

I(OUTx)

OL(OCx)

(2)

= 5 mA 0.4 V

O(OCx)

= 5 V or 3.3 V 1 μA

O(OCx)

= 5.5 V, IO= 1 A, V

I(IN)

(1)

I(ENx)

= 0 V, or V

= 5.5 V (unless

I(ENx)

MIN TYP MAX UNIT

= 0 V or 5.5 V -0.5 0.5 μA

TJ= 25°C 1.1 1.5 1.9

-40°C ≤ TJ≤ 125°C 1.1 1.5 2.1 TPS2061, TPS2062,

TPS2065, TPS2066

1.6 2.3 2.7

TPS2063, TPS2067 1.6 2.4 3.0

TJ= 25°C 0.5 1

-40°C ≤ TJ≤ 125°C 0.5 5 TJ= 25°C 43 60

-40°C ≤ TJ≤ 125°C 43 70

= 5.5 V,

I(EN)

TJ= 25°C 0.5 1

-40°C ≤ TJ≤ 125°C 0.5 5 TJ= 25°C 50 70

-40°C ≤ TJ≤ 125°C 50 90

= 5.5 V,

I(/ENx)

TJ= 25°C 0.5 2

-40°C ≤ TJ≤ 125°C 0.5 10 TJ= 25°C 65 90

-40°C ≤ TJ≤ 125°C 65 110

= 5.5 V,

I(ENx)

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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

OUT

GND

Current

Limit

Driver

UVLO

Charge

Pump

Thermal

Sense

Deglitch

Note A: Current sense Note B: Active low (EN

) for TPS2061. Active high (EN) for TPS2065.

(See Note A)

(See Note B)

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

www.ti.com

DEVICE INFORMATION

Pin Functions (TPS2061 and TPS2065)

PINS

D or DGN Package DBV Package I/O DESCRIPTION

NAME TPS2061 TPS2065 TPS2061 TPS2065

EN 4 - 4 - I Enable input, logic low turns on power switch EN - 4 - 4 I Enable input, logic high turns on power switch GND 1 1 2 2 Ground IN 2, 3 2,3 5 5 I Input voltage OC 5 5 3 3 O Overcurrent, open-drain output, active-low OUT 6, 7, 8 6, 7, 8 1 1 O Power-switch output

PowerPAD™ - - - - to the circuit board traces. Should be connected to GND

Functional Block Diagram

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Internally connected to GND; used to heat-sink the part pin.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

Thermal

Sense

Driver

Current

Limit

Charge

Pump

UVLO

Driver

Current

Limit

Thermal

Sense

Charge

Pump

GND

EN1

EN2

OC1

OUT1

OUT2

OC2

Deglitch

(See Note A)

(See Note B)

Note A: Current sense Note B: Active low (ENx

) for TPS2062. Active high (ENx) for TPS2066.

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Pin Functions (TPS2062 and TPS2066)

PINS

NAME NO.

TPS2062 TPS2066

EN1 3 - I Enable input, logic low turns on power switch IN-OUT1 EN2 4 - I Enable input, logic low turns on power switch IN-OUT2 EN1 - 3 I Enable input, logic high turns on power switch IN-OUT1 EN2 - 4 I Enable input, logic high turns on power switch IN-OUT2 GND 1 1 Ground IN 2 2 I Input voltage OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 7 O Power-switch output, IN-OUT1 OUT2 6 6 O Power-switch output, IN-OUT2

PowerPAD™ - -

I/O DESCRIPTION

Internally connected to GND; used to heat-sink the part to the circuit board traces. Should be connected to GND pin.

Functional Block Diagram

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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

www.ti.com

Pin Functions (TPS2063 and TPS2067)

PINS

NAME TPS2063 TPS2067

EN1 3 – I Enable input, logic low turns on power switch IN1-OUT1 EN2 4 – I Enable input, logic low turns on power switch IN1-OUT2 EN3 7 – I Enable input, logic low turns on power switch IN2-OUT3 EN1 – 3 I Enable input, logic high turns on power switch IN1-OUT1 EN2 – 4 I Enable input, logic high turns on power switch IN1-OUT2 EN3 – 7 I Enable input, logic high turns on power switch IN2-OUT3 GND 1, 5 1, 5 Ground IN1 2 2 I Input voltage for OUT1 and OUT2 IN2 6 6 I Input voltage for OUT3 NC 8, 9, 10 8, 9, 10 No connection OC1 16 16 O Overcurrent, open-drain output, active low, IN1-OUT1 OC2 13 13 O Overcurrent, open-drain output, active low, IN1-OUT2 OC3 12 12 O Overcurrent, open-drain output, active low, IN2-OUT3 OUT1 15 15 O Power-switch output, IN1-OUT1 OUT2 14 14 O Power-switch output, IN1-OUT2 OUT3 11 11 O Power-switch output, IN2-OUT3

I/O DESCRIPTION

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

Thermal

Sense

Driver

Current

Limit

UVLO

Driver

Current

Limit

Thermal

Sense

GND

EN1

IN1

EN2

OC1

OUT1

OUT2

OC2

Deglitch

Driver

Current

Limit

Thermal

Sense

Charge

Pump

GND

IN2

EN3

OUT3

OC3

Deglitch

VCC

Selector

UVLO

(See Note A)

Note A: Current sense Note B: Active low (ENx

) for TPS2063; Active high (ENx) for TPS2067

(See Note A)

(See Note B)

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

www.ti.com

Functional Block Diagram

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

OUT

90%

10%

50%

90%

10%

O(OUT)

I(EN)

O(OUT)

VOLTAGE WAVEFORMS

TEST CIRCUIT

off

50%

90%

10%

I(EN)

O(OUT)

off

I(EN)

5 V/div

O(OUT)

2 V/div

RL = 5 W, CL = 1 mF TA = 255C

t − Time − 500 ms/div

I(EN)

5 V/div

O(OUT)

2 V/div

RL = 5 W, CL = 1 mF TA = 255C

t − Time − 500 ms/div

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Circuit and Voltage Waveforms

Figure 2. Turnon Delay and Rise Time With 1-μF Figure 3. Turnoff Delay and Fall Time With 1-μF

Load Load

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

I(EN)

5 V/div

O(OUT)

2 V/div

RL = 5 W, CL = 100 mF TA = 255C

t − Time − 500 ms/div

O(OUT)

2 V/div

I(EN)

5 V/div

RL = 5 W, CL = 100 mF TA = 255C

t − Time − 500 ms/div

I(EN)

5 V/div

O(OUT)

500 mA/div

t − Time − 500 ms/div

I(EN)

5 V/div

O(OUT)

500 mA/div

470 mF

100 mF

220 mF

VIN = 5 V RL = 5 W, TA = 255C

t − Time − 1 ms/div

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 4. Turnon Delay and Rise Time With 100-μF Figure 5. Turnoff Delay and Fall Time With 100-μF

Load Load

www.ti.com

Figure 6. Short-Circuit Current, Figure 7. Inrush Current With Different

Device Enabled Into Short Load Capacitance

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

O(OC

)

2 V/div

O(OUT)

1 A/div

t − Time − 2 ms/div

O(OC

)

2 V/div

O(OUT)

1 A/div

t − Time − 2 ms/div

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

2 3 4 5 6

Turnon Time − ms

VI − Input Voltage − V

CL = 100 mF, RL = 5 W, TA = 255C

1.5

1.6

1.7

1.8

1.9

2 3 4 5 6

CL = 100 mF, RL = 5 W, TA = 255C

Turnoff Time − mS

VI − Input Voltage − V

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

www.ti.com

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 8. 2-Ω Load Connected to Enabled Device Figure 9. 1-Ω Load Connected to Enabled Device

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS

TURNON TIME TURNOFF TIME

vs vs

INPUT VOLTAGE INPUT VOLTAGE

Figure 10. Figure 11.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

0.1

0.2

0.3

0.4

0.5

0.6

2 3 4 5 6

Rise Time − ms

VI − Input Voltage − V

CL = 1 mF, RL = 5 W, TA = 255C

0.05

0.1

0.15

0.2

0.25

2 3 4 5 6

CL = 1 mF, RL = 5 W, TA = 255C

Fall Time − ms

VI − Input Voltage − V

−50 0 50 100 150

VI = 5.5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Enabled −

I (IN)

Aµ

VI = 5 V

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Enabled −

I (IN)

Aµ

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS (continued)

RISE TIME FALL TIME

vs vs

INPUT VOLTAGE INPUT VOLTAGE

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Figure 12. Figure 13.

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLED

TPS2061, TPS2065 TPS2062, TPS2066

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 14. Figure 15.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Enabled −

I (IN)

Aµ

TJ − Junction Temperature − 5C

− Supply Current, Output Disabled −I I (IN)

Aµ

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

−50 0 50 100 150

VI = 2.7 V

VI = 3.3 V

VI = 5.5 V

VI = 5 V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Disabled −

I (IN)

Aµ

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Disabled −

I (IN)

Aµ

VI = 3.3 V

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS (continued)

TPS2063, TPS2067 TPS2061, TPS2065

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLED

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 16. Figure 17.

SUPPLY CURRENT, OUTPUT DISABLED SUPPLY CURRENT, OUTPUT DISABLED

TPS2062, TPS2066 TPS2063, TPS2067

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 18. Figure 19.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

1.34

1.36

1.38

1.4

1.42

1.44

1.48

1.5

1.52

1.54

1.56

−50

0 50 100 150

1.46

VI = 3.3 V

VI = 5 V

VI = 3.3 V

VI = 5.5 V

TJ − Junction Temperature − 5C

− Short-Circuit Output Current − A I

VI = 2.7 V

100

120

−50 0 50 100 150

Out1 = 5 V

Out1 = 3.3 V

Out1 = 2.7 V

IO = 0.5 A

TJ − Junction Temperature − 5C

DS(on) − Static Drain-Source

On-State Resistance − mΩ

2.1

2.14

2.18

2.22

2.26

2.3

−50 0 50 100 150

UVLO Rising

UVLO Falling

UVOL − Undervoltage Lockout − V

TJ − Junction Temperature − 5C

1.5

1.7

1.9

2.1

2.3

2.5

2.5 3 3.5 4 4.5 5 5.5 6

TA = 255C Load Ramp = 1A/10 ms

Threshold Trip Current − A

VI − Input Voltage − V

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS (continued)

STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

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Figure 20. Figure 21.

THRESHOLD TRIP CURRENT UNDERVOLTAGE LOCKOUT

vs vs

INPUT VOLTAGE JUNCTION TEMPERATURE

Figure 22. Figure 23.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

100

150

200

0 2.5 5 7.5 10 12.5

Current-Limit Response − sµ

Peak Current − A

VI = 5 V , TA = 255C

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

TYPICAL CHARACTERISTICS (continued)

CURRENT-LIMIT RESPONSE

PEAK CURRENT

Figure 24.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

OC1 EN1 OC2

0.1 µF 22 µF

Load

OUT1

OUT2

Power Supply

2.7 V to 5.5 V

EN2

GND

0.1 µF

TPS2062

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

APPLICATION INFORMATION

POWER-SUPPLY CONSIDERATIONS

Figure 25. Typical Application

A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.

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OVERCURRENT

A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before V

has been applied (see Figure 15). The TPS206x senses the short and

I(IN)

immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload

occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 18). The TPS206x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

OC RESPONSE

The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

GND IN EN1

EN2

OC1

OC2

OUT1 OUT2

TPS2062

pullup

V+

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

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Figure 26. Typical Circuit for the OC Pin

POWER DISSIPATION AND JUNCTION TEMPERATURE

The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the r N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r dissipation per switch can be calculated by:

• PD= r

DS(on)

× I

Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs.

The thermal resistance, R

= 1 / (DERATING FACTOR), where DERATING FACTOR is obtained from the

θJA

Dissipation Ratings Table. Thermal resistance is a strong function of the printed circuit board construction , and the copper trace area connecting the integrated circuit.

Finally, calculate the junction temperature:

• TJ= PDx R

θJA

+ T

Where:

• TA= Ambient temperature °C

• R

= Thermal resistance

θJA

• PD= Total power dissipation based on number of switches being used. Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,

repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer.

DS(on)

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

of the

DS(on)

from Figure 20. Using this value, the power

THERMAL PROTECTION

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises above a minimum of 135°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots.

UNIVERSAL SERIAL BUS (USB) APPLICATIONS

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements:

• Hosts/self-powered hubs (SPH)

• Bus-powered hubs (BPH)

• Low-power, bus-powered functions

• High-power, bus-powered functions

• Self-powered functions SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability

than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream ports or functions.

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HOST/SELF-POWERED AND BUS-POWERED HUBS

Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see

Figure 27). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream

connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

OC1 EN1 OC2 EN2

GND

0.1 µF

8 3

5 4

33 µF

GND

OUT1

TPS2062

Power Supply

D+ D−

BUS

GND

D+ D−

BUS

Downstream

USB Ports

USB

Controller

3.3 V

5 V

33 µF

GND

OUT2

D+ D−

BUS

33 µF

GND

D+ D−

BUS

0.1 µF

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TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Figure 27. Typical Four-Port USB Host / Self-Powered Hub

BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 μF at power up, the device must implement inrush current limiting (see Figure 28). With TPS206x, the internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving circuits.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

OC1

OC2

8 3

0.1 µF 10 µF

Internal

Function

OUT1

Power Supply

3.3 V

EN1

0.1 µF 10 µF

OUT2

Internal

Function

0.1 µF

10 µF

USB

Control

GND

BUS

D−

D+

TPS2062

EN2

GND

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Figure 28. High-Power Bus-Powered Function

USB POWER-DISTRIBUTION REQUIREMENTS

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.

• Hosts/SPHs must: – Current-limit downstream ports – Report overcurrent conditions on USB V

• BPHs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 μF)

• Functions must: – Limit inrush currents – Power up at <100 mA

The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 29).

BUS

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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

DP1

DM1

DP2

DM2

DP3

DM3

DP4

PWRON1

OVRCUR1

PWRON2

OVRCUR2

DM4

DP0 DM0

XTAL1

XTAL2

OCSOFF

SN75240

D + D −

5 V

GND

D + D −

5 V

D + D −

5 V

D + D −

5 V

48-MHz

Crystal

Downstream

Ports

TUSB2040

Hub Controller

Tuning Circuit

ABC

33 µF

†

SN75240

ABC

GND

33 µF

†

33 µF

†

33 µF

†

D + D −

Upstream Port

TPS2041B

SN75240

5 V

GND

C D

1 µF

GND

Ferrite Beads

BUSPWR GANGED

Tie to TPS2041 EN

Input

OC EN

OUT

5-V Power

Supply

GND

3.3 V

4.7 µF

0.1 µF

4.7 µF

EN1

OC1

OUT1

TPS2062

EN2 OC2

OUT2

0.1 µF

GND

†

USB rev 1.1 requires 120 µF per hub.

TPS76333

www.ti.com

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

GENERIC HOT-PLUG APPLICATIONS

Figure 29. Hybrid Self / Bus-Powered Hub Implementation

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206x also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

Power

Supply

0.1 µF

1000 µF Optimum

2.7 V to 5.5 V

PC Board

Overcurrent Response

TPS2062

OC1

GND

EN1

EN2

OUT1

OUT2

OC2

Block of Circuitry

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Figure 30. Typical Hot-Plug Implementation

By placing the TPS206x between the VCCinput and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device.

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DETAILED DESCRIPTION

Power Switch

The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 1 A.

Charge Pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current.

Driver

The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage.

Enable (ENx or ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 μA when a logic high is present on ENx, or when a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels.

Overcurrent (OCx)

The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OCx is asserted instantaneously.

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

www.ti.com

Current Sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load.

Thermal Sense

The TPS206x implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

Undervoltage Lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch.

spacer

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

REVISION HISTORY

Changes from Original (December 2003) to Revision A Page

• Added devices to the data sheet- TPS2063, TPS2065, TPS2066, TPS2067 ...................................................................... 1

• Added the General Switch Catalog ....................................................................................................................................... 1

Changes from Revision A (July 2004) to Revision B Page

• Changed Features Bullet From: UL Pending To: UL Listed - File No. E169910 .................................................................. 1

• Changed Electrical Characteristics - CURRENT LIMIT information. .................................................................................... 4

Changes from Revision C (January 2006) to Revision D Page

• Changed ORDERING INFORMATION table ........................................................................................................................ 2

Changes from Revision D (Februaty 2007) to Revision E Page

• Changed General Switch Catalog information. ..................................................................................................................... 1

Changes from Revision E (September 2007) to Revision F Page

• Added the DBV-5 package. .................................................................................................................................................. 1

• Added the DBV-5 package option. ....................................................................................................................................... 1

• Added the DBV-5 package option to the Dissipation Ratings table. .................................................................................... 3

• Changed Thermal Sense paragraph: From: Once the die temperature rises to approximately 140°C To: Once the

die temperature rises above a minimum of 135°C ............................................................................................................. 17

Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

TPS2061, TPS2062, TPS2063 TPS2065, TPS2066, TPS2067

SLVS490I –DECEMBER 2003–REVISED OCTOBER 2009

Changes from Revision F (April 2008) to Revision G Page

• Changed DBV-5 to Product Preview. ................................................................................................................................... 1

Changes from Revision G (July 2008) to Revision H Page

• Deleted Product Preview from the DBV package ................................................................................................................. 1

• Changed TPS2061DBV status From Preview to Active ....................................................................................................... 2

• Changed TPS2065DBV status From Preview to Active ....................................................................................................... 2

Changes from Revision H (December 2008) to Revision I Page

• Changed the ESD statement ................................................................................................................................................ 2

• Deleted temp range of 0°C to 70°C from the Available Option table. .................................................................................. 2

• Added Note to the Available Options table - The printed circuit board layout is important for control of temperature

rise when operated at high ambient temperatures ............................................................................................................... 2

• Deleted temp range of 0°C to 70°C from the Ordering Information table. ............................................................................ 2

• Added Note to the Ordering Information table - The printed circuit board layout is important for control of

temperature rise when operated at high ambient temperatures ........................................................................................... 2

• Changed the Abs Max Ratings table - Operating virtual junction temperature range From: -40°C to 125°C To: -40°C

to 150°C ................................................................................................................................................................................ 3

• Deleted Storage temperature range, T

from the Abs Max Ratings table .......................................................................... 3

stg

• Deleted MIL-STD-883C reference from ESD in the Abs Max table ..................................................................................... 3

• Added 3 table notes to the Dissipation Ratings table. .......................................................................................................... 3

• Added Addition values for the DBV-5 option in the Dissipation Ratings table. .................................................................... 3

• Deleted Note - Not tested in production, specified by design from r

in the Electrical Characteristics table. ................ 3

DS(on)

• Deleted Note - Not tested in production, specified by design from trin the Electrical Characteristics table. ....................... 3

• Deleted Note - Not tested in production, specified by design from tfin the Electrical Characteristics table. ....................... 3

• Added text to the POWER DISSIPATION section - The thermal resistance, R

............................................................. 17

θJA

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Product Folder Link(s): TPS2061 TPS2062 TPS2063 TPS2065 TPS2066 TPS2067

PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

(1)

TPS2061D ACTIVE SOIC D 8 75 Green (RoHS

TPS2061DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS

TPS2061DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS

TPS2061DG4 ACTIVE SOIC D 8 75 Green (RoHS

TPS2061DGN ACTIVE MSOP-

TPS2061DGNG4 ACTIVE MSOP-

TPS2061DGNR ACTIVE MSOP-

TPS2061DGNRG4 ACTIVE MSOP-

TPS2061DR ACTIVE SOIC D 8 2500 Green (RoHS

TPS2061DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TPS2062D ACTIVE SOIC D 8 75 Green (RoHS

TPS2062DG4 ACTIVE SOIC D 8 75 Green (RoHS

TPS2062DGN ACTIVE MSOP-

TPS2062DGNG4 ACTIVE MSOP-

TPS2062DGNR ACTIVE MSOP-

TPS2062DGNRG4 ACTIVE MSOP-

TPS2062DR ACTIVE SOIC D 8 2500 Green (RoHS

Package Type Package

Drawing

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAU Level-1-260C-UNLIM 0 to 70 2061

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2061

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2062

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2062

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2062

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2062

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2062

18-Oct-2013

Samples

(4/5)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

TPS2062DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TPS2063D ACTIVE SOIC D 16 40 Green (RoHS

TPS2063DG4 ACTIVE SOIC D 16 40 Green (RoHS

TPS2063DR ACTIVE SOIC D 16 2500 Green (RoHS

TPS2063DRG4 ACTIVE SOIC D 16 2500 Green (RoHS

TPS2065D ACTIVE SOIC D 8 75 Green (RoHS

TPS2065DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS

TPS2065DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS

TPS2065DG4 ACTIVE SOIC D 8 75 Green (RoHS

TPS2065DGN ACTIVE MSOP-

TPS2065DGNG4 ACTIVE MSOP-

TPS2065DGNR ACTIVE MSOP-

TPS2065DGNRG4 ACTIVE MSOP-

TPS2065DR ACTIVE SOIC D 8 2500 Green (RoHS

TPS2065DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TPS2066D ACTIVE SOIC D 8 75 Green (RoHS

TPS2066DG4 ACTIVE SOIC D 8 75 Green (RoHS

TPS2066DGN ACTIVE MSOP-

Package Type Package

Drawing

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2062

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2063

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2065

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2065

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2065

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2065

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2065

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2066

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2066

CU NIPDAUAG

18-Oct-2013

Samples

(4/5)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

TPS2066DGNG4 ACTIVE MSOP-

TPS2066DGNR ACTIVE MSOP-

TPS2066DGNRG4 ACTIVE MSOP-

TPS2066DR ACTIVE SOIC D 8 2500 Green (RoHS

Package Type Package

Drawing

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2066

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2066

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2066

18-Oct-2013

(4/5)

& no Sb/Br)

TPS2066DRG4 ACTIVE SOIC D 8 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2066

& no Sb/Br)

TPS2066ID PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 85

TPS2066IDR PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 85

TPS2067D ACTIVE SOIC D 16 40 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2067

& no Sb/Br)

TPS2067DG4 ACTIVE SOIC D 16 40 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2067

& no Sb/Br)

TPS2067DR ACTIVE SOIC D 16 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2067

& no Sb/Br)

TPS2067DRG4 ACTIVE SOIC D 16 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2067

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Samples

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

18-Oct-2013

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS2062, TPS2065, TPS2066 :

Automotive: TPS2062-Q1, TPS2065-Q1, TPS2066-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS2061DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS2061DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS2061DGNR MSOP-

Power

TPS2061DGNR MSOP-

Power

TPS2061DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TPS2062DGNR MSOP-

Power

TPS2062DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TPS2063DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2065DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS2065DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS2065DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS2065DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS2065DGNR MSOP-

Power

Type

PAD

Package Drawing

DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2013

Device Package

TPS2065DGNR MSOP-

Power

TPS2065DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2066DGNR MSOP-

Power

TPS2066DGNR MSOP-

Power

TPS2066DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TPS2067DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Type

PAD

Package Drawing

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Quadrant

Pin1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2061DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0

TPS2061DBVT SOT-23 DBV 5 250 203.0 203.0 35.0 TPS2061DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2061DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0

TPS2061DR SOIC D 8 2500 340.5 338.1 20.6

TPS2062DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2013

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2062DR SOIC D 8 2500 340.5 338.1 20.6

TPS2063DR SOIC D 16 2500 367.0 367.0 38.0 TPS2065DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS2065DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 TPS2065DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS2065DBVT SOT-23 DBV 5 250 203.0 203.0 35.0

TPS2065DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2065DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0

TPS2065DR SOIC D 8 2500 340.5 338.1 20.6

TPS2066DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0 TPS2066DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0

TPS2066DR SOIC D 8 2500 340.5 338.1 20.6

TPS2067DR SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 3

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments TPS2061D, TPS2061DBV, TPS2061DGN, TPS2062D, TPS2062DGN Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

DESCRIPTION (CONTINUED)

ABSOLUTE MAXIMUM RATINGS

DISSIPATING RATING TABLE

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

POWER-SUPPLY CONSIDERATIONS

OVERCURRENT

OC RESPONSE

POWER DISSIPATION AND JUNCTION TEMPERATURE

THERMAL PROTECTION

UNDERVOLTAGE LOCKOUT (UVLO)

UNIVERSAL SERIAL BUS (USB) APPLICATIONS

HOST/SELF-POWERED AND BUS-POWERED HUBS

LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS

USB POWER-DISTRIBUTION REQUIREMENTS

GENERIC HOT-PLUG APPLICATIONS

DETAILED DESCRIPTION

Power Switch

Charge Pump

Driver

Enable (ENx or ENx)

Overcurrent (OCx)

Current Sense

Thermal Sense

Undervoltage Lockout

REVISION HISTORY