Datasheet TPS2010APWP, TPS2010APWPR, TPS2010ADR, TPS2010AD, TPS2013ADR Datasheet (Texas Instruments)
...
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
33-mΩ (5-V Input) High-Side MOSFET
Switch
D
Short-Circuit and Thermal Protection
D
Operating Range . . . 2.7 V to 5.5 V
D
Logic-Level Enable Input
D
Typical Rise Time . . . 6.1 ms
D
Undervoltage Lockout
D
Maximum Standby Supply
Current ...10 µA
D
No Drain-Source Back-Gate Diode
D
Available in 8-pin SOIC and 14-Pin TSSOP
Packages
D
Ambient Temperature Range, –40°C to 85°C
D
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
description
The TPS201xA family of power distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS201xA limits the output
current to a safe level by switching into a constant-current mode. When continuous heavy overloads and short
circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal
protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once
the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is
present.
The TPS201xA devices differ only in short-circuit current threshold. The TPS2010A limits at 0.3-A load, the
TPS201 1 at 0.9-A load, the TPS2012A at 1.5-A load, and the TPS2013A at 2.2-A load (see Available Options).
The TPS201xA is available in an 8-pin small-outline integrated-circuit (SOIC) package and in a 14-pin
thin-shrink small-outline package (TSSOP) and operates over a junction temperature range of –40°C to 125°C.
TPS201xA
TPS202x
TPS203x
33 mΩ, single
0.2 A – 2 A
0.2 A – 2 A
0.2 A – 2 A
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mΩ, single
600 mA
1 A
500 mA
500 mA
250 mA
250 mA
GENERAL SWITCH CATALOG
TPS2042
TPS2052
TPS2046
TPS2056
80 mΩ, dual
500 mA
500 mA
250 mA
250 mA
TPS2100/1
260 mΩ
IN1 500 mA
IN2 10 mA
OUT
IN1
IN2
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 Ω
TPS2043
TPS2053
TPS2047
TPS2057
80 mΩ, triple
500 mA
500 mA
250 mA
250 mA
TPS2044
TPS2054
TPS2048
TPS2058
80 mΩ, quad
500 mA
500 mA
250 mA
250 mA
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OUT
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
IN
IN
IN
IN
IN
EN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PWP PACKAGE
(TOP VIEW)
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
RECOMMENDED
TYPICAL SHORT-CIRCUIT
PACKAGED DEVICES
T
A
ENABLE
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
CURRENT LIMIT AT 25°C
(A)
SMALL OUTLINE
(D)
†
TSSOP
(PWP)
‡
0.2 0.3 TPS2010AD TPS2010APWPR
°
°
0.6 0.9 TPS2011AD TPS2011APWPR
–
40°C to 85°C
Active lo
w
1 1.5 TPS2012AD TPS2012APWPR
1.5 2.2 TPS2013AD TPS2013APWPR
†
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR)
‡
The PWP package is only available left-end taped-and-reeled.
TPS201xA functional block diagram
OUTIN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†
Current Sense
Terminal Functions
TERMINAL
NAME
NO.
D
NO.
PWP
I/O DESCRIPTION
EN 4 7 I Enable input. Logic low turns on power switch.
GND 1 1 I Ground
IN 2, 3 2–6 I Input voltage
OUT 5, 6, 7, 8 8–14 O Power-switch output
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (V
I(IN)
= 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
enable (EN
)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on EN . A logic zero input on EN restores bias
to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Input voltage range, V
I(IN)
(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O(OUT)
(see Note 1) –0.3 V to V
I(IN)
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I(EN)
–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O(OUT)
internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine model 200V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
PWP 700 mW 5.6 mW/°C 448 mW 364 mW
recommended operating conditions
MIN MAX UNIT
p
V
I(IN)
2.7 5.5 V
Input voltage
V
I(EN)
0 5.5 V
TPS2010A 0 0.2
p
TPS2011A 0 0.6
Continuous output current, I
O
TPS2012A 0 1
A
TPS2013A 0 1.5
Operating virtual junction temperature, T
J
–40 125 °C
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, EN = 0 V (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX UNIT
V
I(IN)
= 5 V, TJ = 25°C, IO = 1.5 A 33 36
V
I(IN)
= 5 V, TJ = 85°C, IO = 1.5 A 38 46
V
I(IN)
= 5 V, TJ = 125°C, IO = 1.5 A 44 50
V
I(IN)
= 3.3 V, TJ = 25°C, IO = 1.5 A 37 41
V
I(IN)
= 3.3 V, TJ = 85°C, IO = 1.5 A 43 52
V
I(IN)
= 3.3 V, TJ = 125°C, IO = 1.5 A 51 61
r
DS(on)
Static drain-source on-state resistance
V
I(IN)
= 5 V, TJ = 25°C, IO = 0.18 A 30 34
mΩ
V
I(IN)
= 5 V, TJ = 85°C, IO = 0.18 A 35 41
V
I(IN)
= 5 V, TJ = 125°C, IO = 0.18 A 39 47
V
I(IN)
= 3.3 V, TJ = 25°C, IO = 0.18 A 33 37
V
I(IN)
= 3.3 V, TJ = 85°C, IO = 0.18 A 39 46
V
I(IN)
= 3.3 V, TJ = 125°C, IO = 0.18 A 44 56
p
V
I(IN)
= 5.5 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
6.1
trRise time, output
V
I(IN)
= 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
8.6
ms
p
V
I(IN)
= 5.5 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
3.4
tfFall time, output
V
I(IN)
= 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL = 10 Ω
3
ms
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input (EN)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
V
IH
High-level input voltage 2.7 V ≤ V
I(IN)
≤ 5.5 V 2 V
p
4.5 V ≤ V
I(IN)
≤ 5.5 V 0.8
VILLow-level in ut voltage
2.7 V ≤ V
I(IN)
≤ 4.5 V 0.5
V
I
I
Input current EN = 0 V or EN = V
I(IN)
–0.5 0.5 µA
t
on
Turnon time CL = 100 µF, RL = 10 Ω 20
t
off
Turnoff time CL = 100 µF, RL = 10 Ω 40
ms
current limit
PARAMETER
TEST CONDITIONS
†
MIN TYP MAX UNIT
TPS2010A 0.22 0.3 0.4
p
TJ = 25°C, VI = 5.5 V,
TPS2011A 0.66 0.9 1.1
IOSShort-circuit output current
OUT
connected to
GND
,
D
evice enable
into short circuit
TPS2012A 1.1 1.5 1.8
A
Device enable into short circuit
TPS2013A 1.65 2.2 2.7
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, EN = 0 V (unless otherwise noted) (continued)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
pp
p
TJ = 25°C 0.3 1
Supply current, low-level output
No Load on OUT
EN = V
I(IN)
–40°C ≤ TJ ≤ 125°C 10
µ
A
pp
p
TJ = 25°C 58 75
Supply current, high-level output
No Load on OUT
EN
= 0
V
–40°C ≤ TJ ≤ 125°C 75 100
µ
A
Leakage current OUT connected to ground EN = V
I(IN)
–40°C ≤ TJ ≤ 125°C 10 µA
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-level input voltage 2 2.5 V
Hysteresis TJ = 25°C 100 mV
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
t
r
t
f
90%
90%
10%
10%
50%
50%
90%
10%
V
O(OUT)
V
I(EN)
V
O(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
t
on
t
off
Figure 1. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Turnon Delay and Rise TIme 2
Turnoff Delay and Fall Time 3
Turnon Delay and Rise TIme with 1-µF Load 4
Turnoff Delay and Rise TIme with 1-µF Load 5
Device Enabled into Short 6
TPS2010A, TPS201 1A, TPS2012A, and TPS2013A, Ramped Load on Enabled Device 7, 8, 9, 10
TPS2013A, Inrush Current 11
7.9-Ω Load Connected to an Enabled TPS2010A Device 12
3.7-Ω Load Connected to an Enabled TPS2010A Device 13
3.7-Ω Load Connected to an Enabled TPS2011A Device 14
2.6-Ω Load Connected to an Enabled TPS2011A Device 15
2.6-Ω Load Connected to an Enabled TPS2012A Device 16
1.2-Ω Load Connected to an Enabled TPS2012A Device 17
1.2-Ω Load Connected to an Enabled TPS2013A Device 18
0.9-Ω Load Connected to an Enabled TPS2013A Device 19
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 2. Turnon Delay and Rise Time
2
468101214161820
t – Time – ms
0
VIN = 5 V
RL = 27 Ω
TA = 25°C
V
O(OUT)
(2 V/div)
V
I(EN)
V
O(OUT)
V
I(EN)
(5 V/div)
Figure 3. Turnoff Delay and Fall Time
2 4 6 8 10 12 14 16 18 20
t – Time – ms
V
I(EN)
(5 V/div)
0
V
I(IN)
= 5 V
RL = 27 Ω
TA = 25°C
V
O(OUT)
(2 V/div)
V
I(EN)
V
O(OUT)
Figure 4. Turnon Delay and Rise Time
With 1-µF Load
2
4 6 81012141618 20
t – Time – ms
V
I(EN)
(5 V/div)
0
V
I(IN)
= 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
V
O(OUT)
(2 V/div)
V
I(EN)
O(OUT)
Figure 5. Turnoff Delay and Fall Time
With 1-µF Load
2
468101214161820
t – Time – ms
V
I(EN)
(5 V/div)
0
V
I(IN)
= 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
V
O(OUT)
(2 V/div)
V
I(EN)
V
O(OUT)
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 6. Device Enabled Into Short
1
2345678910
t – Time – ms
V
I(EN)
(5 V/div)
0
I
O(OUT)
(1 A/div)
V
I(EN)
I
O(OUT)
V
I(IN)
= 5 V
TA = 25°C
TPS2013A
TPS2012A
TPS2011A
TPS2010A
Figure 7. TPS2010A, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
I
O(OUT)
(500 mA/div)
I
O(OUT)
V
I(IN)
= 5 V
TA = 25°C
Figure 8. TPS2011A, Ramped Load on Enabled
Device
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
TA = 25°C
Figure 9. TPS2012A, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
TA = 25°C
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 10. TPS2013A, Ramped Load on
Enabled Device
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
I
O(OUT)
(1 A/div)
O(OUT)
V
I(IN)
= 5 V
TA = 25°C
Figure 11. TPS2013A, Inrush Current
123 4567 8910
t – Time – ms
0
I
I(IN)
(500 mA/div)
V
I(EN)
I
I(IN)
RL = 10 Ω
TA = 25°C
V
I(EN)
(5 V/div)
470 µF
47 µF
150 µF
Figure 12. 7.9-Ω Load Connected to an Enabled
TPS2010A Device
200 400 600 800 1000 12001400 1600 1800 2000
t – Time – µs
0
I
O(OUT)
(200 mA/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 7.9 Ω
TA = 25°C
Figure 13. 3.7-Ω Load Connected to an Enabled
TPS2010A Device
50 100 150 200 250 300 350 400 450 500
t – Time – µs
0
I
O(OUT)
(500 mA/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 3.7 Ω
TA = 25°C
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 14. 3.7-Ω Load Connected to an Enabled
TPS2011A Device
200 400 600 800 1000 1200 1400 1600 1800 2000
t – Time – µs
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 3.7 Ω
TA = 25°C
Figure 15. 2.6-Ω Load Connected to an Enabled
TPS2011A Device
50 100 150 200 250 300 350 400 450 500
t – Time – µs
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 2.6 Ω
TA = 25°C
Figure 16. 2.6-Ω Load Connected to an Enabled
TPS2012A Device
200 400 600 800 1000 12001400 1600 1800 2000
t – Time – µs
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 2.6 Ω
TA = 25°C
Figure 17. 1.2-Ω Load Connected to an Enabled
TPS2012A Device
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
0
I
O(OUT)
(1 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 1.2 Ω
TA = 25°C
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 18. 1.2-Ω Load Connected to an Enabled
TPS2013A Device
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
0
I
O(OUT)
(2 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 1.2 Ω
TA = 25°C
Figure 19. 0.9-Ω Load Connected to an Enabled
TPS2013A Device
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
0
I
O(OUT)
(2 A/div)
I
O(OUT)
V
I(IN)
= 5 V
RL = 0.9 Ω
TA = 25°C
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
t
d(on)
Turnon delay time vs Output voltage 20
t
d(off)
Turnoff delay time vs Input voltage 21
t
r
Rise time vs Load current 22
t
f
Fall time vs Load current 23
Supply current (enabled) vs Junction temperature 24
Supply current (disabled) vs Junction temperature 25
Supply current (enabled) vs Input voltage 26
Supply current (disabled) vs Input voltage 27
vs Input voltage 28
IOSShort-circuit current limit
vs Junction temperature 29
vs Input voltage 30
vs Junction temperature 31
r
DS(on)
Static drain-source on-state resistance
vs Input voltage 32
vs Junction temperature 33
V
I
Input voltage Undervoltage lockout 34
Figure 20
4.5
4
3.5
2.5 3 3.5 4 4.5
– Turn-on Delay T ime – ms
5
5.5
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
7.5
5 5.5 6
VI – Input Voltage – V
t
d(on)
6
6.5
7
TA = 25°C
CL = 1 µF
Figure 21
17
16.5
16
2.5 3 3.5 4 4.5
17.5
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
18
5 5.5 6
VI – Input Voltage – V
– Turn-off Delay T ime – ms
t
d(off)
TA = 25°C
CL = 1 µF
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
5.5
5
0 0.5 1
– Rise Time – ms
6
RISE TIME
vs
LOAD CURRENT
6.5
1.5 2
IL – Load Current – A
t
r
TA = 25°C
CL = 1 µF
Figure 23
3.25
2.75
2.5
0 0.5
– Fall Time – ms
3.5
FALL TIME
vs
LOAD CURRENT
1 1.5 2
3
IL – Load Current – A
t
f
TA = 25°C
CL = 1 µF
Figure 24
55
45
35
–50 –25 0 25 50
65
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
75
75 100 150
TJ – Junction Temperature – °C
Supply Current (Enabled) – Aµ
125
V
I(IN)
= 3.3 V
V
I(IN)
= 4 V
V
I(IN)
= 5 V
V
I(IN)
= 5.5 V
V
I(IN)
= 2.7 V
Figure 25
1
0
–1
–50 –25 0 25 50
4
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
5
75 100 150
TJ – Junction Temperature – °C
Supply Current (Disabled) – Aµ
125
3
2
V
I(IN)
= 4 V
V
I(IN)
= 2.7 V
V
I(IN)
= 5 V
V
I(IN)
= 5.5 V
V
I(IN)
= 3.3 V
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 26
55
45
35
2.5 3 3.5 4 4.5
65
SUPPLY CURRENT (ENABLED)
vs
INPUT VOLTAGE
75
5 5.5 6
VI – Input Voltage – V
Supply Current (Enabled) – Aµ
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = –40°C
Figure 27
1
0
–1
2.5 3 3.5 4 4.5
4
SUPPLY CURRENT (DISABLED)
vs
INPUT VOLTAGE
5
5 5.5 6
VI – Input Voltage – V
Supply Current (Disabled) – Aµ
3
2
TJ = 85°C
TJ = 0°C
TJ = –40°C
TJ = 125°C
TJ = 25°C
SHORT-CIRCUIT CURRENT LIMIT
vs
INPUT VOLTAGE
Figure 28
1.5
0.5
0
23 4
2.5
3.5
56
VI – Input Voltage – V
– Short-Circuit Current Limit – A
I
OS
1
2
3
TPS2013A
TPS2012A
TPS2011A
TPS2010A
TA = 25°C
Figure 29
SHORT-CIRCUIT CURRENT LIMIT
vs
JUNCTION TEMPERATURE
1.5
0.5
0
–50 –25 0
2.5
3.5
25 100
TJ – Junction Temperature – °C
– Short-Circuit Current Limit – A
I
OS
1
2
3
TPS2013A
TPS2012A
TPS2011A
TPS2010A
50 75
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 30
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
20
2.5 3 3.5
40
60
46
VI – Input Voltage – V
30
50
4.5 5
Ω
r
DS(on)
– Static Drain-Source On-State Resistance – m
5.5
TJ = 25°C
TJ = 125°C
TJ = –40°C
IO = 0.18 A
Figure 31
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
20
–50 –25 0
40
60
25 150
TJ – Junction Temperature – °C
30
50
VI = 2.7 V
50 75 100
125
VI = 3.3 V
VI = 5.5 V
IO = 0.18 A
Ω
r
DS(on)
– Static Drain-Source On-State Resistance – m
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
20
3 3.5
40
60
46
VI – Input Voltage – V
30
50
4.5 5 5.5
TJ = 25°C
TJ = 125°C
Figure 32
IO = 1.5 A
TJ = –40°C
Ω
r
DS(on)
– Static Drain-Source On-State Resistance – m
Figure 33
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
20
–50 –25 0
40
60
25 150
TJ – Junction Temperature – °C
30
50
VI = 3.3 V
50 75 100
125
VI = 4 V
VI = 5.5 V
IO = 1.5 A
Ω
r
DS(on)
– Static Drain-Source On-State Resistance – m
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 34
2
–50 0 50 100
2.4
UNDERVOLTAGE LOCKOUT
2.5
150
TJ – Temperature – °C
2.3
2.2
Start Threshold
Stop Threshold
2.1
V
I
– Input Voltage – V
APPLICATION INFORMATION
IN
EN
GND
0.1 µF
2,3
4
5,6,7,8
0.1 µF 22 µF
Load
1
OUT
TPS2013A
Power Supply
2.7 V to 5.5 V
Figure 35. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load
is heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FET s do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly . Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
overcurrent (continued)
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
I(IN)
has been applied (see Figure 6). The TPS201xA senses the short and
immediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 12–19).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7–10). The TPS201xA is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find r
DS(on)
at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read r
DS(on)
from Figures 30–33. Next, calculate the power dissipation using:
P
D
+
r
DS(on
)
I
2
Finally, calculate the junction temperature:
T
J
+
P
D
R
q
JA
)
T
A
Where:
TA = Ambient Temperature °C
R
θJA
= Thermal resistance SOIC = 172°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS201xA into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
generic hot-plug applications (see Figure 36)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS201xA series, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS201xA also ensures the switch will be off after the card has been removed, and the switch will be off
during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion
of the card or module.
Power
Supply
Block of
Circuitry
TPS2013A
GND
IN
IN
EN
OUT
OUT
OUT
OUT
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Figure 36. Typical Hot-Plug Implementation
By placing the TPS201xA between the VCC input and the rest of the circuitry, the input power will reach this
device first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES
SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE P ACKAGE
4073225/E 03/97
0,50
0,75
0,25
0,15 NOM
Thermal Pad
(See Note D)
Gage Plane
2824
7,70
7,90
20
6,40
6,60
9,60
9,80
6,60
6,20
11
0,19
4,50
4,30
10
0,15
20
A
1
0,30
1,20 MAX
1614
5,10
4,90
PINS **
4,90
5,10
DIM
A MIN
A MAX
0,05
Seating Plane
0,65
0,10
M
0,10
0°–8°
20-PIN SHOWN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
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