Texas Instruments TPS1120DR, TPS1120D Datasheet

TPS1120, TPS1120Y

DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low r

DS(on)

. . . 0.18 Ω at VGS = –10 V

D

3-V Compatible

D

Requires No External V

CC

D

TTL and CMOS Compatible Inputs

D

V

GS(th)

= –1.5 V Max

D

ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015

description

The TPS1120 incorporates two independent
p-channel enhancement-mode MOSFETs that
have been optimized, by means of the Texas
Instruments LinBiCMOS process, for 3-V or 5-V
power distribution in battery-powered systems. With a maximum V

GS(th)

of –1.5 V and an I

DSS

of only 0.5 µA,
the TPS1120 is the ideal high-side switch for low-voltage portable battery-management systems, where
maximizing battery life is a primary concern. Because portable equipment is potentially subject to electrostatic
discharge (ESD), the MOSFET s have built-in circuitry for 2-kV ESD protection. End equipment for the TPS1 120
includes notebook computers, personal digital assistants (PDAs), cellular telephones, bar-code scanners, and
PCMCIA cards. For existing designs, the TPS1 120D has a pinout common with other p-channel MOSFETs in
small-outline integrated circuit SOIC packages.

The TPS1120 is characterized for an operating junction temperature range, T

J

, from –40°C to 150°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

†

T

J

SMALL OUTLINE

(D)

CHIP FORM

(Y)

–40°C to 150°C TPS1120D TPS1120Y

†

The D package is available taped and reeled. Add an R suffix to device
type (e.g., TPS1120DR). The chip form is tested at 25°C.

Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.

LinBiCMS is a trademark of Texas Instruments Incorporated.

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

1SOURCE

1GATE

2SOURCE

2GATE

1DRAIN
1DRAIN
2DRAIN
2DRAIN

D PACKAGE

(TOP VIEW)

TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic

1GATE

1SOURCE

1DRAIN

†

ESD-

Protection

Circuitry

2GATE

2SOURCE

2DRAIN

†

ESD-

Protection

Circuitry

†

For all applications, both drain pins for each device should be connected.

TPS1120Y chip information

This chip, when properly assembled, displays characteristics similar to the TPS1 120C. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS

TPS1120Y

(2)

(6)

(1)

(3)

(7)

(8)

(5)(4)

1DRAIN1SOURCE

1GATE

2SOURCE

2GATE

1DRAIN
2DRAIN

2DRAIN

57

64

(2)

(1)

(3)

(4)

(6)

(7)

(8)

(5)

TPS1120, TPS1120Y

DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

UNIT

Drain-to-source voltage, V

DS

–15 V

Gate-to-source voltage, V

GS

2 or –15 V

TA = 25°C ±0.39

V

GS

= –2.7

V

TA = 125°C ±0.21
TA = 25°C ±0.5

°

V

GS

= –3

V

TA = 125°C ±0.25

Continuous drain current, each device (T

J

=

150°C), I

D

TA = 25°C ±0.74

A

V

GS

= –4.5

V

TA = 125°C ±0.34
TA = 25°C ±1.17

V

GS

= –10

V

TA = 125°C ±0.53

Pulse drain current, I

D

TA = 25°C ±7 A

Continuous source current (diode conduction), I

S

TA = 25°C –1 A
Continuous total power dissipation See Dissipation Rating Table
Storage temperature range, T

stg

–55 to 150 °C

Operating junction temperature range, T

J

–40 to 150 °C

Operating free-air temperature range, T

A

–40 to 125 °C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 125°C

POWER RATING

D 840 mW 6.71 mW/°C 538 mW 437 mW 169 mW

‡

Maximum values are calculated using a derating factor based on R

θJA

= 149°C/W for the package. These devices are

mounted on an FR4 board with no special thermal considerations.

TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at TJ = 25°C (unless otherwise noted)

static

TPS1120

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

V

GS(th)

Gate-to-source threshold voltage VDS = VGS, ID = –250 µA –1 –1.25 –1.50 V

V

SD

Source-to-drain voltage (diode forward voltage)

†

IS = –1 A, VGS = 0 V –0.9 V

I

GSS

Reverse gate current, drain short circuited to source VDS = 0 V, VGS = –12 V ±100 nA

V

= –12 V ,

TJ = 25°C –0.5

I

DSS

Zero-gate-voltage drain current

DS

,

VGS = 0 V

TJ = 125°C –10

µ

A

VGS = –10 V ID = –1.5 A 180
VGS = –4.5 V ID = –0.5 A 291 400

r

DS(on)

Static drain-t

o-source on-state resistance

†

VGS = –3 V

476 700

mΩ

VGS = –2.7 V

I

D

= –0.2

A

606 850

g

fs

Forward transconductance

†

VDS = –10 V , ID = –2 A 2.5 S

†

Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2%

static

TPS1120Y

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

V

GS(th)

Gate-to-source threshold voltage VDS = VGS, ID = –250 µA –1.25 V

V

SD

Source-to-drain voltage (diode forward voltage)

†

IS = –1 A, VGS = 0 V –0.9 V
VGS = –10 V ID = –1.5 A 180
VGS = –4.5 V ID = –0.5 A 291

r

DS(on)

Static drain-t

o-source on-state resistance

†

VGS = –3 V

476

mΩ

VGS = –2.7 V

I

D

= –0.2

A

606

g

fs

Forward transconductance

†

VDS = –10 V , ID = –2 A 2.5 S

†

Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2%

dynamic

TPS1120, TPS1120Y

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

Q

g

Total gate charge 5.45

Q

gs

Gate-to-source charge

VDS = –10 V , VGS = –10 V , ID = –1 A

0.87

nC

Q

gd

Gate-to-drain charge 1.4

t

d(on)

Turn-on delay time 4.5 ns

t

d(off)

Turn-off delay time

V

= –10 V , R

= 10 Ω,I

= –1 A,

13 ns

t

r

Rise time

DD

,

RG = 6 Ω,

L

,

See Figures 1 and 2

D

,

10

t

f

Fall time 2

ns

t

rr(SD)

Source-to-drain reverse recovery time IF = 5.3 A, di/dt = 100 A/µs 16