Texas Instruments TPL5010-Q1 Datasheet

VIN

POWER MANAGEMENT

VOUT

GND

µC

GPIO

VDD

GND

Rp

GPIO

RSTn

TPL5010-Q1

VDD

GND

RSTn

WAKE

DELAY/
M_RST

DONE

R

EXT

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TPL5010-Q1

SNAS679 –SEPTEMBER 2016

TPL5010-Q1 AEC-Q100 Nano-Power System Timer with Watchdog Function

1 Features

1

• Qualified for Automotive Applications

• AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C5

• Current Consumption of 35 nA (typ) at 2.5 V

• Supply Voltage from 1.8 V to 5.5 V

• Selectable Time Intervals 100 ms to 7200 s

• Timer Accuracy 1% (Typical)

• Resistor Selectable Time Interval

• Watchdog Functionality

• Manual Reset

• TPL5x10Q Family of AEC-Q100 Nano-Power
System Timers

• TPL5010-Q1 - Supply Current 35 nA
– Low Power Timer
– Watchdog Function
– Programmable Delay Range
– Manual Reset

• TPL5110-Q1 - Supply Current 35 nA
– Low Power Timer
– MOS-Driver
– Programmable Delay Range
– Manual Reset
– One-Shot Feature

2 Applications

• Electric Vehicles

• Always On Systems

• Battery powered systems

• Clutch Actuator circuit

• Car Door Handle circuit

• Smart Key

• Remote current sensor

• Intruder Detection

3 Description

The TPL5010-Q1 Nano Timer is a low power, AEC­Q100 qualified timer with a watchdog feature ideal for
system wake up in duty cycled or battery powered
applications. In such systems the microcontroller
timer can be used for system wake-up, but if the
timer sleep current is high, up to 60-80% of the total
system current can be consumed by the
microcontroller timer in this sleep mode. Consuming
only 35 nA, the TPL5010-Q1 can replace the
functionality of the integrated microcontroller timer
and allow the microcontroller to be placed in a much
lower power mode. Such power savings extend the
operating life of batteries and enable the use of
significantly smaller batteries making the TPL5010­Q1 ideal for power sensitive applications.. The
TPL5010-Q1 provides selectable timing intervals from
100 ms to 7200 s and is designed for interrupt-driven
applications. Some standards (such as EN50271)
require implementation of a watchdog for safety and
the TPL5010-Q1 realizes this watchdog function at
almost no additional power consumption. The
TPL5010-Q1 is available in a 6-pin SOT23 package.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPL5010-Q1 SOT23 (6) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

Simplified Application

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPL5010-Q1

SNAS679 –SEPTEMBER 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions ...................... 4

7.4 Thermal Information ................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements ............................................... 6

7.7 Typical Characteristics.............................................. 7

8 Detailed Description.............................................. 8

8.1 Overview ................................................................... 8

8.2 Functional Block Diagram......................................... 8

4 Revision History

DATE REVISION NOTES

September 2016 * Initial release.

8.3 Feature Description................................................... 8

8.4 Device Functional Modes.......................................... 9

8.5 Programming ............................................................ 9

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

10 Power Supply Recommendations ..................... 17

11 Layout................................................................... 17

11.1 Layout Guidelines ................................................. 17

11.2 Layout Example .................................................... 17

12 Device and Documentation Support................. 18

12.1 Receiving Notification of Documentation Updates 18

12.2 Community Resources.......................................... 18

12.3 Trademarks........................................................... 18

12.4 Electrostatic Discharge Caution............................ 18

12.5 Glossary................................................................ 18

13 Mechanical, Packaging, and Orderable

Information........................................................... 18

5 Device Comparison Table

TPL5x10Q Family of AEC-Q100 Nano- Power System Timers

PART NUMBER SUPPLY CURRENT (Typ) SPECIAL FEATURES

TPL5010-Q1 35 nA

TPL5110-Q1 35 nA

Low Power Timer

Watchdog Function

Programmable Delay Range

Manual Reset

Low Power Timer

MOS-Driver

Programmable Delay Range

Manual Reset

One-Shot Feature

2

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TPL5010-Q1

VDD

GND

RSTn

WAKE

DELAY/
M_RST

DONE

1

2

3 4

5

6

TPL5010-Q1

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SNAS679 –SEPTEMBER 2016

6 Pin Configuration and Functions

SOT23

6-Pin DDC

Top View

Table 1. Pin Functions

PIN

NO. NAME

1 VDD P Supply voltage
2 GND G Ground
3 DELAY/

M_RST

4 DONE I Logic Input for watchdog functionality Digital signal driven by the µC to indicate successful

5 WAKE O Timer output signal generated every t

6 RSTn O Reset Output (open drain output) Digital signal to RESET the µC, pull-up resistance is

(1) G= Ground, P= Power, O= Output, I= Input.

(1)

TYPE

I Time Interval set and Manual Reset Resistance between this pin and GND is used to

period.

DESCRIPTION APPLICATION INFORMATION

select the time interval. The reset switch is also
connected to this pin.

processing of the WAKE signal.
Digital pulsed signal to wake up the µC at the end of

IP

the programmed time interval.

required

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TPL5010-Q1

SNAS679 –SEPTEMBER 2016

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDD-GND) –0.3 6.0 V
Input voltage at any pin

(2)

Input current on any pin –5 5 mA

T

stg

T

J

Storage temperature –65 150 °C
Junction temperature

(3)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The voltage between any two pins should not exceed 6V.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power

dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC
board.

7.2 ESD Ratings

V

(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.

Human-body model, per AEC Q100-002
Charged-device model (CDM), per AEC Q10-011 ±750

(1)

MIN MAX UNIT

–0.3 VDD + 0.3 V

150 °C

VALUE UNIT

(1)

±2000

V

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage (VDD-GND) 1.8 5.5 V
Temperature –40 125 °C

7.4 Thermal Information

TPL5010-Q1

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

Junction-to-ambient thermal resistance 163 °C/W
Junction-to-case (top) thermal resistance 26 °C/W
Junction-to-board thermal resistance 57 °C/W
Junction-to-top characterization parameter 7.5 °C/W
Junction-to-board characterization parameter 57 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITSOT23

6 PINS

4

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7.5 Electrical Characteristics

TA= 25°C, VDD-GND=2.5 V (unless otherwise stated)

PARAMETER TEST CONDITIONS MIN

POWER SUPPLY

IDD Supply current

TIMER

t

IP

Time interval period

Time interval setting accuracy
Timer interval setting accuracy over

supply voltage

t

OSC

Oscillator accuracy –0.5% 0.5%
Oscillator accuracy over

temperature
Oscillator accuracy over supply

voltage
Oscillator accuracy over life time

t

DONE

t

RSTn

t

WAKE

Minimum DONE pulse width
RSTn pulse width 320 ms
WAKE pulse width 20 ms

t_Rext Time to convert Rext

DIGITAL LOGIC LEVELS

VIH Minimum logic high threshold DONE

pin

VIL Maximum logic low threshold DONE

pin

VOH Logic output high-level WAKE pin

VOL Logic output low-level WAKE pin

VOL

IOH

VIH

RSTn

RSTn

M_RST

RSTn logic output low-level IOL= –1 mA 0.3 V
RSTn high-level output current VOH
Minimum logic high threshold

DELAY/M_RST pin

(1) Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating

of the device such that TJ= TA.No specification of parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be
permanently degraded, either mechanically or electrically.

(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through

correlations using statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) The accuracy for time interval settings below 1 second is ±100 ms.
(7) Operational life time test procedure equivalent to 10 years.

(4)

(5)

(6)

(5)

(5)

(7)

(5)

(5)

(5)

(1)

(2)

TYP

(3)

MAX

(2)

UNIT

Operation mode 35 50 nA
Digital conversion of external

200 400 µA

resistance (Rext)

1650 selectable time
Intervals

Min time interval 100 ms
Max time

7200

interval

s

Excluding the precision of Rext ±0.6%

1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V

-40°C ≤ TA≤ 125°C 150 ppm/°C

1.8 V ≤ VDD ≤ 5.5 V ±0.4 %/V

0.24%
100 ns

100 ms

0.7 ×

V

VDD

0.3 ×

V

VDD
Iout = 100 µA VDD – 0.3 V
Iout = 1 mA VDD – 0.7 V
Iout = –100 µA 0.3 V
Iout = –1 mA 0.7 V

= VDD 1 nA

RSTn

1.5 V

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5

WAKE

VDD

DONE

RSTn

t

t

IP

t

tt

R_EXT

+ t

RSTn

t

t

tD

DONE

t

t

DONE

tr

RSTn

tf

RSTn

tr

WAKE

tf

WAKE

tt

RSTn+tDB

t

tt

RSTn

+ tIPt

DELAY/
M_RST

tt

WAKE

t

tt

M_RST

tt

RSTn

t

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SNAS679 –SEPTEMBER 2016

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7.6 Timing Requirements

(1)

MIN

tr

RSTn

tf

RSTn

tr

WAKE

tf

WAKE

tD

DONE

t

M_RST

t

DB

Rise Time RSTn
Fall time RSTn
Rise time WAKE
Fall time WAKE

DONE to RSTn or WAKE to
DONE delay

Minimum valid manual reset
De-bounce manual reset 20 ms

(3)

(3)

(3)

(3)

Capacitive load 50 pF, Rpull-up 100 kΩ 11 µs
Capacitive load 50 pF, Rpull-up 100 kΩ 50 ns
Capacitive load 50 pF 50 ns
Capacitive load 50 pF 50 ns
Min delay
Max delay

(3)

Observation time 30 ms 20 ms

(4)

(4)

(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through

correlations using statistical quality control (SQC) method.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.

NOM

(2)

MAX

(1)

UNIT

100 ns

tIP–20 ms

Figure 1. TPL5010-Q1 Timing

6

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Accuracy (%)

Frequency

0

5%

10%

15%

20%

25%

30%

35%

40%

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Time (s)

Supply current (PA)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.01

0.1

1

10

100

1000

POR

R

EXT

READING

TIMER MODE

Supply Voltage (V)

Oscillator accuracy (%)

1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

-1

-0.5

0

0.5

1

1.5

2

TA= -40°C
TA= 25°C
TA= 70°C
TA= 105°C
TA= 125°C

Temperature (°C)

Oscillator accuracy (%)

-40 -25 -10 5 20 35 50 65 80 95 110 125

-1

-0.5

0

0.5

1

1.5

2

VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V

Temperature (°C)

Supply current (nA)

-40 -25 -10 5 20 35 50 65 80 95 110 125

20

30

40

50

60

70

80

90

100

VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V

Supply Voltage (V)

Supply current (nA)

1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

20

30

40

50

60

70

80

90

100

TA= -40°C
TA= 25°C
TA= 70°C
TA= 105°C
TA = 125°C

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7.7 Typical Characteristics

TPL5010-Q1

SNAS679 –SEPTEMBER 2016

Figure 2. IDDvs V

DD

Figure 4. Oscillator Accuracy vs V

DD

Figure 3. IDDvs Temperature

Figure 5. Oscillator Accuracy vs Temperature

Figure 6. IDDvs Time

number of

observations >

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1 s < tIP≤ 7200 s

20000

Figure 7. Time Interval Setting Accuracy

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7

WAKE

DONE

RSTn

DELAY/
M_RST

t

t

IP

t

t

t

IP

t

tt

RSTn

+ tIPt

MISSED

DONE

LOW FREQUENCY

OSCILLATOR

FREQUENCY

DIVIDER

RSTn
WAKE

VDD

GND

DELAY/
M_RST

DECODER

&

MANUAL RESET

DETECTOR

LOGIC

CONTROL

DONE

TPL5010-Q1

SNAS679 –SEPTEMBER 2016

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8 Detailed Description

8.1 Overview

The TPL5010-Q1 is a system wakeup timer with a watchdog feature, ideal for low power applications. TPL5010­Q1 is ideal for use in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.

8.2 Functional Block Diagram

8.3 Feature Description

The DONE, WAKE and RSTn signals are used to implement the watchdog function. The TPL5010-Q1 is
programmed to issue a periodic WAKE pulse to a µC which is in sleep or standby mode. After receiving the
WAKE pulse, the µC must issue a DONE signal to the TPL5010-Q1 at least 20 ms before the rising edge of the
next WAKE pulse. If the DONE signal is not asserted, the TPL5010-Q1 asserts the RSTn signal to reset the µC.
A manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD.

Figure 8. Watchdog

8.3.1 WAKE

The WAKE pulse is sent out from the TPL5010-Q1 when the programmed time interval starts (except at the
beginning of the first cycle or if in the previous interval the DONE has not been received).

This signal is normally low.

8.3.2 DONE

The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010-Q1
recognizes a valid DONE signal as a low to high transition; if two or more DONE signals are received within the
time interval, only the first DONE signal is processed.

The DONE signal resets the counter of the watchdog only. If the DONE signal is received when the WAKE is still
high, the WAKE will go low as soon as the DONE is recognized.

8

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