Texas Instruments TPIC6C596N, TPIC6C596D, TPIC6C596DR Datasheet
TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000
D
Low r
DS(on)
D
Avalanche Energy ...30 mJ
D
Eight Power DMOS Transistor Outputs of
...7 Ω Typ
100-mA Continuous Current
D
250-mA Current Limit Capability
D
ESD Protection . . . 2500 V
D
Output Clamp Voltage . . . 33 V
D
Enhanced Cascading for Multiple Stages
D
All Registers Cleared With Single Input
D
Low Power Consumption
description
The TPIC6C596 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The storage register transfers data to the output buffer when shift register
clear (CLR
in the device are cleared. When output enable (G)
is held high, all data in the output buffers is held
) is high. When CLR is low, all registers
logic symbol
8
G
10
RCK
7
CLR
SRCK
SER IN
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
15
2
D OR N PACKAGE
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
†
EN3
C2
SRG8
R
C1
1D
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
2
2
3
4
5
6
11
12
13
14
9
low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buf fers. When data in the output buf fers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
available from Texas Instruments.
Guidelines for
Copyright 2000, Texas Instruments Incorporated
1
TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability . Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and 200 V machine model.
The TPIC6C596 is characterized for operation over the operating case temperature range of –40°C to 125°C.
logic diagram (positive logic)
8
G
10
RCK
CLR
SRCK
SER IN
15
7
D
C1
2
CLR
D
C1
CLR
D
C2
CLR
D
C2
CLR
3
4
5
DRAIN0
DRAIN1
DRAIN2
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C2
CLR
D
C2
CLR
D
C2
CLR
D
C2
CLR
D
C2
CLR
D
C2
CLR
16
6
11
12
13
14
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
GND
D
C1
CLR
2
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9
SER OUT
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
25 V
12 V
TPIC6C596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000
DRAIN
33 V
20 V
GND
GND
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
Continuous drain current, each output, all outputs on, ID, TC = 25°C 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,T
Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, I
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 4).
†
, T
= 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . .
D
C
= 25°C (see Note 3) 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
(see Note 4) 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AS
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
DISSIPATION RATING TABLE
PACKAGE
D 1087 mW 8.7 mW/°C 217 mW
N 1470 mW 11.7 mW/°C 294 mW
TC ≤ 25°C
POWER RATING
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DERATING FACTOR
ABOVE TC = 25°C
POWER RATING
TC = 125°C
3
TPIC6C596
VOHHigh-level output voltage, SER OUT
V
VOLLow-level output voltage, SER OUT
V
ICCLogic supply current
V
V
A
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS093 – MARCH 2000
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Pulsed drain output current, TC = 25°C, VCC = 5 V, all outputs on (see Notes 3 and 5 and Figure 11) 250 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 15 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, T
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ – TC to 10°C maximum.
CC
IH
IL
C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
SD
I
IH
I
IL
I
CC(FRQ)
I
N
I
DSX
r
DS(on)
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
Drain-to-source breakdown voltage ID = 1 mA 33 37 V
Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V
p
p
High-level input current VCC = 5.5 V, VI = V
Low-level input current VCC = 5.5 V, VI = 0 –1 µA
pp
Logic supply current at frequency
Nominal current
Off-state drain current
Static drain-source on-state resistance
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
IOH = –20 µA, VCC = 4.5 V 4.4 4.49
IOH = –4 mA, VCC = 4.5 V 4 4.2
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
IOL = 4 mA, VCC = 4.5 V 0.3 0.5
CC
= 5.5
CC
f
= 5 MHz,
SRCK
All outputs off,
V
TC = 85°C,
VDS = 30 V, VCC = 5.5 V 0.1 5
VDS = 30 V,
TC = 125°C
ID = 50 mA,
VCC = 4.5 V
ID = 50 mA,
TC = 125°C,
VCC = 4.5 V
ID = 100 mA,
VCC = 4.5 V
DS(on)
= 0.5 V,
All outputs off 20 200
All outputs on 150 500
CL = 30 pF,
See Figures 2 and 6
IN = ID,
See Notes 5, 6 and 7
VCC = 5.5 V,
See Notes 5 and 6
and Figures 7 and 8
4.5 5.5 V
0.85 V
CC
0.15 V
CC
–40 125 °C
1 µA
1.2 5 mA
90 mA
0.15 8
6.5 9
9.9 12
6.8 10
V
V
µ
µA
Ω
4
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