TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
...5 Ω
D
Avalanche Energy ...30 mJ
D
Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current
D
500-mA Typical Current-Limiting Capability
D
Output Clamp Voltage . . . 50 V
D
Enhanced Cascading for Multiple Stages
D
All Registers Cleared With Single Input
D
Low Power Consumption
description
The TPIC6B596 is a monolithic, high-voltage,
medium-current power 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other mediumcurrent or high-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shiftregister clear (SRCLR
) is high. When SRCLR is
low, all registers in the device are cleared. When
output enable (G) is held high, all data in the
output buffers is held low and all drain outputs are
off. When G
is held low, data from the storage
register is transparent to the output buffers. When
data in the output buffers is low, the DMOStransistor outputs are off. When data is high, the
DMOS-transistor outputs have sink-current capability . The serial output (SER OUT) is clocked out of the device
on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved
performance for applications where clock signals may be skewed, devices are not located near one another,
or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sinkcurrent capability . Each output provides a 500-mA typical current limit at T
C
= 25°C. The current limit decreases
as the junction temperature increases for additional device protection.
The TPIC6B596 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
GND
NC
GND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
GND
DW OR N PACKAGE
(TOP VIEW)
logic symbol
†
2
SRG8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
9
12
8
13
3
EN3
C2
R
C1
1D
G
RCK
SRCLR
SRCK
SER IN
4
6
5
14
7
16
15
18
17
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
NC – No internal connection
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G
RCK
SRCLR
SRCK
SER IN
CLR
D
C1
D
C2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
4
DRAIN0
5
DRAIN1
10, 11, 19
GND
6
DRAIN2
7
DRAIN3
14
DRAIN4
15
DRAIN5
16
DRAIN6
17
DRAIN7
9
8
3
12
13
18
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
D
C1
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
GND
GND
DRAIN
50 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
D
, T
C
= 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, ID, TC = 25°C 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,T
C
= 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, I
AS
(see Note 4) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
DW 1389 mW 11.1 mW/°C 278 mW
N 1050 mW 10.5 mW/°C 263 mW
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, V
CC
4.5 5.5 V
High-level input voltage, V
IH
0.85 V
CC
V
Low-level input voltage, V
IL
0.15 V
CC
V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –500 500 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 15 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 15 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, T
C
–40 125 °C
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ – TC to 10°C maximum.
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 1 mA 50 V
V
SD
Source-to-drain diode forward
voltage
IF = 100 mA 0.85 1 V
High-level output voltage,
IOH = –20 µA, VCC = 4.5 V 4.4 4.49
V
OH
gg,
SER OUT
IOH = –4 mA, VCC = 4.5 V
4 4.2
V
Low-level output voltage,
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
V
OL
g,
SER OUT
IOL = 4 mA, VCC = 4.5 V
0.3 0.5
V
I
IH
High-level input current VCC = 5.5 V, VI = V
CC
1 µA
I
IL
Low-level input current VCC = 5.5 V, VI = 0 –1 µA
pp
All outputs off 20 100
ICCLogic supply current
V
CC
= 5.5
V
All outputs on 150 300
µ
A
I
CC(FRQ)
Logic supply current at frequency
f
SRCK
= 5 MHz, CL = 30 pF,
All outputs off, See Figures 2 and 6
0.4 5 mA
I
N
Nominal current
V
DS(on)
= 0.5 V,
IN = ID,T
C
= 85°C
See Notes 5, 6, and 7 90 mA
VDS = 40 V, VCC = 5.5 V 0.1 5
I
DSX
Off-state drain current
VDS = 40 V, VCC = 5.5 V, TC = 125°C 0.15 8
µ
A
ID = 100 mA, VCC = 4.5 V 4.2 5.7
r
DS(on)
Static drain-source on-state
resistance
ID = 100 mA, TC = 125°C,
VCC = 4.5 V
See Notes 5 and 6
and Figures 7 and 8
6.8 9.5
Ω
ID = 350 mA, VCC = 4.5 V 5.5 8
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output from G 150 ns
t
PHL
Propagation delay time, high-to-low-level output from G
C
= 30 pF, I
= 100 mA,
90 ns
t
r
Rise time, drain output
L
,
D
,
See Figures 1, 2, and 9
200 ns
t
f
Fall time, drain output 200 ns
t
pd
Propagation delay time, SRCK↓ to SEROUT
CL = 30 pF, ID = 100 mA,
See Figure 2
15 ns
f
(SRCK)
Serial clock frequency
CL = 30 pF, ID = 100 mA,
See Note 8
10 MHz
t
a
Reverse-recovery-current rise time
I
= 100 mA, di/dt = 20 A/µs,
100
t
rr
Reverse-recovery time
F
, µ ,
See Notes 5 and 6 and Figure 3
300
ns
NOTES: 5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
DW package
p
p
90
°
R
θJA
Thermal resistance, junction-to-ambient
N package
All 8 outputs with equal power
95
°C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
V
CC
DRAIN
GND
SRCLR
SER IN
RL = 235 Ω
CL = 30 pF
(see Note B)
VOLTAGE WA VEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
76543210
5 V
SRCK
5 V
G
5 V
SER IN
RCK
SRCLR
5 V
5 V
DUT
24 V
DRAIN1
24 V
0 V
0 V
0 V
0.5 V
0 V
10, 11, 19
8
13
3
12
9
0 V
4–7,
14–17
I
D
2
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
4–7,
14–17
TEST CIRCUIT
5 V 24 V
V
CC
DRAIN
SRCLR
SER IN
RL = 235 Ω
CL = 30 pF
(see Note B)
G
Output
SRCK
RCK
DUT
GND
Word
Generator
(see Note A)
10, 11, 19
8
13
3
12
9
I
D
2
SWITCHING TIMES
G
5 V
50%
24 V
0.5 V
90%
10%
t
PLH
t
r
50%
90%
10%
t
PHL
t
f
SRCK
5 V
50%
SER IN
5 V
50%
50%
t
su
t
h
t
w
INPUT SETUP AND HOLD WAVEFORMS
Output
0 V
0 V
0 V
50% 50%
50%50%
t
pd
t
pd
SRCK
SER OUT
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.1 A
I
F
0
I
RM
25% of I
RM
t
a
t
rr
di/dt = 20 A/µs
+
–
2500 µF
250 V
L = 1 mH
I
F
(see Note A)
R
G
V
GG
(see Note B)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
25 V
t
1
t
3
t
2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
15 V
10.5 Ω
200 mH
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
t
w
t
av
IAS = 0.5 A
V
(BR)DSX
= 50 V
VOLTAGE AND CURRENT WAVEFORMS
Input
I
D
V
DS
See Note B
V
CC
DRAIN
SRCLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
GND
5 V
V
DS
I
D
2
8
13
3
12
9
10, 11, 19
4–7,
14–17
5 V
0 V
MIN
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A.
Energy test level is defined as EAS = IAS × V
(BR)DSX
× tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I – Peak Avalanche Current – A
AS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
tav – Time Duration of Avalanche – ms
TC = 25°C
Figure 6
I – Supply Current – mA
CC
SUPPLY CURRENT
vs
FREQUENCY
f – Frequency – MHz
1
0.5
0
0.1 1 10
1.5
2
100
2.5
VCC = 5 V
TC = –40°C to 125°C
Figure 7
10
8
4
2
0
6
0 100 200 300 400
14
12
16
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
18
500 600 700
ID – Drain Current – mA
VCC = 5 V
See Note A
TC = 25°C
TC = –40°C
TC = 125°C
Ω
DS(on)
– Drain-to-Source On-State Resistance –r
Figure 8
VCC – Logic Supply Voltage – V
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
4
3
1
0
4 4.5 5 5.5
5
7
8
6 6.5 7
6
2
TC = 125°C
TC = 25°C
TC = – 40°C
ID = 100 mA
See Note A
Ω
DS(on)
– Static Drain-to-Source On-State Resistance –r
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Switching Time – ns
SWITCHING TIME
vs
CASE TEMPERATURE
–50
TC – Case Temperature – °C
ID = 100 mA
See Note A
200
150
100
50
250
300
t
PHL
t
PLH
t
r
t
f
–25 0 25 50 75 100 125
Figure 9
NOTE A: Technique should limit TJ – TC to 10°C maximum.
TPIC6B596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS095 – MARCH 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 10
– Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
N – Number of Outputs Conducting Simultaneously
of Each Output – A
D
I
0
123 4 5678
VCC = 5 V
TC = 25°C
TC = 125°C
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
TC = 100°C
Figure 11
– Maximum Peak Drain Current of Each Output – A
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
D
N – Number of Outputs Conducting Simultaneously
I
0.15
0.05
0.4
0
12 34 5
0.3
0.2
0.35
0.5
678
0.45
0.25
0.1
VCC = 5 V
TC = 25°C
d = tw/t
period
= 1 ms/t
period
d = 10%
d = 20%
d = 50%
d = 80%
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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