APPLICATION CIRCUIT
Actual Solution Siz e
6,9 mm
5,25 mm
(1)
C
B
R
I
R
I
C
S
R
F
R
F
_
+
V
DD
V
O+
V
O-
GND
To Battery
C
s
Bias
Circuitry
IN-
IN+
+
-
In From
DAC
SHUTDOWN
R
I
R
I
R
F
R
F
Applies to the GQV/ZQV Packages Only
C
( )
BYPASS
(Optional)
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
FEATURES APPLICATIONS
• 1.25 W Into 8 Ω From a 5-V Supply at
THD = 1% (Typical)
• Low Supply Current: 1.7 mA Typical
• Shutdown Control < 10 µ A
• Only Five External Components
– Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
– Fully Differential Design Reduces RF
Rectification
– Improved CMRR Eliminates Two Input
Coupling Capacitors
– C
(BYPASS)
Design and High PSRR
• Avaliable in a 2 mm x 2 mm MicroStar
Junior ™ BGA Package (GQV, ZQV)
• Available in 3 mm x 3 mm QFN Package
(DRB)
• Available in an 8-Pin PowerPAD™ MSOP
(DGN)
Is Optional Due to Fully Differential
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
• Designed for Wireless or Cellular Handsets
and PDAs
DESCRIPTION
The TPA6203A1 is a 1.25-W mono fully differential
amplifier designed to drive a speaker with at least
8- Ω impedance while consuming less than 37 mm
(ZQV package option) total printed-circuit board
(PCB) area in most applications. This device operates
from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent
supply current. The TPA6203A1 is available in the
space-saving 2 mm x 2 mm MicroStar Junior™ BGA
package, and the space saving 3 mm x 3 mm QFN
(DRB) package.
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6203A1 ideal for wireless
handsets. A fast start-up time of 4 µ s with minimal
pop makes the TPA6203A1 ideal for PDA
applications.
2
Junior, PowerPAD, MicroStar Junior are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2002–2005, Texas Instruments Incorporated
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES
MicroStar Junior™ MicroStar Junior™ QFN MSOP
(GQV) (ZQV) (DRB) (DGN)
Device TPA6203A1GQVR TPA6203A1ZQVR TPA6203A1DRB TPA6203A1DGN
Symbolization AADI AAEI AAJI AAII
(1) The GQV is the standard MicroStar Junior package. The ZQV is a lead-free option and is qualified for 260 ° lead-free assembly.
(2) The GQV and ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts.
(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
Supply voltage, V
Input voltage, V
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature, T
Junction temperature, T
Storage temperature, T
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DD
I
J
stg
INx and SHUTDOWN pins -0.3 V to V
A
(1)
ZQV, DRB, DGN 260 ° C
GQV 235 ° C
(1) (2) (3)
UNIT
-0.3 V to 6 V
DD
-40 ° C to 85 ° C
-40 ° C to 125 ° C
-65 ° C to 85 ° C
+ 0.3 V
RECOMMENDED OPERATING CONDITIONS
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Common-mode input voltage, V
Operating free-air temperature, T
Load impedance, Z
DD
IH
IL
L
DISSIPATION RATINGS
PACKAGE DERATING FACTOR
GQV, ZQV 885 mW 8.8 mW/ ° C 486 mW 354 mW
DRB 2.7 W 21.8 mW/ ° C 1.7 W 1.4 W
2
MIN TYP MAX UNIT
2.5 5.5 V
SHUTDOWN 2 V
SHUTDOWN 0.8 V
V
IC
A
= 2.5 V, 5.5 V, CMRR ≤ -60 dB 0.5 VDD-0.8 V
DD
-40 85 ° C
6.4 8 Ω
TA≤ 25 ° C TA= 70 ° C TA= 85 ° C
POWER RATING POWER RATING POWER RATING
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
TA= 25 ° C, Gain = 1 V/V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
PSRR Power supply rejection ratio V
CMRR Common-mode rejection ratio dB
V
V
|IIH| High-level input current V
|IIL| Low-level input current V
I
DD
I
DD(SD)
Output offset voltage (measured
| VI= 0 V, V
OO
differentially)
= 2.5 V to 5.5 V -90 -70 dB
DD
V
= 3.6 V to 5.5 V, VIC= 0.5 V to VDD-0.8 -70 -65
DD
V
= 2.5 V, VIC= 0.5 V to 1.7 V -62 -55
DD
Low-level output voltage V
OL
High-level output voltage V
OH
Supply current V
RL= 8 Ω , V
V
= 0 V or V
IN-
RL= 8 Ω , V
V
= 0 V or V
IN-
= 5.5 V, VI= 5.8 V 1.2 µ A
DD
= 5.5 V, VI= -0.3 V 1.2 µ A
DD
= 2.5 V to 5.5 V, No load, SHUTDOWN = 2 V 1.7 2 mA
DD
= 2.5 V to 5.5 V 9 mV
DD
= VDD,
IN+
= 0 V, V
IN+
= VDD,
IN+
= 0 V, V
IN+
Supply current in shutdown mode SHUTDOWN = 0.8 V, V
V
= 5.5 V 0.30 0.46
DD
= 3.6 V 0.22 V
= V
IN-
DD
= V
IN-
DD
= 2.5 V to 5.5 V, No load 0.01 0.9 µ A
DD
DD
V
= 2.5 V 0.19 0.26
DD
V
= 5.5 V 4.8 5.12
DD
= 3.6 V 3.28 V
DD
V
= 2.5 V 2.1 2.24
DD
OPERATING CHARACTERISTICS
TA= 25 ° C, Gain = 1 V/V, RL= 8 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
= 5 V 1.25
DD
P
THD+N V
k
SVR
SNR Signal-to-noise ratio V
V
CMRR resistor tolerance = 0.1%, dB
Z
I
Z
O
Output power THD + N = 1%, f = 1 kHz V
O
V
= 5 V, PO= 1 W, f = 1 kHz 0.06%
Total harmonic distortion
plus noise
Supply ripple rejection ratio V
Output voltage noise f = 20 Hz to 20 kHz µ V
n
Common-mode rejection
ratio
DD
= 3.6 V, PO= 0.5 W, f = 1 kHz 0.07%
DD
V
= 2.5 V, PO= 200 mW, f = 1 kHz 0.08%
DD
C
(BYPASS)
V
DD
Inputs ac-grounded with CI= 2 µ F
C
(BYPASS)
DD
Inputs ac-grounded with CI= 2 µ F
C
(BYPASS)
V
DD
Inputs ac-grounded with CI= 2 µ F
DD
V
DD
gain = 4V/V, V
= 0.47 ° F,
= 3.6 V to 5.5 V, -87
= 0.47 µ F,
= 2.5 V to 3.6 V, -82 dB
= 0.47 µ F,
= 2.5 V to 5.5 V, ≤ -74
= 5 V, PO= 1 W 104 dB
= 2.5 V to 5.5 V, f = 20 Hz to 1 kHz ≤ -85
= 200 mV
ICM
PP
= 3.6 V 0.63 W
DD
V
= 2.5 V 0.3
DD
f = 217 Hz to 2 kHz,
V
= 200 mV
RIPPLE
PP
f = 217 Hz to 2 kHz,
V
= 200 mV
RIPPLE
PP
f = 40 Hz to 20 kHz,
V
= 200 mV
RIPPLE
PP
No weighting 17
A weighting 13
f = 20 Hz to 20 kHz ≤ -74
Input impedance 2 M Ω
Output impedance Shutdown mode >10k
Shutdown attenuation f = 20 Hz to 20 kHz, RF= RI= 20 k Ω -80 dB
RMS
3
(SIDE VIEW)
SHUTDOWN
IN+
V
DD
V
O+
GND
V
O-
IN-
A
B
C
1 2 3
BYPASS
8
SHUTDOWN
BYPASS
IN+
IN-
V
O-
GND
V
DD
V
O+
7
6
5
1
2
3
4
7
6
5
1
2
3
SHUTDOWN
BYPASS
IN+
IN-
V
O-
GND
V
DD
V
O+
4
8
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
MicroStar Junior™ (GQV or ZQV) PACKAGE
(TOP VIEW)
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
8-PIN MSOP (DGN) PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
NAME GQV
DRB,
DGN
BYPASS C1 2 I Mid-supply voltage. Adding a bypass capacitor improves PSRR.
GND B2 7 I High-current ground
IN- C3 4 I Negative differential input
IN+ C2 3 I Positive differential input
SHUTDOWN B1 1 I Shutdown terminal (active low logic)
V
DD
V
O+
V
O-
A3 6 I Supply voltage terminal
B3 5 O Positive BTL output
A1 8 O Negative BTL output
Thermal Pad
I/O DESCRIPTION
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device
on the PCB.
4
Table of Graphs
P
P
CMRR Common-mode rejection ratio
I
DD
Output power
O
Power dissipation vs Output power 4, 5
D
Maximum ambient temperature vs Power dissipation 6
Total harmonic distortion + noise vs Frequency 9, 10, 11, 12
Supply voltage rejection ratio vs Frequency 14, 15, 16, 17
Supply voltage rejection ratio vs Common-mode input voltage 18
GSM Power supply rejection vs Time 19
GSM Power supply rejection vs Frequency 20
Closed loop gain/phase vs Frequency 23
Open loop gain/phase vs Frequency 24
Supply current
Start-up time vs Bypass capacitor 27
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS
FIGURE
vs Supply voltage 1
vs Load resistance 2, 3
vs Output power 7, 8
vs Common-mode input voltage 13
vs Frequency 21
vs Common-mode input voltage 22
vs Supply voltage 25
vs Shutdown voltage 26
5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
8 13 18 23 28
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
R
L
- Load Resistance - Ω
- Output Power - WP
O
f = 1 kHz
THD+N = 10%
Gain = 1 V/V
32
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.5 3 3.5 4 4.5 5
V
DD
- Supply Voltage - V
- Output Power - WP
O
RL = 8 Ω
f = 1 kHz
Gain = 1 V/V
THD+N = 1%
THD+N = 10%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
8 13 18 23 28
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
R
L
- Load Resistance - Ω
- Output Power - WP
O
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
32
0
10
20
30
40
50
60
70
80
90
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
PD- Power Dissipation - W
Maximum Ambient Temperature - C
o
ZQV Package Only
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 0.2 0.4 0.6 0.8
8 Ω
16 Ω
P
O
- Output Power - W
- Power Dissipation - WP
D
VDD = 3.6 V
0 0.2 0.4 0.6 0.8 1 1.2 1.4
8 Ω
16 Ω
P
O
- Output Power - W
- Power Dissipation - WP
D
VDD = 5 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VDD = 5 V
CI = 2 µF
RL = 8 Ω
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k100 200 1 k 2 k 10 k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
50 mW
250 mW
1 W
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10 m 3100 m 1 2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
2.5 V
3.6 V
5 V
RL = 8 Ω, f = 1 kHz
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10 m 100 m 1 2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
2.5 V
5 V
3.6 V
RL = 16 Ω
f = 1 kHz
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
OUTPUT POWER OUTPUT POWER OUTPUT POWER
vs vs vs
SUPPLY VOLTAGE LOAD RESISTANCE LOAD RESISTANCE
Figure 1. Figure 2. Figure 3.
TYPICAL CHARACTERISTICS
POWER DISSIPATION POWER DISSIPATION MAXIMUM AMBIENT
vs vs TEMPERATURE
OUTPUT POWER OUTPUT POWER vs
POWER DISSIPATION
Figure 4. Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +
NOISE NOISE NOISE
vs vs vs
OUTPUT POWER OUTPUT POWER FREQUENCY
6
Figure 7. Figure 8. Figure 9.
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
25 mW
125 mW
500 mW
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
15 mW
200 mW
75 mW
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
VDD = 3.6 V
CI = 2 µF
RL = 16 Ω
C
(Bypass)
= 0 to 1 µF
Gain = 1 V/V
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
25 mW
250 mW
125 mW
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
VDD = 3.6 V
VDD = 5 V
VDD =2. 5 V
f - Frequency - Hz
- Supply Voltage Rejection Ratio - dBk
SVR
CI = 2 µF
RL = 8 Ω
C
(Bypass)
= 0.47 µF
V
p-p
= 200 mV
Inputs ac-Grounded
Gain = 1 V/V
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
- Supply Voltage Rejection Ratio - dBk
SVR
VDD = 3.6 V
VDD = 5 V
VDD =2. 5 V
Gain = 5 V/V
CI = 2 µF
RL = 8 Ω
C
(Bypass)
= 0.47 µF
V
p-p
= 200 mV
Inputs ac-Grounded
0.01
0.10
1
10
0 0.5 1 1.5 2 2.5 3 3.5
VDD = 2.5 V
VDD = 3.6 V
f = 1 kHz
PO = 200 mW
V
IC
- Common Mode Input Voltage - V
THD+N - Total Harmonic Distortion + Noise - %
-90
-80
-70
-60
-50
-40
-30
-20
-10
0 1 2 3 4 5
V
IC
- Common Mode Input Voltage - V
f = 217 Hz
C
(Bypass)
= 0.47 µF
RL = 8 Ω
Gain = 1 V/V
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
- Supply Voltage Rejection Ratio - dBk
SVR
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
- Supply Voltage Rejection Ratio - dBk
SVR
VDD =2. 5 V
VDD = 5 V
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Inputs Floating
Gain = 1 V/V
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Inputs ac-Grounded
Gain = 1 V/V
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
- Supply Voltage Rejection Ratio - dBk
SVR
C
(Bypass)
= 0.1 µF
C
(Bypass)
= 0
C
(Bypass)
= 0.47 µF
C
(Bypass)
= 1 µF
TYPICAL CHARACTERISTICS (continued)
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +
NOISE NOISE NOISE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION + SUPPLY VOLTAGE REJECTION SUPPLY VOLTAGE REJECTION
NOISE RATIO RATIO
vs vs vs
COMMON MODE INPUT VOLTAGE FREQUENCY FREQUENCY
SUPPLY VOLTAGE REJECTION SUPPLY VOLTAGE REJECTION SUPPLY VOLTAGE REJECTION
Figure 13. Figure 14. Figure 15.
RATIO RATIO RATIO
vs vs vs
FREQUENCY FREQUENCY COMMON MODE INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
7
f - Frequency - Hz
0
-50
-100
0 200 400 600 800 1k 1.2k
- Output Voltage - dBV
1.4k1.6k 1.8k 2k
-150
-150
-100
0
-50
V
O
- Supply Voltage - dBVV
DD
VDD Shown in Figure 19
CI = 2 µF,
C
(Bypass)
= 0.47 µF,
Inputs ac-Grounded
Gain = 1V/V
C1
Frequency
217.41 Hz
C1 - Duty
20 %
C1 High
3.598 V
C1 Pk-Pk
504 mV
Voltage - V
Ch1 100 mV/div
Ch4 10 mV/div
2 ms/div
t - Time - ms
V
DD
V
O
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f - Frequency - Hz
CMRR - Common Mode Rejection Ratio - dB
VDD = 2.5 V to 5 V
VIC = 200 mV
p-p
RL = 8 Ω
Gain = 1 V/V
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
10 100 10 k 100 k 1 M 10 M
-220
-180
-140
-100
-60
-20
20
60
100
140
180
220
1 k
f - Frequency - Hz
Gain - dB
Phase - Degrees
Gain
Phase
VDD = 3.6 V
RL = 8 Ω
Gain = 1 V/V
-200
-150
-100
-50
0
50
100
150
200
100 1 k 10 k 100 k 1 M
-200
-150
-100
-50
0
50
100
150
200
f - Frequency - Hz
Gain - dB
Phase - Degrees
Gain
Phase
VDD = 3.6 V
RL = 8 Ω
10 M
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RL = 8 Ω
Gain = 1 V/V
V
IC
- Common Mode Input Voltage - V
CMRR - Common Mode Rejection Ratio - dB
VDD = 3.6 V
VDD = 5 V
VDD = 2.5 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
DD
- Supply Voltage - V
- Supply Current - mA
I
DD
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
Voltage on SHUTDOWN Terminal - V
- Supply Current - mA
I
DD
0.2
0
1
2
3
4
5
6
0 0.5 1 1.5 2
C
(Bypass)
- Bypass Capacitor - µF
Start-Up Time - ms
(1)
Start-Up time is the time it takes (from a
low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach -3 dB of the final
gain.
TPA6203A1
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
GSM POWER SUPPLY GSM POWER SUPPLY COMMON MODE REJECTION RATIO
REJECTION REJECTION vs
vs vs FREQUENCY
TIME FREQUENCY
Figure 19. Figure 20. Figure 21.
TYPICAL CHARACTERISTICS (continued)
COMMON MODE REJECTION RATIO CLOSED LOOP GAIN/PHASE OPEN LOOP GAIN/PHASE
vs vs vs
COMMON MODE INPUT VOLTAGE FREQUENCY FREQUENCY
Figure 22. Figure 23. Figure 24.
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SHUTDOWN VOLTAGE
START-UP TIME
BYPASS CAPACITOR
(1)
vs
8
Figure 25. Figure 26. Figure 27.
APPLICATION INFORMATION
_
+
V
DD
V
O+
V
O-
GND
To Battery
C
s
Bias
Circuitry
IN-
IN+
+
-
In From
DAC
SHUTDOWN
R
I
R
I
C
( )
BYPASS
(Optional)
R
F
R
F
FULLY DIFFERENTIAL AMPLIFIER
The TPA6203A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential
voltage that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
V
/2 regardless of the common- mode voltage at the
DD
input.
Advantages of Fully Differential Amplifiers
• Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6203A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has mid-supply lower than the mid-supply of
the TPA6203A1, the common-mode feedback
circuit adjusts for that, and the TPA6203A1
outputs are still biased at mid-supply of the
TPA6203A1. The inputs of the TPA6203A1 can
be biased from 0.5 V to V
are biased outside of that range, input coupling
capacitors are required.
- 0.8 V. If the inputs
DD
SLOS364E – MARCH 2002 – REVISED DECEMBER 2005
• Mid-supply bypass capacitor, C
(BYPASS)
required: The fully differential amplifier does not
require a bypass capacitor. This is because any
shift in the mid-supply affects both positive and
negative channels equally and cancels at the
differential output. However, removing the bypass
capacitor slightly worsens power supply rejection
ratio (k
), but a slight decrease of k
SVR
acceptable when an additional component can be
eliminated (see Figure 17 ).
• Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter
at a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
APPLICATION SCHEMATICS
Figure 28 through Figure 30 show application
schematics for differential and single-ended inputs.
Typical values are shown in Table 1 .
Table 1. Typical Component Values
COMPONENT VALUE
R
I
R
F
C
C
C
(1) C
(1)
(BYPASS)
S
I
(BYPASS)
is optional
10 k Ω
10 k Ω
0.22 µ F
1 µ F
0.22 µ F
TPA6203A1
, not
may be
SVR
Figure 28. Typical Differential Input Application Schematic
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