TEXAS INSTRUMENTS TPA6140A2 Technical data
INR+
INR-
INL+
INL-
AGND
SGND
OUTR
HPVSS
CPP CPN
SW
HPVDD
OUTL
TPA6140A2
Vbat
CODEC
OUTR+
OUTR-
OUTL+
OUTL-
1 Fm
SDA
SCL SCL
AVDD
SDA
2.2 Hm
2.2 Fm
1 Fm
2.2 Fm
TPA6140A2
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.................................................................................................................................................................................................. SLOS598 – MARCH 2009
CLASS-G DIRECTPATH™ STEREO HEADPHONE AMPLIFIER
WITH I2C VOLUME CONTROL
1
FEATURES DESCRIPTION
2
• TI Class-G Technology Significantly Prolongs
Battery Life and Music Playback Time
– 0.6 mA / Ch Quiescent Current
– 50% to 80% Lower Quiescent Current than
Ground-Referenced Class-AB Headphone
Amplifiers
• DirectPath
Output DC-Blocking Capacitors
– Outputs Biased at 0 V
– Improves Low Frequency Audio Fidelity
• I2C Volume Control
– – 59 dB to +4 dB Gain
• Active Click and Pop Suppression
• Fully Differential Inputs Reduce System Noise
– Also Configurable as Single-Ended Inputs
• SGND Pin Eliminates Ground Loop Noise
• Wide Power Supply Range: 2.5 V to 5.5 V
• 100 dB Power Supply Noise Rejection
• Short-Circuit Current Limiter
• Thermal-Overload Protection
• Software Compatible with TPA6130A2
• 0,4 mm Pitch, 1,6 mm × 1,6 mm WCSP
Package
TM
Technology Eliminates Large
The TPA6140A2 (also known as TPA6140) is a
Class-G DirectPath™ stereo headphone amplifier
with built-in I2C volume control. Class-G technology
maximizes battery life by adjusting the voltage
supplies of the headphone amplifier based on the
audio signal level. At low level audio signals, the
internal supply voltage is reduced to minimize power
dissipation. DirectPath
TM
technology eliminates
external DC-blocking capacitors.
The device operates from a 2.5 V to 5.5 V supply
voltage. Class-G operation keeps total supply current
below 5.0 mA while delivering 500 µ W per channel
into 32 Ω . Shutdown mode reduces the supply
current to less than 3 µ A and is activated through the
I2C interface.
The TPA6140A2 (TPA6140) I2C register map is
compatible to the TPA6130A2, simplifying software
development.
The amplifier outputs have short-circuit and
thermal-overload protection along with ± 8 kV HBM
ESD protection, simplifying end equipment
compliance to the IEC 61000-4-2 ESD standard.
The TPA6140A2 (TPA6140) is available in a 0,4 mm
pitch, 16-bump 1,6 mm × 1,6 mm WCSP (YFF)
package.
APPLICATIONS
• Cellular Phones / Music Phones
• Portable Media / MP3 Players
• Portable CD / DVD Players
1
2 Class-G DirectPath, DirectPath are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2009, Texas Instruments Incorporated
Thermal
Protection
SDA
I2CInterface
SCL
Click-and-Pop
Suppression
Charge
Pump
1 Fm
CPP
CPN
HPVSSSGND
Short-Circuit
Protection
+
–
HPVDD
HPVSS
+
–
HPVDD
HPVSS
OUTL
OUTR
INR+
INR-
INL+
INL-
+
–
Gate
Drivers
AVDD
Optimizer
Ramp
Generator
+
–
Comparator
Audio
Level
Detector
AGND
2.2 Fm
SW
AVDD
HPVDD
HPVDD
HPVDD
Compensation
Network
2.2 Hm
2.2 Fm
TPA6140A2
SLOS598 – MARCH 2009 ..................................................................................................................................................................................................
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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FUNCTIONAL BLOCK DIAGRAM
2 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6140A2
D1 D2 D3 D4
C1 C2 C3 C4
B1 B2 B3 B4
A1 A3 A4
SW
AGND
CPN
SDA
AVDD
CPP
HPVSS
SCL
OUTL
HPVDD
OUTR
INL-
INL+
INR+
A2
SGND
INR-
WCSP PACKAGE
(TOPVIEW)
TPA6140A2
www.ti.com
.................................................................................................................................................................................................. SLOS598 – MARCH 2009
DEVICE PINOUT
TERMINAL INPUT /
NAME
INL – A4 I Inverting left input for differential signals; connect to left input signal through 1 µ F capacitor for
INL+ B4 I Non-inverting left input for differential signals; connect to ground through 1 µ F capacitor for
INR – C4 I Inverting right input for differential signals; connect to right input signal through 1 µ F capacitor for
INR+ D4 I Non-inverting right input for differential signals; connect to ground through 1 µ F capacitor for
SGND C3 I Sense Ground; connect to shield terminal of headphone jack or to AGND
SDA D1 I/O I2C Data; 1.8 V logic compliant
SCL D2 I I2C Clock; 1.8 V logic compliant
OUTL A3 O Left headphone amplifier output; connect to left terminal of headphone jack
OUTR D3 O Right headphone amplifier output; connect to right terminal of headphone jack
CPP B2 P Charge pump positive flying cap; connect to positive side of capacitor between CPP and CPN
CPN C1 P Charge pump negative flying cap; connect to negative side of capacitor between CPP and CPN
SW A1 P Buck converter switching node
AVDD A2 P Primary power supply for device
HPVDD B3 P Power supply for headphone amplifier (DC/DC output node)
AGND B1 P Main Ground for headphone amplifiers, DC/DC converter, and charge pump
HPVSS C2 P Charge pump output; connect 2.2 µ F capacitor to GND
– 40 ° C to 85 ° C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com .
(2) YFF packages are only available taped and reeled. The suffix “ R ” indicates a reel of 3000, the suffix “ T ” indicates a reel of 250.
BALL
WCSP
T
A
OUTPUT /
POWER
(I/O/P)
TERMINAL FUNCTIONS
DESCRIPTION
single-ended input applications
single-ended input applications
single-ended input applications
single-ended input applications
ORDERING INFORMATION
PACKAGED DEVICES
16-ball, 1,6 mm × 1,6 mm WCSP TPA6140A2YFFR AIFI
16-ball, 1,6 mm × 1,6 mm WCSP TPA6140A2YFFT AIFI
(1)
PART NUMBER
(2)
SYMBOL
Copyright © 2009, Texas Instruments Incorporated 3
Product Folder Link(s): TPA6140A2
TPA6140A2
SLOS598 – MARCH 2009 ..................................................................................................................................................................................................
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range, TA= 25 ° C (unless otherwise noted)
VALUE / UNIT
Supply voltage, AVDD – 0.3 V to 6.0 V
Amplifier supply voltage, HPVDD – 0.3 V to 2.0 V
V
Input voltage – 0.3 V to HPV
I
I2C voltage – 0.3 V to AVDD
Output continuous total power dissipation See Dissipation Rating Table
T
Operating free-air temperature range – 40 ° C to 85 ° C
A
T
Operating junction temperature range – 40 ° C to 150 ° C
J
T
Storage temperature range – 65 ° C to 85 ° C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
ESD Protection – HBM
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute – maximum – rated conditions for extended periods may affect device reliability.
PACKAGE
POWER RATING ABOVE TA= POWER RATING POWER RATING
YFF (WCSP) 1.25 W 10 mW/ ° C 800 mW 650 mW
OUTL, OUTR, SGND 8 kV
All other pins 2 kV
DISSIPATION RATINGS TABLE
(1) (2)
OPERATING
TA< 25 ° C FACTOR TA= 70 ° C TA= 85 ° C
25 ° C
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+0.3 V
DD
(1) Derating factor measured with JEDEC High K board: 1S0P – One signal layer and zero plane layers.
(2) See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC
Standard 51-12 for using package thermal information. See JEDEC document page for downloadable
copies: http://www.jedec.org/download/default.cfm .
RECOMMENDED OPERATING CONDITIONS
Supply voltage, AV
V
High-level input voltage SDA, SCL 1.3 V
IH
V
Low-level input voltage SDA, SCL 0.35 V
IL
Voltage applied to Output; OUTR, OUTL (when SWS = 1, device disabled) – 0.3 3.6 V
Voltage applied to Output; OUTR, OUTL (when SWS = 0, HiZ_L = HiZ_R = 1, device in HI-Z mode) – 1.8 1.8 V
T
Operating free-air temperature – 40 85 ° C
A
DD
MIN MAX UNIT
2.5 5.5 V
4 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6140A2
SCL
SDA
t
w(H)
t
w(L)
t
su1
t
h1
TPA6140A2
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.................................................................................................................................................................................................. SLOS598 – MARCH 2009
ELECTRICAL CHARACTERISTICS
TA= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PSRR Power supply rejection ratio AV
CMRR Common-mode rejection ratio HPV
|IIH| High-level input current AV
|IIL| Low-level input current AV
I
SD
I
DD
Soft shutdown current SW Shutdown mode, V
Total supply current AV
(1) Per channel output power assuming a 10 dB crest factor
= 2.5 V to 5.5 V, inputs grounded, GAIN = 0 dB 90 105 dB
DD
= 1.3 V to 1.8 V, GAIN = 0 dB 68 dB
DD
= 2.5 V to 5.5 V, VI= AV
DD
= 2.5 V to 5.5 V, VI= 0 V SCL, SDA 1 µ A
DD
AV
= 3.6 V HPVDD = 1.3 V, Amplifiers active, no load, no
DD
input signal
AV
= 3.6 V, P
DD
= 3.6 V, P
DD
AV
= 3.6 V, P
DD
AV
= 3.6 V, HiZ_L = HiZ_R = HIGH (High output impedance
DD
mode)
= 100 µ W into 32 Ω
OUT
= 500 µ W into 32 Ω
OUT
= 1 mW into 32 Ω
OUT
DD
= 2.5 V to 5.5 V, SWS bit = 1 1 3 µ A
DD
(1)
TIMING CHARACTERISTICS
For I2C interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
t
t
t
t
t
t
t
t
Frequency, SCL No wait states 400 kHz
SCL
Pulse duration, SCL high 0.6 µ s
W(H)
Pulse duration, SCL low 1.3 µ s
W(L)
Setup time, SDA to SCL 100 µ s
SU1
Hold time, SCL to SDA 10 ns
H1
Bus free time between stop and start condition 1.3 µ s
(BUF)
Setup time, SCL to start condition 0.6 µ s
SU2
Hold time, start condition to SCL 0.6 µ s
H2
Setup time, SCL to stop condition 0.6 µ s
SU3
SCL, SDA 1 µ A
1.2 2.0
(1)
, f
= 1 kHz 2.5
AUD
(1)
, f
= 1 kHz 4.0 mA
AUD
, f
= 1 kHz 6.8
AUD
1.0 2.0
Figure 1. SCL and SDA Timing
Product Folder Link(s): TPA6140A2
Copyright © 2009, Texas Instruments Incorporated 5
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition
StopCondition
TPA6140A2
SLOS598 – MARCH 2009 ..................................................................................................................................................................................................
Figure 2. Start and Stop Conditions Timing
OPERATING CHARACTERISTICS
AV
= 3.6 V , TA= 25 ° C, GAIN = 0 dB, RL= 32 Ω (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV
P
O
Output power
(1)
(Outputs in Phase) mW
THD+N Total harmonic distortion plus noise
k
SVR
Δ A
V
V
OS
E
n
f
BUCK
f
PUMP
AC-Power supply rejection ratio dB
Gain matching Between left and right channels 1%
Output offset voltage AV
Noise output voltage A-weighted 5.3 µ V
Buck converter switching frequency PO= 0.5 mW into 32 Ω , f = 1 kHz 600 kHz
Charge pump switching frequency kHz
Start-up time from shutdown 5 ms
R
IN,SE
R
IN,DF
Single Ended Input impedance Gain = 4 dB, per input node 15.6 k Ω
Differential input impedance Gain = 4 dB, per input node 31.2 k Ω
SNR Signal-to-noise ratio V
Thermal shutdown ° C
Z
O,SD
Z
O,HI-Z
Output impedance in shutdown SWS = 1, DC value 8 k Ω
Output impedance in Hi-Z mode 6 MHz, 1.8 V
Crosstalk PO= 15 mW, f = 1 kHz – 80 dB
V
CM
Input common-mode voltage range 0 1.4 V
(1) Per channel output power
(2) A-weighted
AV
AV
16 Ω
PO= 10 mW into 16 Ω , f = 1 kHz 0.02%
(2)
PO= 20 mW into 32 Ω , f = 1 kHz 0.01%
200 mVpp ripple, f = 217 Hz 80 100
200 mVpp ripple, f = 4 kHz 90
PO= 0.5 mW into 32 Ω , f = 1 kHz 315
PO= 15 mW into 32 Ω , f = 1 kHz 1260
Threshold 165
Hysteresis 35
40 kHz, 1.8 V
13 MHz, 1.8 V
= 2.7V, THD = 1%, f = 1 kHz 26
DD
= 2.7V, THD = 10%, f = 1 kHz 32
DD
= 2.7V, THD = 1%, f = 1 kHz, RL=
DD
= 2.5 V to 5.5 V, inputs grounded – 0.5 0 0.5 mV
DD
= 1 V
OUT
, GAIN = 4 dB, no load 105 dB
RMS
signal max 8.5 k Ω
PEAK
signal max 600 Ω
PEAK
signal max 400 Ω
PEAK
25
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RMS
6 Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6140A2
VDD − Supply Voltage − V
0
1
2
3
4
5
6
7
8
9
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Quiescent Supply Current − mA
G001
PO − Output Power − W
f = 1 kHz
RL = 16 Ω
VDD = 3.6 V
THD+N − T otal Harmonic Distortion + Noise − %
0.0001 0.001 0.01 0.1
100
1
0.1
0.01
G002
10
Out of Phase
In Phase
PO − Output Power − W
f = 1 kHz
RL = 16 Ω
THD+N − T otal Harmonic Distortion + Noise − %
0.0001 0.001 0.01 0.1
100
1
0.1
0.01
G003
10
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
PO − Output Power − W
f = 1 kHz
RL = 32 Ω
THD+N − T otal Harmonic Distortion + Noise − %
0.0001 0.001 0.01 0.1
100
1
0.1
0.01
G004
10
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
f − Frequency − Hz
RL = 16 Ω
VDD = 2.5 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G005
10k
PO = 1 mW
per Channel
PO = 10 mW
per Channel
PO = 4 mW
per Channel
f − Frequency − Hz
RL = 32 Ω
VDD = 2.5 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G006
10k
PO = 1 mW
per Channel
PO = 4 mW
per Channel
PO = 10 mW
per Channel
TPA6140A2
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.................................................................................................................................................................................................. SLOS598 – MARCH 2009
TYPICAL CHARACTERISTICS
TA= 25 ° C, AV
(V
) = 3.6 V, GAIN = 0 dB, C
DD
DD
= C
HPVDD
HPVSS
= 2.2 µ F, C
= C
INPUT
= 1 µ F, Outputs out of phase
FLYING
QUIESCENT SUPPLY CURRENT TOTAL HARMONIC DISTORTION + NOISE
vs vs
SUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
FREQUENCY FREQUENCY
Copyright © 2009, Texas Instruments Incorporated 7
Figure 7. Figure 8.
vs vs
Product Folder Link(s): TPA6140A2
f − Frequency − Hz
RL = 16 Ω
VDD = 3.6 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G007
10k
PO = 1 mW
per Channel
PO = 10 mW
per Channel
PO = 15 mW
per Channel
f − Frequency − Hz
RL = 32 Ω
VDD = 3.6 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G008
10k
PO = 1 mW
per Channel
PO = 20 mW
per Channel
PO = 10 mW
per Channel
f − Frequency − Hz
RL = 16 Ω
VDD = 5 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G009
10k
PO = 1 mW
per Channel
PO = 15 mW
per Channel
PO = 10 mW
per Channel
f − Frequency − Hz
RL = 32 Ω
VDD = 5 V
THD+N − T otal Harmonic Distortion + Noise − %
20 100 1k 20k
1
0.1
0.01
0.001
G010
10k
PO = 1 mW
per Channel
PO = 20 mW
per Channel
PO = 10 mW
per Channel
VDD − Supply Voltage − V
0
10
20
30
40
50
60
2.5 3.0 3.5 4.0 4.5 5.0 5.5
P
O
− Output Power per Channel − mW
G011
THD+N = 1%
THD+N = 10%
RL = 16 Ω
In Phase
VDD − Supply Voltage − V
0
10
20
30
40
50
60
2.5 3.0 3.5 4.0 4.5 5.0 5.5
P
O
− Output Power per Channel − mW
G012
THD+N = 1%
THD+N = 10%
RL = 32 Ω
In Phase
TPA6140A2
SLOS598 – MARCH 2009 ..................................................................................................................................................................................................
TA= 25 ° C, AV
TYPICAL CHARACTERISTICS (continued)
(V
) = 3.6 V, GAIN = 0 dB, C
DD
DD
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
= C
HPVDD
HPVSS
= 2.2 µ F, C
= C
INPUT
= 1 µ F, Outputs out of phase
FLYING
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Figure 11. Figure 12.
OUTPUT POWER PER CHANNEL OUTPUT POWER PER CHANNEL
SUPPLY VOLTAGE SUPPLY VOLTAGE
8 Copyright © 2009, Texas Instruments Incorporated
Figure 13. Figure 14.
vs vs
Product Folder Link(s): TPA6140A2
RL − Load Resistance − Ω
0
5
10
15
20
25
30
35
40
45
50
THD+N = 1%
Out of Phase
P
O
− Output Power − mW
10 100 1k
G013
VDD = 5 V
VDD = 2.5 V
VDD = 3.6 V
RL − Load Resistance − Ω
0
5
10
15
20
25
30
35
40
45
50
THD+N = 1%
In Phase
P
O
− Output Power − mW
10 100 1k
G014
VDD = 5 V
VDD = 2.5 V
VDD = 3.6 V
f − Frequency − Hz
−120
−100
−80
−60
−40
−20
0
RL = 32 Ω
Supply Ripple = 0.2 V
pp
Sine Wave
20 100 1k 20k
G016
10k
k
SVR
− Supply Ripple Rejection Ratio− dB
VDD = 2.5 V
VDD = 5 V
VDD = 3.6 V
f − Frequency − Hz
−120
−100
−80
−60
−40
−20
0
RL = 16 Ω
Supply Ripple = 0.2 V
pp
Sine Wave
20 100 1k 20k
G015
10k
k
SVR
− Supply Ripple Rejection Ratio − dB
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
PO − T otal Output Power − mW
f = 1 kHz
RL = 16 Ω
0.001 0.01 100
100
10
1
G017
100.1
VDD = 2.5 V
1
VDD = 3.6 V
VDD = 5 V
I
DD
− Supply Current − mA
PO − T otal Output Power − mW
f = 1 kHz
RL = 32 Ω
0.001 0.01 100
100
10
1
G018
100.1
VDD = 2.5 V
1
VDD = 3.6 V
VDD = 5 V
I
DD
− Supply Current − mA
TPA6140A2
www.ti.com
TA= 25 ° C, AV
.................................................................................................................................................................................................. SLOS598 – MARCH 2009
TYPICAL CHARACTERISTICS (continued)
(V
) = 3.6 V, GAIN = 0 dB, C
DD
DD
OUTPUT POWER OUTPUT POWER
vs vs
LOAD RESISTANCE LOAD RESISTANCE
Figure 15. Figure 16.
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
= C
HPVDD
HPVSS
= 2.2 µ F, C
= C
INPUT
= 1 µ F, Outputs out of phase
FLYING
Figure 17. Figure 18.
SUPPLY CURRENT SUPPLY CURRENT
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
Copyright © 2009, Texas Instruments Incorporated 9
Figure 19. Figure 20.
vs vs
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