TEXAS INSTRUMENTS TPA6012A4 Technical data

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S001

APPLICATIONCIRCUIT

PGND

ROUT−

RIN–

RIN+

LIN–

LIN+

LOUT−

ROUT+

SE/BTL

VOLUME

AGND

BYPASS

FADE

SHUTDOWN

LOUT+

PGND

0.47 Fm

RightNegative

Differential

InputSignal

PowerSupply

RightPositive

Differential

InputSignal

LeftNegative

Differential

InputSignal

LeftPositive

Differential

InputSignal

PowerSupply

100kW

InFromDAC

Potentiometer

(DCVoltage)

0.47 F

(BYP)

SystemControl

330 FOm

Right Speaker

Left Speaker

Headphones

1kW

10 FSm

0.47 Fm

4,10,19,20,22

DCVOLUMECONTROL

Volume[Pin21] − V

Gain − dB

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

−90

−80

−70

−60

−50

−40

−30

−20

−10

VolumeUp VolumeDown

VDD=5.0V BTLOutput

R =NoLoad

GAIN(BTL)

VOLUMEVOLTAGE

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3-W STEREO AUDIO POWER AMPLIFIER

WITH ADVANCED DC VOLUME CONTROL

Check for Samples :TPA6012A4

FEATURES

• Advanced 32 Steps DC Volume Control – Steps From –40 dB to 18 dB – Fade Mode – –85-dB Mute Mode

• 3 W Into 3-Ω Speakers

• Differential Inputs

• Headphone Mode

• Pin-to-Pin Compatible With TPA6011A4 and TPA6013A4

• 24-Pin PowerPAD™ Package (PWP)

APPLICATIONS

• LCD Monitors

• Notebook PC

• All-in-One PC

TPA6012A4

SLOS636 –OCTOBER 2009

DESCRIPTION

The TPA6012A4 is a stereo audio power amplifier that drives 3 W/channel of continuous RMS power into a 3-Ω load. Advanced dc volume control minimizes external components and allows BTL (speaker) volume control and SE (headphone) volume control. LCD monitors and notebook benefit from the integrated feature set that minimizes external components without sacrificing functionality.

To simplify design, the speaker volume level is adjusted by applying a dc voltage to the VOLUME terminal. To ensure a smooth transition between active and shutdown modes, a fade mode ramps the volume up and down.

The 24-pin PowerPAD™ package (PWP) enchances thermal performance.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Application Circuit and DC Volume Control

TPA6012A4

SLOS636 –OCTOBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS

–40°C to 85°C TPA6012A4PWP

PACKAGE

24-PIN TSSOP (PWP)

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Supply voltage, VDD, PV

Input voltage, RIN+, RIN–, LIN+,LIN– –0.3 V to VDD+0.3 V Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range –40°C to 85°C Operating junction temperature range –40°C to 150°C Storage temperature range –65°C to 85°C

DISSIPATION RATING TABLE

PACKAGE

PWP 2.7 mW 21.8 mW/°C 1.7 W 1.4 W

(1) All characterization is done using an external heatsink with θSA= 25°C/W. The resulting derating factor

is 22.2 mW/°C.

TA= 25°C DERATING FACTOR TA= 70°C TA= 85°C

POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING

(1)

UNIT

–0.3 V to 6 V

(1)

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TPA6012A4

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RECOMMENDED OPERATING CONDITIONS

Supply voltage, VDD, PV

High-level input voltage

Low-level input voltage

SE/BTL, FADE 0.8 x V SHUTDOWN 2 V SE/BTL, FADE 0.6 x V SHUTDOWN 0.8 V

Operating free-air temperature –40 85 °C

ELECTRICAL CHARACTERISTICS

TA= 25°C, VDD= PVDD= 5.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

| VOO| Output offset voltage (measured differentially)

PSRR Power supply rejection ratio VDD= PVDD= 4 V to 5.5 V, Gain = 0 dB –80 dB | IIH| 1 µA

| IIL| VDD= PVDD= 5 V, VI= 0 V 1 µA

DD(SD)

High-level input current (SE/BTL, FADE, VDD= PVDD= 5.5 V, SHUTDOWN, VOLUME) VI= VDD= PV

Low-level input current (SE/BTL, FADE, SHUTDOWN, VOLUME)

Supply current, no load mA

Supply current, max power into a 3-Ω load SHUTDOWN = 2 V, RL= 3 Ω, 1.5 A

Supply current, shutdown mode SHUTDOWN = 0 V 10 25 µA

VDD= 5.5 V, Gain = 0 dB, SE/BTL = 0 V 2 30 mV VDD= 5.5 V, Gain = 18 dB, SE/BTL = 0 V 2.6 50 mV

VDD= PVDD= 5 V, SE/BTL = 0 V, SHUTDOWN = 2 V

VDD= PVDD= 5 V, SE/BTL = 5 V, SHUTDOWN = 2 V

VDD= 5 V = PVDD, SE/BTL = 0 V, PO= 2 W, stereo

SLOS636 –OCTOBER 2009

MIN MAX UNIT

4 5.5 V

6.7 9

4.5 6

RMS

OPERATING CHARACTERISTICS

TA= 25°C, VDD= PVDD= 5 V, RL= 3 Ω, Gain = 6 dB, Stereo (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

THD = 1%, f = 1 kHz, RL= 16 Ω (SE) 195 mW

Output power

THD+N Total harmonic distortion + noise PO= 0.9 W, RL= 8 Ω (BTL), f = 20 Hz to 20 kHz <0.1%

(Bypass)

High-level output voltage RL= 8 Ω, Measured between output and VDD= 5.5 V 700 mV Low-level output voltage 400 mV Bypass voltage (Nominally VDD/2) Measured at pin 17, No load, VDD= 5.5 V 2.65 2.75 2.85 V

Supply ripple rejection ratio f = 1 kHz, Gain = 0 dB, C

Crosstalk

Noise output voltage BTL 36 µV

Input impedance (see Figure 20) VOLUME = 5 V 12 kΩ

THD = 10%, f = 1 kHz, RL= 16 Ω (SE) 235 mW THD = 1%, f = 1 kHz, RL= 3 Ω (BTL) 2.0 THD = 10%, f = 1 kHz, VDD= 5.5 V, RL=3 Ω (BTL) 3.2

PO= 0.1 W, RL= 16 Ω (SE), f = 20 Hz to 20 kHz 0.03%

RL= 8 Ω, Measured between output and GND, VDD= 5.5 V

(BYP)

= 1 µF

BTL (4Ω) –66 dB SE (32Ω) –60 dB BTL 110 dB SE 102 dB

f = 20 Hz to 20 kHz, Gain = 0 dB, C

= 1 µF

(BYP)

RMS

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PWP Package

(TopView)

P0110-02

PGND

ROUT−

NC RIN+ RIN–

LIN–

LIN+

LOUT−

ROUT+

SE/BTL

NC VOLUME NC NC

AGND BYPASS

FADE SHUTDOWN LOUT+ PGND

TPA6012A4

SLOS636 –OCTOBER 2009

Terminal Functions

TERMINAL

NAME NO.

BYPASS 17 I Tap to voltage divider for internal mid-supply bias generator used for analog reference FADE 16 I AGND 18 – Analog power supply ground

LIN- 8 I Left channel negative input for fully differential input. LIN+ 9 I Left channel positive input for fully differential input. LOUT– 12 O Left channel negative audio output LOUT+ 14 O Left channel positive audio output. NC 4, – No connection

PGND 1, 13 – Power ground PV

RIN+ 5 I Right channel positive input for fully differential input. RIN– 6 I Right channel negative input for fully differential input. ROUT– 2 O Right channel negative audio output ROUT+ 24 O Right channel positive audio output

SE/BTL 23 I SHUTDOWN 15 I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal

DC VOLUME 21 I Terminal for dc volume control. DC voltage range is 0 to VDD.

I/O DESCRIPTION

Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high is placed on this terminal.

10, 19, 20, 22

3, 11 – Supply voltage terminal for power stage

Output control. When this terminal is high, SE outputs are selected. When this terminal is low, BTL outputs are selected.

7 – Supply voltage terminal

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Power

Management

32-Step Volume Control

Output Control

RIN+

ROUT+

SHUTDOWN

ROUT-

PGND V

BYPASS

AGND

LOUT-

LOUT+

RIN-

VOLUME

FADE

BYP

SE/BTL

BYP

SE/BTL

LIN-

LIN+

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TPA6012A4

SLOS636 –OCTOBER 2009

FUNCTIONAL BLOCK DIAGRAM

NOTE: All resistor wipers are adjusted with 32 step volume control.

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TPA6012A4

SLOS636 –OCTOBER 2009

(1) For other values of VDD, scale the voltage values in the table by a factor of VDD/5. (2) Tested in production.

Table 1. DC Volume Control (BTL Mode, VDD= 5 V)

VOLUME (PIN 21)

FROM (V) TO (V)

0.00 0.26 –85

0.33 0.37 –40

0.44 0.48 –34

0.56 0.59 –31

0.67 0.70 –28

0.78 0.82 –25

0.89 0.93 –22

1.01 1.04 –19

1.12 1.16 –16

1.23 1.27 –13

1.35 1.38 –10

1.46 1.49 –7

1.57 1.60 –4

1.68 1.72 –2

1.79 1.83 0

1.91 1.94 2

2.02 2.06 4

2.13 2.17 6

2.25 2.28 8

2.36 2.39 10

2.47 2.50 11

2.58 2.61 12

2.70 2.73 13

2.81 2.83 14

2.92 2.95 14.5

3.04 3.06 15

3.15 3.17 15.5

3.26 3.29 16

3.38 3.40 16.5

3.49 3.51 17

3.60 3.63 17.5

3.71 5.00 18

GAIN OF AMPLIFIER

(1)

(Typ)

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(2)

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Table 2. DC Volume Control (SE Mode, VDD= 5 V)

VOLUME (PIN 21)

FROM (V) TO (V)

0.00 0.26 –85

0.33 0.37 –46

0.44 0.48 –40

0.56 0.59 –37

0.67 0.70 –34

0.78 0.82 –31

0.89 0.93 –28

1.01 1.04 –25

1.12 1.16 –22

1.23 1.27 –19

1.35 1.38 –16

1.46 1.49 –13

1.57 1.60 –10

1.68 1.72 –8

1.79 1.83 –6

1.91 1.94 –4

2.02 2.06 -2

2.13 2.17 0

2.25 2.28 2

2.36 2.39 4

2.47 2.50 5

2.58 2.61 6

2.70 2.73 7

2.81 2.83 8

2.92 2.95 8.5

3.04 3.06 9

3.15 3.17 9.5

3.26 3.29 10

3.38 3.40 10.5

3.49 3.51 11

3.60 3.63 11.5

3.71 5.00 12

(1) For other values of VDD, scale the voltage values in the table by a factor of VDD/5. (2) Tested in production. Remaining gain steps are specified by design.

GAIN OF AMPLIFIER

TPA6012A4

SLOS636 –OCTOBER 2009

(1)

(Typ)

(2)

Product Folder Link(s) :TPA6012A4

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

PO = 500 mW PO = 1 W PO = 1.5 W

VDD = 5.0 V RL = 3 Ω BTL Output Gain = 6 dB

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

PO = 250 mW PO = 1 W PO = 1.5 W

VDD = 5.0 V RL = 4 Ω BTL Output Gain = 6 dB

TPA6012A4

SLOS636 –OCTOBER 2009

TYPICAL CHARACTERISTICS

Test conditions (unless otherwise noted) for typical operating performance:

VDD= 5.0 V, CIN= 1 µF, C

Table of Graphs

Gain (BTL) vs Volume voltage Figure 1

THD+N Total harmonic distortion plus noise (BTL)

THD+N Total harmonic distortion plus noise (SE) vs Output power Figure 10

Total power dissipation (BTL) vs Total output power Figure 12 Total power dissipation (SE) vs Total output power Figure 13 Crosstalk (BTL) vs Frequency Figure 14

Crosstalk (SE) vs Frequency Figure 15 PSRR Power supply rejection ratio (BTL) vs Frequency Figure 16 PSRR Power supply rejection ratio (SE) vs Frequency Figure 17 I

Supply current (BTL) vs Total output power Figure 18

Supply current (SE) vs Total output power Figure 19

Input impedance vs Gain Figure 20

vs Frequency Figure 2, Figure 3, Figure 4 vs Output power Figure 7, Figure 8, Figure 9 vs Frequency Figure 5, Figure 6

vs Output voltage Figure 11

= 1 µF, TA= 27°C, SHUTDOWN = V

BYPASS

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TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)

vs vs

FREQUENCY FREQUENCY

Figure 2. Figure 3.

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f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

PO = 250 mW PO = 500 mW PO = 900 mW

VDD = 5.0 V RL = 8 Ω BTL Output Gain = 6 dB

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

Po = 10 mW Po = 40 mW Po = 80 mW

VDD = 5.0 V RL = 32 Ω SE Output Gain = 0 dB

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

VO = 500 mV

RMS

VO = 1.0 V

RMS

VO = 1.75 V

RMS

VDD = 5.0 V RL = 10 kΩ SE Output Gain = 0 dB

PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

1m 10m 100m 1 4

0.01

0.1

100

VDD = 4.5 V VDD = 5.0 V VDD = 5.5 V

RL = 3 Ω BTL Output Gain = 6 dB

PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

1m 10m 100m 1 3

0.01

0.1

100

VDD = 4.5 V VDD = 5.0 V VDD = 5.5 V

RL = 4 Ω BTL Output Gain = 6 dB

PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

1m 10m 100m 1 2

0.01

0.1

100

VDD = 4.5 V VDD = 5.0 V VDD = 5.5 V

RL = 8 Ω BTL Output Gain = 6 dB

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TPA6012A4

SLOS636 –OCTOBER 2009

TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (SE)

vs vs

FREQUENCY FREQUENCY

Figure 4. Figure 5.

TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (BTL)

vs vs

FREQUENCY OUTPUT POWER

Figure 6. Figure 7.

TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)

OUTPUT POWER OUTPUT POWER

Figure 8. Figure 9.

vs vs

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PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

100u 1m 10m 100m 300m

0.01

0.1

100

RL = 16 Ω RL = 32 Ω

VDD = 5.0 V SE Output Gain = 0 dB

VO − Output Voltage − V

RMS

THD+N − Total Harmonic Distortion + Noise − %

0.0 500.0m 1.0 1.5 2.0

0.001

0.01

0.1

100

VDD = 5.0 V RL = 10 kΩ SE Output Gain = 0 dB

PO − Total Output Power − W

− Total Power Dissipation − W

0 100m 200m 300m 400m 500m

25m

50m

75m

100m

125m

150m

175m

200m

RL = 16 Ω RL = 32 Ω

VDD = 5.0 V SE Output Gain = 0 dB

PO − Total Output Power − W

− Total Power Dissipation − W

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

RL = 3 Ω RL = 4 Ω RL = 8 Ω

VDD = 5.0 V BTL Output Gain = 6 dB

f − Frequency − Hz

Crosstalk − dB

20 100 1k 10k 20k

−140

−120

−100

−80

−60

−40

−20

RL = 4 Ω PO = 1 W BTL Output Gain = 6 dB

f − Frequency − Hz

Crosstalk − dB

20 100 1k 10k 20k

−140

−120

−100

−80

−60

−40

−20

RL = 32 Ω PO = 50 mW SE Output Gain = 0 dB

TPA6012A4

SLOS636 –OCTOBER 2009

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TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (SE)

vs vs

OUTPUT POWER OUTPUT VOLTAGE

Figure 10. Figure 11.

TOTAL POWER DISSIPATION (BTL) TOTAL POWER DISSIPATION (SE)

vs vs

TOTAL OUTPUT POWER TOTAL OUTPUT POWER

Figure 12. Figure 13.

CROSSTALK (BTL) CROSSTALK (SE)

vs vs

FREQUENCY FREQUENCY

Figure 14. Figure 15.

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f − Frequency − Hz

PSRR − Power Supply Rejection Ratio − dB

20 100 1k 10k 20k

−80

−60

−40

−20

Gain = 6 dB Gain = 18 dB

VDD = 5.0 V RL = 4 Ω BTL Output Supply Ripple = 0.2 Vpp Sine Wave

f − Frequency − Hz

PSRR − Power Supply Rejection Ratio − dB

20 100 1k 10k 20k

−80

−60

−40

−20

Gain = 0 dB Gain = 12 dB

VDD = 5.0 V RL = 32 Ω SE Output Supply Ripple = 0.2 Vpp Sine Wave

PO − Total Output Power − W

− Supply Current − A

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

RL = 3 Ω RL = 4 Ω RL = 8 Ω

VDD = 5.0 V BTL Output Gain = 6 dB

PO − Total Output Power − W

− Supply Current − A

0 100m 200m 300m 400m 500m

25m

50m

75m

100m

125m

RL = 16 Ω RL = 32 Ω

VDD = 5.0 V SE Output Gain = 0 dB

Gain − dB

Input Impedance − Ω

−40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20

20k

40k

60k

80k

100k

120k

Differential Single−Ended

VDD = 5.0 V RL = No Load

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TPA6012A4

SLOS636 –OCTOBER 2009

POWER SUPPLY REJECTION RATIO (BTL) POWER SUPPLY REJECTION RATIO (SE)

vs vs

FREQUENCY FREQUENCY

Figure 16. Figure 17.

SUPPLY CURRENT (BTL) SUPPLY CURRENT (SE)

vs vs

TOTAL OUTPUT POWER TOTAL OUTPUT POWER

Figure 18. Figure 19.

INPUT IMPEDANCE

GAIN

Figure 20.

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PGND

ROUT–

RIN+

RIN–

LIN–

LIN+

LOUT-

ROUT+

SE/BTL

VOLUME

AGND

BYPASS

FADE

SHUTDOWN

LOUT+

PGND

4,19,20,22

Right

AudioSource

Left

AudioSource

PowerSupply

100kW

InFromDAC

Potentiometer

(DCVoltage)

System Control

Right Speaker

Left Speaker

Headphones

1kW

330 FOm

0.47 F

(BYP)

0.47 Fm

10 FSm

TPA6012A4

SLOS636 –OCTOBER 2009

APPLICATION INFORMATION

SELECTION OF COMPONENTS

Figure 21 and Figure 22 are schematic diagrams of typical LCD monitor application circuits.

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A. A 0.47-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise

signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.

Figure 21. Typical TPA6012A4 Application Circuit Using Single-Ended Inputs

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PGND

ROUT–

RIN+

RIN–

LIN–

LIN+

LOUT–

ROUT+

SE/BTL

VOLUME

AGND

BYPASS

FADE

SHUTDOWN

LOUT+

PGND

4,10,19,20,22

RightPositive

DifferentialInputSignal

LeftNegative

DifferentialInputSignal

RightNegative

DifferentialInputSignal

LeftPositive

DifferentialInputSignal

PowerSupply

100kW

330 FOm

0.47 Fm

10 FSm

0.47 F

(BYP)

InFromDAC

Potentiometer

(DCVoltage)

System Control

Right Speaker

Left Speaker

Headphones

1kW

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TPA6012A4

SLOS636 –OCTOBER 2009

A. A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise

SE/BTL OPERATION

The ability of the TPA6012A4 to easily switch between BTL and SE modes is one of its most important cost saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the TPA6012A4, two separate amplifiers drive OUT+ and OUT–. The SE/BTL input controls the operation of the follower amplifier that drives LOUT– and ROUT–. When SE/BTL is held low, the amplifier is on and the TPA6012A4 is in the BTL mode. When SE/BTL is held high, the OUT– amplifiers are in a high output impedance state, which configures the TPA6012A4 as an SE driver from LOUT+ and ROUT+. IDDis reduced by approximately one-third in SE mode. Control of the SE/BTL input can be from a logic-level CMOS source or, more typically, from a resistor divider network as shown in Figure 23. The trip level for the SE/BTL input can be found in the recommended operating conditions table.

signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.

Figure 22. Typical TPA6012A4 Application Circuit Using Differential Inputs

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SE/BTL

ROUT+ 24

RIN+

6 RIN–

ROUT– 2

1kW

330 Fm

100kW

Bypass

LOUT+

TPA6012A4

SLOS636 –OCTOBER 2009

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Figure 23. TPA6012A4 Resistor Divider Network Circuit

Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ resistor is disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT– amplifier is shut down causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output capacitor, Co, into the headphone jack.

SHUTDOWN MODES

The TPA6012A4 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, IDD= 20 µA. SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable.

Table 3. SE/BTL and Shutdown Functions

INPUTS

(1) Inputs should never be left unconnected.

(1)

SE/BTL SHUTDOWN OUTPUT

X Low Mute Low High BTL High High SE

AMPLIFIER STATE

FADE OPERATION

For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.

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ROUT+

Device Shutdown

ROUT+

Device Shutdown

TPA6012A4

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When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the recommended operating conditions table.

When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock frequency of 58 Hz, this equates to 34 ms (1/29 Hz) per step. The gain steps down until the lowest gain step is reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown. For example, if the amplifier is in the highest gain mode of 18 dB, the time it takes to ramp down the channel gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.

After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a

0.47-µF capacitor that is used in the application diagram in Figure 21, the time is approximately 500 ms. This time scales linearly with the value of bypass capacitor. For example, if a 1-µF capacitor is used for bypass, the time period to discharge the capacitor to ground is twice that of the 0.47-µF capacitor, or 1 second. Figure 22 below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode. The gain is set to the highest level and the output is at VDDwhen the amplifier is shut down.

When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of VDD/2, the gain increases from the lowest gain level to the gain level set by the dc voltage applied to the VOLUME pin.

In the fade-off mode, the output of the amplifier immediately drops to VDD/2 and the bypass capacitor begins a smooth discharge to ground. When shutdown is released, the bypass capacitor charges up to VDD/2 and the channel gain returns immediately to the value on the VOLUME terminal. Figure 23 below is a waveform captured at the output during the shutdown sequence when the part is in the fade-off mode. The gain is set to the highest level, and the output is at VDDwhen the amplifier is shut down.

The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not change the power-up sequence. Upon a power-up condition, the TPA6012A4 begins in the lowest gain setting and steps up every 2 clock cycles until the final value is reached as determined by the dc voltage applied to the VOLUME pin.

SLOS636 –OCTOBER 2009

Figure 24. Shutdown Sequence in the Fade-on Figure 25. Shutdown Sequence in the Fade-off

Mode Mode

VOLUME OPERATION

The VOLUME pin controls the BTL volume when driving speakers, and the SE volume when driving headphones. This pin is controlled with a dc voltage, which should not exceed VDD.

Product Folder Link(s) :TPA6012A4

2.702.61 2.73 2.81

BTL

Gain-dB

VoltageonVOLUMEPin-V

Input Signal

TPA6012A4

SLOS636 –OCTOBER 2009

The output volume increases in discrete steps as the dc voltage increases and decreases in discrete steps as the dc voltage decreases. There are a total of 32 discrete gain steps of the amplifier and range from –85 dB to 18 dB for BTL operation and –85 dB to 12 dB for SE operation.

Table 1 and Table 2 show a range of voltages for each gain step. There is a gap in the voltage between each

gain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. If a potentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer is turned in one direction and decreases as it is turned back the other direction. The trip point, where the gain actually changes, is different depending on whether the voltage is increased or decreased as a result of the hysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensure that the desired gain is achieved.

A pictorial representation of the typical volume control can be found in Figure 26. The graph focuses on three gain steps with the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about each gain step.

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Figure 26. DC Volume Control Operation

INPUT RESISTANCE

Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or cutoff frequency also changes by over six times.

Figure 27. Resistor on Input for Cut-Off Frequency

The input resistance at each gain setting is given in Figure 20. The –3-dB frequency can be calculated using Equation 1.

Product Folder Link(s) :TPA6012A4

*3 dB

2p CR

c(highpass)

2p RiC

−3 dB

2p Rif

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TPA6012A4

SLOS636 –OCTOBER 2009

(1)

INPUT CAPACITOR, C

In the typical application an input capacitor CIis required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CIand the input impedance of the amplifier RIform a high-pass filter with the corner frequency determined in Equation 2.

(2)

The value of CIis important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RIis 70 kΩ and the specification calls for a flat-bass response down to 40 Hz.

Equation 2 is reconfigured as Equation 3.

(3)

In this example, CIis 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 µF. A further consideration for this capacitor is the leakage path from the input source through the input network CIand the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

POWER SUPPLY DECOUPLING, C

(S)

The TPA6012A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VDDlead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended.

MIDRAIL BYPASS CAPACITOR, C

The midrail bypass capacitor C start-up or recovery from shutdown mode, C

(BYP)

is the most critical capacitor and serves several important functions. During

determines the rate at which the amplifier starts up. The second

(BYP)

function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD+N.

Bypass capacitor C the best THD and noise performance. For the best pop performance, choose a value for C greater than the value chosen for CI. This ensures that the input capacitors are charged up to the midrail voltage before C

is fully charged to the midrail voltage.

(BYP)

values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for

(BYP)

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that is equal to or

(BYP)

c(high)

2p RLC

(C)

−3 dB

TPA6012A4

SLOS636 –OCTOBER 2009

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OUTPUT COUPLING CAPACITOR, C

In the typical single-supply SE configuration, an output coupling capacitor C

(C)

is required to block the dc bias at

(C)

the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.

(4)

The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives the low-frequency corner higher, degrading the bass response. Large values of C frequencies into the load. Consider the example where a C

of 330 µF is chosen and loads vary from 4 Ω, 8 Ω,

(C)

are required to pass low

(C)

32 Ω , 10 kΩ, and 47 kΩ. Table 4 summarizes the frequency response characteristics of each configuration.

Table 4. Common Load Impedances vs Low Frequency

Output Characteristics in SE Mode

4 Ω 330 µF 120 Hz 8 Ω 330 µF 60 Hz

32 Ω 330 µF 15 Hz 10,000 Ω 330 µF 0.05 Hz 47,000 Ω 330 µF 0.01 Hz

(C)

LOWEST

FREQUENCY

As Table 4 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate, headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

BRIDGE-TIED LOAD vs SINGLE-ENDED LOAD

Figure 28 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6012A4 BTL amplifier

consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differential drive configuration, but, initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Plugging 2 x V where voltage is squared, yields 4x the output power from the same supply rail and load impedance (see

Equation 5).

Product Folder Link(s) :TPA6012A4

into the power equation,

O(PP)

Power +

(rms)

O(PP)

2 2

2x V

O(PP)

-V

O(PP)

(c)

2p RLC

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TPA6012A4

SLOS636 –OCTOBER 2009

(5)

Figure 28. Bridge-Tied Load Configuration

In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the single-supply SE configuration shown in Figure 29. A coupling capacitor is required to block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance and is calculated with Equation 6.

(6)

For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor.

Product Folder Link(s) :TPA6012A4

(C)

O(PP)

-3 dB

(LRMS)

DD(avg)

TPA6012A4

SLOS636 –OCTOBER 2009

Figure 29. Single-Ended Configuration and Frequency Response

Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4x the output power of the SE configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal considerations section.

SINGLE-ENDED OPERATION

In SE mode (see Figure 29), the load is driven from the primary amplifier output for each channel (OUT+). The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative

outputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.

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BTL AMPLIFIER EFFICIENCY

Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that varies inversely to output power. The second component is due to the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power dissipation of the amplifier.

An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 30).

Figure 30. Voltage and Current Waveforms for BTL Amplifiers

Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency.

Product Folder Link(s) :TPA6012A4

Efficiency of a BTL amplifier +

SUP

Where:

VLrms

, andV

LRMS

, therefore, P

and

SUP

+ VDDIDDavg

and

IDDavg +

sin(t) dt

[cos(t)]

0 +

p R

Therefore,

SUP

2 VDDV

p R

Efficiency of a BTL amplifier +

2 R

2 VDDV

p R

p V

4 V

PL = Power delivered to load P

SUP

= Power drawn from power supply

LRMS

= RMS voltage on BTL load

RL = Load resistance

VP+ 2 PLR

BTL

p 2 PLR

4 V

Where:

Therefore,

VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage

BTL

= Efficiency of a BTL amplifier

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substituting PLand P

into Equation 7,

SUP

TPA6012A4

SLOS636 –OCTOBER 2009

(7)

Table 5 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency

of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, we get an efficiency of 0.628. Total output power is 2-W. Thus the maximum draw on the power supply is almost 3.25 W.

OUTPUT POWER EFFICIENCY PEAK VOLTAGE INTERNAL DISSIPATION

(1) High peak voltages cause the THD to increase.

Table 5. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems

(W) (%) (V) (W)

0.25 31.4 2.00 0.55

0.50 44.4 2.83 0.62

1.00 62.8 4.00 0.59

1.25 70.2 4.47

Product Folder Link(s) :TPA6012A4

(1)

(8)

0.53

P =10Log

=10Log

ref

3W 1W

=5dB

P =10 xP

W ref

PdB/10

TPA6012A4

SLOS636 –OCTOBER 2009

A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation 8, VDDis in the denominator. This indicates that as VDDgoes down, efficiency goes up.

CREST FACTOR AND THERMAL CONSIDERATIONS

Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal dissipated power at the average output power level must be used. From the data sheet graph (Figure 5.), one can see that when the TPA6012A4 is operating from a 5-V supply into a 4-Ω speaker at 1% THD, that output power is 1.5-W so maximum instantaneous output power is 3-W. Use equation 9 to convert watts to dB.

Subtracting the headroom restriction to obtain the average listening level without distortion yields:

5 dB - 15 dB = –10 dB (15-dB crest factor) 5 dB - 12 dB = –7 dB (12-dB crest factor) 5 dB - 9 dB = –4 dB (9-dB crest factor) 5 dB - 6 dB = -1 dB (6-dB crest factor) 5 dB - 3 dB = 2 dB (3-dB crest factor)

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(9)

To convert dB back into watts use equation 10.

(10)

= 48 mW (18-dB crest factor) = 95 mW (15-dB crest factor) = 190 mW (12-dB crest factor) = 380 mW (9-dB crest factor) = 750 mW (6-dB crest factor) = 1500 mW (3-dB crest factor)

This is valuable information to consider when attempting to estimate the heat dissipation requirements for the amplifier system. Comparing the worst case, which is 1.5 W of continuous power output with a 3-dB crest factor, against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system. Using the power dissipation curves for a 5-V, 4-Ω system, the internal dissipation in the TPA6012A4 and maximum ambient temperatures is shown in Table 6.

Product Folder Link(s) :TPA6012A4

D(max)

2 DD

=45 C/W

DeratingFactor

0.0222

Max= T P

J JA D

Max- q

=150-45(0.6x2)=96 C(15-dBcrestfactor)

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SLOS636 –OCTOBER 2009

Table 6. TPA6012A4 Power Rating, 5-V, 4-Ω Stereo

PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT

(W) (W/Channel) TEMPERATURE

3 1500 mW (3 dB) 1.26 37°C 3 750 mW (6 dB) 1.20 42°C 3 380 mW (9 dB) 1.00 59°C 3 190 mW (12 dB) 0.79 79°C 3 95 mW (15 dB) 0.60 96°C 3 48 mW (18 dB) 0.44 110°C

(1) Package limited to 85°C ambient.

AVERAGE OUTPUT POWER

Table 7. TPA6012A4 Power Rating, 5-V, 8-Ω Stereo

PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT

(W) (W/Channel) TEMPERATURE

2.2 1100 mW (3-dB crest factor) 0.57 99°C

2.2 876 mW (4-dB crest factor) 0.61 95°C

2.2 440 mW (7-dB crest factor) 0.62 95°C

2.2 220 mW (10-dB crest factor) 0.53 103°C

(1) Package limited to 85°C ambient.

The maximum dissipated power (P a 4-Ω load. As a result, this simple formula for calculating P

AVERAGE OUTPUT POWER

) is reached at a much lower output power level for an 8-Ω load than for

D(max)

may be used for an 8-Ω application.

D(max)

TPA6012A4

(1)

(1) (1) (1)

(1)

(11)

However, in the case of a 4-Ω load, the P The amplifier may therefore be operated at a higher ambient temperature than required by the P

occurs at a point well above the normal operating power level.

D(max)

formula for

a 4-Ω load. The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor

for the N package with an external heatsink is shown in the dissipation rating table. Use Equation 12 to convert this to θ

JA.

(12)

To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per channel, so the dissipated power needs to be doubled for two channel operation. Given θJA, the maximum allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be calculated using Equation 13. The maximum recommended junction temperature for the TPA6012A4 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.

(13)

NOTE

Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel.

Table 6 and Table 7 show that some applications require no airflow to keep junction temperatures in the

specified range. The TPA6012A4 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Table 6 and Table 7 were calculated for maximum listening volume without distortion. When the output level is reduced the numbers in the table change significantly. Also, using 8-Ω speakers increases the thermal performance by increasing amplifier efficiency.

Product Folder Link(s) :TPA6012A4

PACKAGE OPTION ADDENDUM

www.ti.com 7-Dec-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TPA6012A4PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

no Sb/Br)

TPA6012A4PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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TEXAS INSTRUMENTS TPA6012A4 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

FUNCTIONAL BLOCK DIAGRAM

TYPICAL CHARACTERISTICS

Table of Graphs

APPLICATION INFORMATION

SELECTION OF COMPONENTS

SE/BTL OPERATION

SHUTDOWN MODES

FADE OPERATION

VOLUME OPERATION

INPUT RESISTANCE

USING LOW-ESR CAPACITORS

BRIDGE-TIED LOAD vs SINGLE-ENDED LOAD

SINGLE-ENDED OPERATION

BTL AMPLIFIER EFFICIENCY

CREST FACTOR AND THERMAL CONSIDERATIONS