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TPA5050
Technical data
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TEXAS INSTRUMENTS TPA5050 Technical data

TPA5050
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LRCLK
DATA DATA_OUT
3
3.3V
LRCLK
DATA
TPA5050
Digital Amplifier
SCLK
AudioProcessor
SCLK
LRCLK
DATA
SDA
SCL
ADDx
(2:0)
I CDelay
Control
2
VDD
GND
TAS3103A
or
ATSC
Processor
TAS5504A +TAS5122
STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL

FEATURES APPLICATIONS

• Digital Audio Formats: 16-24-bit I2S,
Right-Justified, Left-Justified
• I2C Bus Controlled
• Single Serial Input Port
• Delay Time: 170 ms/ch at fs = 48 kHz
• Delay Resolution: One Sample
• Delay Memory Cleared on Power-Up or After
Delay Changes – Eliminates Erroneous Data From Being
Output
• 3.3 V Operation With 5 V Tolerant I/O and I2C
Control
• Supports Audio Bit Clock Rates of 32 to 64 fs
with fs = 32 kHz–192 kHz
• No external crystal or oscillator required
– All Internal Clocks Generated From the
Audio Clock
• Surface Mount 4mm × 4mm, 16-pin QFN
Package
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
• High Definition TV Lip-Sync Delay
• Flat Panel TV Lip-Sync Delay
• Home Theater Rear-Channel Effects
• Wireless Speaker Front-Channel
Synchronization

DESCRIPTION

The TPA5050 accepts a single serial audio input, buffers the data for a selectable period of time, and outputs the delayed audio data on a single serial output. One device allows delay of up to 170 ms/ch (fs = 48 kHz) to synchronize the audio stream to the video stream in systems with complex video processing algorithms. If more delay is needed, the devices can be connected in series.

SIMPLIFIED APPLICATION DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
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BCLK
DATA_OUT
GND
VDD
ADD1
LRCLK
SCL
GND
ADD0
ADD2
GND
DATA
7
5
6
11
9
10
12
16
15
14
13
3
1
2
4
SDA
8
GND
GND
GND
RSA (QFN)PACKAGE
(TOP VIEW)
DATA
BCLK
LRCLK
INPUT
BUFFER
OUTPUT BUFFER
DATA_OUT
CONTROL
2
3
I C
2
ADDx(2:0)
DELAY
MEMORY
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007

PIN DESCRIPTIONS

TERMINAL FUNCTIONS
TERMINAL
NAME NO.
ADD0 10 I I2C address select pin – LSB ADD1 11 I I2C address select pin ADD2 12 I I2C address select pin – MSB BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input. DATA 2 I Audio serial data input for serial input. 5V tolerant input. DATA_OUT 15 O Delayed audio serial data output. GND 5–9, 14 P Ground – All ground terminals must be tied to GND for proper operation LRCLK 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input. SCL 3 I I2C communication bus clock input. 5V tolerant input. SDA 4 I/O I2C communication bus data input. 5V tolerant input. VDD 13 P Power supply interface.
Thermal Pad -
I/O DESCRIPTION
Connect to ground. Must be soldered down in all applications to properly secure device on the PCB.

FUNCTIONAL BLOCK DIAGRAM

2
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SLOS492B – MAY 2006 – REVISED MAY 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)
V
Supply voltage –0.3 to 3.6 V
DD
V
Input voltage
I
Continuous total power dissipation See Dissipation Rating Table
T
Operating free-air temperature range –40 to 85 ° C
A
T
Operating junction temperature range –40 to 125 ° C
J
T
Storage temperature range –65 to 125 ° C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DATA, LRCLK, BCLK, SCL, SDA –0.3 to 5.5 V ADD[2:0] –0.3 to VDD+0.3
(1)
VALUE UNIT
TPA5050

DISSIPATION RATINGS

(1)
PACKAGE TA≤ 25 ° C DERATING TA= 70 ° C TA= 85 ° C
POWER RATING FACTOR POWER RATING POWER RATING
RSA 2.5 W 25mW/ ° C 1.375 W 1.0 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017 D and SLUA271 for more information about using the QFN thermal pad.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
V V V T
Supply voltage VDD 3 3.6 V
DD
High-level input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] 2 V
IH
Low-level input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] 0.8 V
IL
Operating free-air temperature –40 85 ° C
A
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SCL
SDA
t
w(H)
t
w(L)
t
su1
t
h1
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition
StopCondition
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007

DC CHARACTERISTICS

TA= 25 ° C, V
I
DD
I
OH
I
OL
I
IH
I
IL
= 3 V (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply current V High-level output current DATA_OUT = 2.6 V 7 13 mA Low-level output current DATA_OUT = 0.4 V 7 13 mA
High-level input current µ A
Low-level input current 1 µ A
= 3.3 V, fs = 48 kHz, BCLK = 32 fs 1.5 3 mA
DD
DATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V 20 ADD[2:0], Vi = 3.6V, VDD = 3.6V 5 DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0], Vi = 0V,
VDD = 3.6V

TIMING CHARACTERISTICS

(1) (2)
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
Frequency, SCL No wait states 400 kHz
SCL
t
Pulse duration, SCL high 0.6 µ s
w(H)
t
Pulse duration, SCL low 1.3 µ s
w(L)
t
Setup time, SDA to SCL 100 ns
su1
t
Hold time, SCL to SDA 10 ns
h1
t
Bus free time between stop and start condition 1.3 µ s
(buf)
t
Setup time, SCL to start condition 0.6 µ s
su2
t
Hold time, start condition to SCL 0.6 µ s
h2
t
Setup time, SCL to stop condition 0.6 µ s
su3
(1) V (2) A pull-up resistor ≤ 2 k Ω is required for a 5 V I2C bus voltage.
= V
Pull-up
DD
4
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
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Serial Audio Input Ports

t
h1
t
su1
t
su2
t
h2
DATA
(Input)
LRCLK
(Input)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
Frequency, BCLK 32 × fs, 48 × fs, 64 × fs 1.024 12.288 MHz
SCLKIN
t
Setup time, LRCLK to BCLK rising edge 10 ns
su1
t
Hold time, LRCLK from BCLK rising edge 10 ns
h1
t
Setup time, DATA to BCLK rising edge 10 ns
su2
t
Hold time, DATA from BCLK rising edge 10 ns
h2
LRCLK frequency 32 48 192 kHz BCLK duty cycle 50% LRCLK duty cycle 50% BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 64 BCLK edges
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Figure 3. Serial Data Interface Timing

APPLICATION INFORMATION

AUDIO SERIAL INTERFACE

The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64 times the sampling frequency for right-justified, left-justified, and I2S formats. A system clock is not necessary for the operation of the TPA5050.

AUDIO DATA FORMATS AND TIMING

The TPA5050 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The data formats are shown in Figure 4 . Data formats are selected using the I2C interface and register map (see
Table 1 ).
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LRCK
(2)I2SDataFormat;L-Channel=LOW,R-Channel=HIGH
MSB LSB
1/f
S
(= 32fS,48fS,or64fS)
18-BitRight-Justified,BCK=48fSor64f
S
1/f
S
(1) Right-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
(3)Left-JustifiedDataFormat;L-Channel=HIGH,R-Channel=LOW
MSB LSB
20-Bit Right-Justified,BCK=48fSor64f
S
MSB LSB
24-BitRight-Justified,BCK=48fSor64f
S
1/f
S
(=32fS,48fS,or64fS)
(=32fS,48fS,or64fS)
MSB LSB
16-BitRight-Justified,BCK=32f
S
16-BitRight-Justified,BCK=48fSor64f
S
MSB LSB
L-Channel R-Channel
BCK
DATA 14 15 16
1 2 3 14 15 16
14 15 16 1 2 3 14 15 16
16 17 18
DATA
DATA
DATA
DATA
1 2 3 16 17 18
18 19 20 1 2 3 18 19 20
22 23 24 1 2 3
MSB LSB
MSB LSB
MSB LSB
MSB LSB
1 2 3 14 15 16
1 2 3 14 15 16
1 2 3 16 17 18
1 2 3 18 19 20
22 23 24
MSB LSB
1 2 3 22 23 24
L-Channel R-ChannelLRCK
BCK
DATA
1 2 3 1 2
MSB
N–2NN–1
LSB
1 2 3
MSB
N–2NN–1
LSB
L-Channel R-Channel
LRCK
BCK
DATA 1 2 3
N–2NN–1
1 2 3
N–2NN–1
1 2
MSB LSB LSBMSB
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
6
Figure 4. Audio Data Formats
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Register(N)
8-BitDatafor 8-BitDatafor
Register(N+1)
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)

GENERAL I2C OPERATION

The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 5 . The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA5050 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 k Ω and 2 k Ω in value must be used.
Figure 5. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 5 .
The 7-bit address for the TPA5050 is selectable using the 3 address pins (ADD2, ADD1, ADD0). Table 1 lists the 8 possible slave addresses.
Table 1. I2C Slave Address
FIXED ADDRESS
(4 MSB bits)
1101 0 0 0 1101 0 0 1 1101 0 1 0 1101 0 1 1 1101 1 0 0 1101 1 0 1 1101 1 1 0 1101 1 1 1
ADD2 ADD1 ADD0
SELECTABLE ADDRESS BITS

SINGLE-AND MULTIPLE-BYTE TRANSFERS

The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA5050 responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
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