TEXAS INSTRUMENTS TPA321 Technical data

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1
2
3
4

8
7
6
5

SHUTDOWN

BYPASS

IN+
IN-

VO­GND
V

DD

VO+

D OR DGN PACKAGE

(TOP VIEW)

Audio

Input

Bias

Control

V

DD

350 mW

6

5

7

VO+

V

DD

1

24BYPASS

IN -

VDD/2

C

I

R

I

C

S

1

µ

F

C

B

0.1

µ

F

R

F

SHUTDOWN

VO- 8

GND

From System Control

3 IN+

-

+

-

+

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

350-mW MONO AUDIO POWER AMPLIFIER WITH DIFFERENTIAL INPUTS

• Fully Specified for 3.3-V and 5-V Operation

• Wide Power Supply Compatibility

2.5 V – 5.5 V

• Output Power for R

– 350 mW at V
– 250 mW at V

DD
DD

• Ultralow Supply Current in Shutdown

Mode . . . 0.15 µA

• Thermal and Short-Circuit Protection

• Surface-Mount Packaging

– SOIC
– PowerPAD™ MSOP

DESCRIPTION

The TPA321 is a bridge-tied load (BTL) audio power amplifier developed especially for low-voltage applications
where internal speakers are required. Operating with a 3.3-V supply, the TPA321 can deliver 250 mW of
continuous power into a BTL 8-Ω load at less than 1% THD+N throughout voice band frequencies. Although this
device is characterized out to 20 kHz, its operation was optimized for narrower band applications such as cellular
communications. The BTL configuration eliminates the need for external coupling capacitors on the output in
most applications, which is particularly important for small battery-powered equipment. This device features a
shutdown mode for power-sensitive applications with a quiescent current of 0.15 µA during shutdown. The
TPA321 is available in an 8-pin SOIC surface-mount package and the surface-mount PowerPAD™ MSOP, which
reduces board space by 50% and height by 40%.

L

= 5 V
= 3.3 V

= 8 Ω

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

Copyright © 2000–2004, Texas Instruments Incorporated

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TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

T

A

–40°C to 85°C TPA321D TPA321DGN AJB

(1) The D and DGN packages are available taped and reeled. To order a taped and reeled part, add the

suffix R to the part number (e.g., TPA321DR).

AVAILABLE OPTIONS

PACKAGED DEVICES

SMALL OUTLINE

(1)

(D) MSOP

(1)

(DGN)

MSOP

SYMBOLIZATION

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V
V

T
T
T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

Supply voltage 6 V

DD

Input voltage –0.3 V to V

I

Continuous total power dissipation Internally limited (see Dissipation Rating Table)
Operating free-air temperature range –40°C to 85°C

A

Operating junction temperature range –40°C to 150°C

J

Storage temperature range –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

UNIT

+0.3 V

DD

DISSIPATION RATING TABLE

PACKAGE TA≤ 25°C DERATING FACTOR TA= 70°C TA= 85°C

D 725 mW 5.8 mW/°C 464 mW 377 mW

DGN 2.14 W

(1) See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report

(literature number SLMA002), for more information on the PowerPAD™ package. The thermal data
was measured on a PCB layout based on the information in the section entitled Texas Instruments
Recommended Board for PowerPAD on page 33 of the before mentioned document.

(1)

17.1 mW/°C 1.37 W 1.11 W

RECOMMENDED OPERATING CONDITIONS

V
V
V
T

2

Supply voltage 2.5 5.5 V

DD

High-level voltage SHUTDOWN 0.9 V

IH

Low-level voltage SHUTDOWN 0.1 V

IL

Operating free-air temperature –40 85 °C

A

MIN MAX UNIT

DD

V
V

DD

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SLOS312C – JUNE 2000 – REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

at specified free-air temperature, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

|V

| Output offset voltage (measured differentially) SHUTDOWN = 0 V, RL= 8 Ω, RF= 10 kΩ 5 20 mV

OO

PSRR Power supply rejection ratio V
I

DD

I

DD(SD)

|IIH| High-level input current SHUTDOWN, V
|IIL| Low-level input current SHUTDOWN, V

Supply current (see Figure 3 ) SHUTDOWN = 0 V, RF= 10 kΩ 0.7 1.5 mA
Supply current, shutdown mode (see Figure 4 ) SHUTDOWN = VDD, RF= 10 kΩ 0.15 5 µA

= 3.3 V, TA= 25°C (unless otherwise noted)

DD

DD

= 3.2 V to 3.4 V 85 dB

= 3.3 V, VI= 3.3 V 1 µA

DD

= 3.3 V, VI= 0 V 1 µA

DD

OPERATING CHARACTERISTICS

V

= 3.3 V, TA= 25°C, RL= 8 Ω

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

P

O

Output power

THD + N Total harmonic distortion plus noise 1.3%

Maximum output power bandwidth AV= -2 V/V, THD = 3%, See Figure 7 10 kHz

B

1

Unity-gain bandwidth Open loop, See Figure 15 1.4 MHz
Supply ripple rejection ratio f = 1 kHz, CB= 1 µF, See Figure 2 71 dB

V

n

Noise output voltage 15 µV(rms)

(1) Output power is measured at the output terminals of the device at f = 1 kHz.

(1)

THD = 0.5%, See Figure 9 250 mW
PO= 250 mW, f = 20 Hz to 4 kHz,

AV= -2 V/V, See Figure 7

AV= –1 V/V, CB= 0.1 µF,
RL= 32 Ω , See Figure 19

TPA321

ELECTRICAL CHARACTERISTICS

at specified free-air temperature, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

|V

| Output offset voltage (measured differentially) SHUTDOWN = 0 V, RL= 8 Ω, RF= 10 kΩ 5 20 mV

OO

PSRR Power supply rejection ratio V
I

DD

I

DD(SD)

|IIH| High-level input current SHUTDOWN, V
|IIL| Low-level input current SHUTDOWN, V

Supply current (see Figure 3 ) SHUTDOWN = 0 V, RF= 10 kΩ 0.7 1.5 mA
Supply current, shutdown mode (see Figure 4 ) SHUTDOWN = VDD, RF= 10 kΩ 0.15 5 µA

= 5 V, TA= 25°C (unless otherwise noted)

DD

= 4.9 V to 5.1 V 78 dB

DD

= 5.5 V, VI= V

DD

= 5.5 V, VI= 0 V 1 µA

DD

DD

OPERATING CHARACTERISTICS

V

= 5 V, TA= 25°C, RL= 8 Ω

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

P

O

THD + N Total harmonic distortion plus noise 1%

B

1

V

n

Output power THD = 0.5%, See Figure 13 700 mW

PO= 350 mW, f = 20 Hz to 4 kHz, See

AV= –2 V/V, Figure 11
Maximum output power bandwidth AV= –2 V/V, THD = 2%, See Figure 11 10 kHz
Unity-gain bandwidth Open loop, See Figure 16 1.4 MHz
Supply ripple rejection ratio f = 1 kHz, CB= 1 µF, See Figure 2 65 dB

Noise output voltage 15 µV(rms)

AV= -1 V/V, CB= 0.1 µF,

RL= 32 Ω , See Figure 20

1 µA

3

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Audio

Input

Bias

Control

V

DD

6

5

7

VO+

V

DD

1

24BYPASS

IN -

VDD/2

C

I

R

I

C

S

1

µ

F

C

B

0.1

µ

F

R

F

SHUTDOWN

VO- 8

R

L = 8

Ω

GND

3 IN+

-

+

-

+

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

Terminal Functions

TERMINAL

NAME NO.

BYPASS 2 I
GND 7 GND is the ground connection.

IN- 4 I IN- is the inverting input. IN- is typically used as the audio input terminal.
IN+ 3 I IN+ is the noninverting input. IN+ is typically tied to the BYPASS terminal for SE operations.
SHUTDOWN 1 I SHUTDOWN places the entire device in shutdown mode when held high (I
V

DD

VO+ 5 O VO+ is the positive BTL output.
VO- 8 O VO- is the negative BTL output.

I/O DESCRIPTION

BYPASS is the tap to the voltage divider for internal mid-supply bias. This terminal should be connected
to a 0.1-µF to 1-µF capacitor when used as an audio amplifier.

6 V

is the supply voltage terminal.

DD

PARAMETER MEASUREMENT INFORMATION

DD

~ 0.15 µA).

Figure 1. Test Circuit

4

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−50

−60

−80

−100
20 100 1 k

−30

−20

f − Frequency − Hz

0

10 k 20 k

−10

−40

−70

−90

VDD = 5 V

VDD = 3.3 V

RL = 8 Ω
CB = 1 µF

k

SVR

− Supply Voltage Rejection Ratio − dB

VDD − Supply Voltage − V

1.1

0.7

0.3

−0.1

0.9

0.5

0.1

3 4 62 5

I

DD

− Supply Current − mA

SHUTDOWN = 0 V
RF = 10 kΩ

k

SVR

I

DD

P

O

Supply voltage rejection ratio vs Frequency 2
Supply current vs Supply voltage 3, 4

Output power

THD+N Total harmonic distortion plus noise

Open-loop gain and phase vs Frequency 15, 16
Closed-loop gain and phase vs Frequency 17, 18

V

n

P

D

Output noise voltage vs Frequency 19, 20
Power dissipation vs Output power 21, 22

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Supply voltage 5
vs Load resistance 6
vs Frequency 7, 8, 11, 12
vs Output power 9, 10, 13, 14

SUPPLY VOLTAGE REJECTION RATIO SUPPLY CURRENT

vs vs

FREQUENCY SUPPLY VOLTAGE

Figure 2. Figure 3.

5

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VDD − Supply Voltage − V

0.15

0.1

0.05
3 43.5 4.5

0.35

2 5

0.2

0.25

0.3

5.52.5

0.4

0.45

0.5

I

DD(SD)

− Supply Current − Aµ

SHUTDOWN = V

DD

RF = 10 kΩ

VDD − Supply Voltage − V

600

400

200

0

2.5 3.53 4 5.5

1000

2

P

4.5 5

O

− Output Power − mW

800

THD+N 1%

RL = 32 Ω

RL = 8 Ω

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

SUPPLY CURRENT (SHUTDOWN)

vs

SUPPLY VOLTAGE

Figure 4.

OUTPUT POWER

vs

SUPPLY VOLTAGE

Figure 5.

6

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RL − Load Resistance − Ω

300

200

100

0

16 3224 40 64

800

8

P

48 56

O

− Output Power − mW

400

THD+N = 1%

VDD = 5 V

500

600

VDD = 3.3 V

700

f − Frequency − Hz

THD+N −Total Harmonic Distortion + Noise − %

AV = −2 V/V

VDD = 3.3 V
PO = 250 mW
RL = 8 Ω

20 1k 10k

1

0.01

10

0.1

20k100

AV = −20 V/V

AV =− 10 V/V

f − Frequency − Hz

THD+N −Total Harmonic Distortion + Noise − %

PO = 125 mW

VDD = 3.3 V
RL = 8 Ω
AV = −2 V/V

20 1k 10k

1

0.01

10

0.1

20k100

PO = 50 mW

PO = 250 mW

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

OUTPUT POWER

vs

LOAD RESISTANCE

Figure 6.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 7. Figure 8.

7

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PO − Output Power − W

THD+N −Total Harmonic Distortion + Noise − %

f = 20 Hz

VDD = 3.3 V
RL = 8 Ω
AV = −2 V/V

0.01 0.1 1

1

0.01

10

0.1

f = 1 kHz

f = 10 kHz

f = 20 kHz

PO − Output Power − W

THD+N −Total Harmonic Distortion + Noise − %

RL = 8 Ω

0.04 0.1 0.4

1

0.01

10

0.1

0.16 0.22 0.28 0.34

VDD = 3.3 V
f = 1 kHz
AV = −2 V/V

f − Frequency − Hz

THD+N −Total Harmonic Distortion + Noise − %

AV = −2 V/V

VDD = 5 V
PO = 350 mW
RL = 8 Ω

20 1k 10k

1

0.01

10

0.1

20k100

AV = −20 V/V

AV =− 10 V/V

f − Frequency − Hz

THD+N −Total Harmonic Distortion + Noise − %

PO = 175 mW

VDD = 5 V
RL = 8 Ω
AV = −2 V/V

20 1k 10k

1

0.01

10

0.1

20k100

PO = 50 mW

PO = 350 mW

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 9. Figure 10.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

8

Figure 11. Figure 12.

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PO − Output Power − W

THD+N −Total Harmonic Distortion + Noise − %

f = 20 Hz

VDD = 5 V
RL = 8 Ω
AV = −2 V/V

0.01 0.1 1

1

0.01

10

0.1

f = 1 kHz

f = 10 kHz

f = 20 kHz

PO − Output Power − W

0.1 0.25 10.40 0.55 0.70 0.85

THD+N −Total Harmonic Distortion + Noise − %

RL = 8 Ω

VDD = 5 V
f = 1 kHz
AV = −2 V/V

1

0.01

10

0.1

10

0

−20

−30

20

30

f − Frequency − kHz

40

−10

180

120

0

−120

−180

VDD = 3.3 V
RL = Open

Gain

Phase

60

−60

Open-Loop Gain − dB

Phase − °

1

10

1

10

2

10

3

10

4

TPA321

SLOS312C – JUNE 2000 – REVISED JUNE 2004

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 13. Figure 14.

OPEN-LOOP GAIN AND PHASE

vs

FREQUENCY

Figure 15.

9