Texas Instruments TPA3200D1 User Manual

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LRCK

1.0 mF

Control

Inputs

DGND

Gain Select

+5V

Channel Select

{

BCK

GAIN0

VCOM

DATA

FORMAT

SCLK

GAIN1

LR_SEL

VDD

SHUTDOWN

VCLAMP

PGND

Shutdown Control

+18V

MUTE

DEMP

ZERO

AVCC

10 mF

{

Zero Input Flag

FLT1

FLT2

22 nF

COSC

AGND

ROSC

VREF

BYPASS

220 pF

1 mF

120 kW

0.22 mF

BSN

51 W

OUTN

0.22 mF

BSP

OUTP

51 W

PVCC

Digital Audio

Processor

TPA3200D1

I2S or 16-bit RJ

TAS3103

20-W MONO DIGITAL INPUT AUDIO AMPLIFIER

FEATURES DESCRIPTION

• Digital Interface

– 24-bit Resolution – Supports I2S and 16-Bit Word

Right-Justified Digital Input Formats

– Multiple Sampling Frequencies:

5 kHz – 200 kHz – 8x Oversampling Digital Filter – Soft Mute

• Power Amplifier – 20-W into an 8- Ω Load from an 18-V Supply – Efficient Operation Eliminates Need for Heat

Sinks – Three Selectable, Fixed Gain Settings – Thermal and Short-Circuit Protection

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

The TPA3200D1 is a 20-W (per channel) efficient, digital audio power amplifier for driving a bridged-tied speaker. The TPA3200D1 can drive a speaker with an impedance as low as 4 Ω . The high efficiency of the TPA3200D1 (85%) eliminates the need for an external heat sink.

The digital input accepts 16-24 bit data in I2S format or 16-bit word right-justified. A digital filter performs an 8x interpolation function. Other features include soft mute, a zero input detect output flag for power conscious designs, and power saving shutdown mode.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Simplified Application Circuit

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TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

–40 ° C to 85 ° C TPA3200D1DCP

(1) The DCP package is available taped and reeled. To order a taped

and reeled part, add the suffix R to the part number (e.g., TPA3200D1DCPR).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Vi GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, LR_SEL

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Supply voltage, VCC, PVCC –0.3 to 21 V Supply voltage, VDD –0.3 to 6.5 V Load Impedance ≥ 3.6 Ω SHUTDOWN – 0.3 to V

FORMAT, MUTE, DEMP Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range –25 to 85 ° C Operating junction temperature range –25 to 150 ° C Storage temperature range –65 to 150 ° C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 ° C

PACKAGED DEVICE

44-PIN (DCP)

(1)

TPA3200D1 UNIT

+ 0.3 V

–0.3 to V

+ 0.3 V

DISSIPATION RATINGS

PACKAGE TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C

44-pin DCP 4.89 W 39.1 mW/ ° C

(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the printed-circuit board. See the PowerPAD

Thermally Enhanced Package technical brief, literature number SLMA0002. The PowerPAD must be soldered to the PCB.

(1/ θJA)

(1)

3.13 W 2.54 W

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RECOMMENDED OPERATING CONDITIONS

PARAMETER PIN NAME MIN MAX UNIT

OSC

Supply voltage

High-level input voltage 2

Low-level input voltage 0.8 High-level input voltage LR_SEL VDD x 0.7

Low-level input voltage LR_SEL VDD x 0.3

High-level input current

Low-level input current

High-level output voltage IOH= –1 mA, ZERO 2.4 Low-level output voltage IOL= 1 mA, ZERO 0.4 Oscillator frequency 200 300 kHz

SLOS442A – MAY 2005 – REVISED JULY 2005

PVCC, VCC 8 18 VDD 4.5 5.5 SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,

LRCK, FORMAT, MUTE, DEMP SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,

LRCK, FORMAT, MUTE, DEMP

SHUTDOWN: VI= VCC, VCC = 12 V 1 GAIN0, GAIN1, LR_SEL: VI= VDD, VDD = 5 V 1 SCLK, BCK, DATA, LRCK: VI= VDD, VDD = 5 V 10 FORMAT, MUTE, DEMP: VI= VDD, VDD = 5 V 100 SHUTDOWN: VI= 0 V, VCC = 12 V 1 GAIN0, GAIN1, LR_SEL: VI= 0 V, VDD = 5 V 1 BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP:

VI= 0 V, VDD = 5 V

TPA3200D1

µA

ELECTRICAL CHARACTERISTICS

All specifications at TA= 25 ° C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY REQUIREMENTS

DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS

ANALOG FILTER PERFORMANCE

SAMPLING FREQUENCY

fs Sampling frequency 5 200 KHz

DYNAMIC PERFORMANCE

(1) Conditions in 192-kHz operation are system clock = 128 fSand oversampling rate = 64 fSof register 18.

Supply current fS= 96 kHz 25 mA

Pass band ± 0.04 dB 0.454 f Stop band 0.546 f Pass-band ripple ± 0.04 dB Stop-band attenuation Stop band = 0.546 f

Frequency response dB

Channel separation fS= 44.1 KHz, 96 KHz, 192 KHz 100 dB

= 5 V, fS= 44.1 kHz, system clock = 384 fSand 24-bit data, unless otherwise noted

(1)

fS= 44.1 kHz 26 31

fS= 192 kHz 30

–50 dB

At 20 kHz –0.03 At 44 kHz –0.20

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TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

FORMAT CHARACTERISTICS

All specifications at TA= 25 ° C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 24 Bits

Data

Audio-data interface format Audio I2S, standard Audio-data bit length Audio 16–24-bit (I2S), 16-bit (Right-justified) Audio data format MSB first, 2s complement System clock frequency 128 fS,192 fS, 256 fS, 384 fS,

ELECTRICAL CHARACTERISTICS

at TA= 25 ° C, PV

| Output offset voltage (measured differentially) MUTE = 2 V AV= 12 dB 100 mV

PSRR Power supply rejection ratio PV V

5 V regulator voltage IL= 10 mA, V

REF

Supply current

Supply current shutdown mode SHUTDOWN = 0.8 V 1 2 µA

CC(SD)

Output transistor on resistance (high side and

DS(on)

low side)

G Gain GAIN1 = 0.8 V, GAIN0 = 2 V 17.1 18 18.6 dB

= V

= 12 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 5 V, fS= 44.1 kHz, system clock = 384 fSand 24-bit data, unless otherwise noted

512 fS, 768 fS, 1152 f

= 11.5 V to 12.5 V –73 dB

= 8 V – 18 V 4.55 4.9 5.45 V

SHUTDOWN = 2.0 V, No load 8 15 mA SHUTDOWN = VCC, V

RL= 8 Ω

= 18 V, PO = 20 W, 1.3

IO= 0.5 A, TJ= 25 ° C 0.5 0.6 0.7 Ω GAIN1 = 0.8 V, GAIN0 = 0.8 V 10.9 12 13.1

GAIN1 = 2 V, GAIN0 = 0.8 V 22.9 23.6 24.4

OPERATING CHARACTERISTICS

= V

THD+N Total harmonic distortion plus noise PO= 10 W, RL= 4 Ω  f = 20 Hz to 20 kHz 0.2% B

SVR

SNR Signal-to-noise ratio PO= 10 W, RL= 4 Ω 95

= 12 V, TA= 25 ° C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Continuous output power at 10% THD+N f = 1 kHz, RL= 4 Ω 12.8

f = 1 kHz, RL= 8 Ω 9

Continuous output power at 1% THD+N f = 1 kHz, RL= 4 Ω 10.3

f = 1 kHz, RL= 8 Ω 7.5

Maximum output power bandwidth THD = 1% 20 kHz Supply ripple rejection ratio f = 1 kHz, C

Noise output voltage

C A-weighted filter Gain = 12 dB

= 1 µF, f = 20 Hz to 22 kHz, 150 µV(rms)

(BYPASS)

= 1 µF –60

–76.5 dBV

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Audio Serial

Port

Serial

Control

Port

4x/8x

Oversampling

Digital

Filter

and

Function

Control

Multi-Level

Delta-Sigma

Modulator

Audio Serial

Port

System Clock

BCK

LRCK

DATA

FORMAT

MUTE

DEMP

SCLK

DAC and

2:1 Mux

LR_SEL

VCOM

Gain

Adjust

− +

−

Gain

Adjust

FLT1

FLT2

_ +

Deglitch

Logic

Deglitch

Logic

Gate

Drive

Gate

Drive

Clamp

Reference

Short-Circuit

Detect

Start-Up

Protection

Logic

Thermal VCC OK

Gain

SHUTDOWN

GAIN0 GAIN1

Biases

and

References

Ramp Generator

VREF AGND AVCC

VREF AV

Power Supply

Zero Detect

COSC ROSC

BYPASS

ZERO

VDD

DGND

VCLAMP BSN

PVCC

OUTN

PGND BSP

OUTP

PGND

PVCC

Functional Block Diagram

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

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BCK

SCLK

LRCK

DATA

DGND

VDD

LR_SEL

VDD

DGND

VCOM

GAIN0

GAIN1

SHUTDOWN

PGND

VCLAMP

BSN

PVCC

OUTN

PGND

FORMAT

MUTE

DEMP

DGND

ZERO

DGND

FLT1

FLT2

VCC

VREF

BYPASS

COSC

ROSC

AGND

BSP

PVCC

OUTP

PGND

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

DCP

(TOP VIEW)

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SLOS442A – MAY 2005 – REVISED JULY 2005

Terminal Functions

TERMINAL

NO. NAME

1 BCK I Bit clock input for audio data 3 DATA I Audio data input 4 LRCK I Left and right channel audio data latch enable input

7 LR_SEL I HIGH: Left channel active

11 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to 5 V. 12 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to 5 V.

13 SHUTDOWN I

5, 9, 38, 40 DGND - Digital ground

6, 8 VDD - Digital power supply (4.5 V – 5.5 V)

15 VCLAMP - Internally generated voltage supply for bootstrap capacitor 17 BSN I/O Bootstrap I/O, negative high-side FET 28 BSP I/O Bootstrap I/O, positive high-side FET

2, 16 NC - No internal connection

31 ROSC I/O I/O for current setting resistor for ramp generator 32 COSC I/O I/O for charge/discharging currents onto capacitor for ramp generator creation 33 BYPASS O Midrail analog reference voltage 34 VREF O Analog 5-V regulated output. Not to be used for powering external circuitry. 35 VCC - High-voltage analog power supply (8 V to 18 V).

19, 20 OUTN O Class-D 1/2-H-bridge negative output

39 ZERO O

41 DEMP I HIGH: 44.1 kHz De-emphasis ON

42 MUTE I HIGH: Mute ON

43 FORMAT I HIGH: 16-bit right justified

44 SCLK I System clock input 18, 27 PVCC - Power supply for H-bridge (8 V to 18 V) 25, 26 OUTP O Class-D 1/2-H-bridge positive output 29, 30 AGND - Analog ground

14, 21, 22, 23, 24 PGND - Power ground for H-bridge

10 VCOM - Midrail digital reference voltage

36 FLT2 I/O

37 FLT1 I/O

Thermal Pad

I/O DESCRIPTION

Select left-channel or right-channel data LOW: Right channel active

Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to 18 V.

Zero flag output HIGH: No input present LOW: Data present at input This can be used to shutdown the device when no data is present at input.

De-emphasis control. LOW: 44.1 kHz De-emphasis OFF

Soft mute control LOW: Mute OFF

Audio data format select LOW: 16- to 24-bit, I2S format

Noise-filter terminals. Connect capacitor across pins 36 and 37

Connect to AGND and PGND - should be the center point for both grounds. Internal esistive connection to AGND.

TPA3200D1

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0.01

0.02

0.05

0.1

0.2

0.5

10m 10100m 200m 1 2

Total Hormonic Distortion Plus Noise − %

PO − Output Power − W

20 Hz

1 kHz

10 kHz

VCC = 12 V RL = 8  Gain = 18 dB fS = 48 kHz 24−bit, I2S format

0.01

0.02

0.05

0.1

0.2

0.5

10m 10100m 200m 1 2

Total Hormonic Distortion Plus Noise − %

PO − Output Power − W

20 Hz

1 kHz

10 kHz

VCC = 12 V RL = 8  Gain = 23.6 dB fS = 48 kHz 24−bit, I2S format

0.01

0.02

0.05

0.1

0.2

0.5

10m 20100m 200m 1 10

THD+N - T

otal Harmonic Distortion + Noise - %

PO- Output Power - W

10 kHz

1 kHz

R = 4 ,LÙ

Gain = 18 dB,

f = 48 kHz,

24-bit, I S format

V = 12 V

20 Hz

0.01

0.02

0.05

0.1

0.2

0.5

10m

100m 200m

1102

Total Hormonic Distortion Plus Noise − %

PO − Output Power − W

20 Hz

1 kHz

10 kHz

VCC = 18 V RL = 8  Gain = 23.6 dB fS = 48 kHz 24−bit, I2S format

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

TYPICAL CHARACTERISTICS

Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noise

vs vs

Output Power Output Power

Figure 1. Figure 2.

Harmonic Distortion Plus Noise Total Harmonic Distortion

vs vs

Output Power Power

Figure 3. Figure 4.

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0.01

0.02

0.05

0.1

0.2

0.5

20 20k100 200 1k 2k 10k

PO = 1 W

Total Hormonic Distortion Plus Noise − %

f − Frequency − Hz

VCC = 12 V RL = 8  Gain = 18 dB fS = 48 kHz 24−bit, I2S format

PO = 5 W

PO = 500 mW

0.01

0.02

0.05

0.1

0.2

0.5

20 20k100 200 1k 2k 10k

Total Hormonic Distortion Plus Noise − %

f − Frequency − Hz

PO = 500 mW

PO = 1 W

PO = 5 W

VCC = 12 V RL = 8  Gain = 23.6 dB fS = 48 kHz 24−bit, I2S format

0.01

0.02

0.05

0.1

0.2

0.5

20 20k100 200 1k 2k 10k

Total Hormonic Distortion Plus Noise − %

f − Frequency − Hz

PO = 500 mW

PO = 1 W

PO = 5 W

VCC = 18 V RL = 8  Gain = 18 dB fS = 48 kHz 24−bit, I2S format

0.01

0.02

0.05

0.1

0.2

0.5

20 20k100 200 1k 2k 10k

Total Hormonic Distortion Plus Noise − %

f − Frequency − Hz

PO = 500 mW

PO = 1 W

PO = 5 W

VCC = 18 V RL = 8  Gain = 23.6 dB fS = 48 kHz 24−bit, I2S format

TYPICAL CHARACTERISTICS (continued)

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noise

vs vs

Frequency Frequency

Figure 5. Figure 6.

Total Harmonic Distortion Plus Noise Total Harmonic Distortion Plus Noise

vs vs

Frequency Frequency

Figure 7. Figure 8.

+ 21 hidden pages

Texas Instruments TPA3200D1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

FORMAT CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

TYPICAL CHARACTERISTICS