Texas Instruments TPA3120D2, TPA3124D2 User Manual
1 Fm
SD
MuteControl
PVCCL
TPA3120D2
TPA3120D2
SIMPLIFIED APPLICATIONCIRCUIT
PVCCR
VCLAMP
GAIN1
BYPASS
1 Fm
1 Fm
0.22 Fm
AGND
LeftChannel
RightChannel
10Vto30V
10Vto30V
}
4-StepGain
Control
Shutdown
Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 Fm
22 Hm
22 Hm
0.68 Fm
470 Fm
0.68 Fm
1 Fm
470 Fm
GAIN0
AVCC
MUTE
ROUT
LOUT
TPA3120D2
www.ti.com
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
25-W STEREO CLASS-D AUDIO POWER AMPLIFIER
1
FEATURES
2
• 25-W/ch into a 4- Ω Load from a 27-V Supply
• 20-W/ch into a 4- Ω Load from a 24-V Supply
• Operates from 10 V to 30 V
• Efficient Class-D Operation Eliminates Need
for Heat Sinks
• Four Selectable, Fixed-Gain Settings TPA3120D2 eliminates the need for an external heat
• Internal Oscillator (No External Components
Required)
• Single-Ended Analog Inputs
• Thermal and Short-Circuit Protection With
Auto Recovery
• Space-Saving Surface-Mount 24-Pin TSSOP
Package
APPLICATIONS
• Televisions
DESCRIPTION
The TPA3120D2 is a 25-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
speakers in a single-ended configuration or a mono
bridge-tied speaker. The TPA3120D2 can drive
stereo speakers as low as 4 Ω . The efficiency of the
sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The patented start-up and shut-down sequences
minimize pop noise in the speakers without additional
circuitry.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 System Two, Audio Precision are trademarks of Audio Precision, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
www.ti.com
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL
NAME
SD 2 I
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
MUTE 4 I
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
BYPASS 7 O
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Thermal pad Die pad P
2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
24-PIN
(PWP)
I/O/P DESCRIPTION
PWP (TSSOP) PACKAGE
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
outputs enabled). TTL logic levels with compliance to AVCC
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
Connect to ground. Thermal pad should be soldered down on all applications to secure the
device properly to the printed wiring board.
Product Folder Link(s): TPA3120D2
www.ti.com
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
CC
V
I
V
IN
T
A
T
J
T
stg
R
L
ESD Electrostatic Discharge
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltage AVCC, PVCC – 0.3 to 36 V
Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V
Analog input voltage RIN, LIN – 0.3 to 7 V
Continuous total power dissipation See Dissipation Ratings table
Operating free-air temperature range – 40 to 85 ° C
Operating junction temperature range – 40 to 150 ° C
Storage temperature range – 65 to 150 ° C
Load resistance (minimum value) 3.2 Ω
Human-body model (all pins) ± 2 kV
Charged-device model (all
pins)
(1)
VALUE UNIT
+ 0.3 V
CC
± 500 V
DISSIPATION RATINGS
PACKAGE
24-pin TSSOP 4.16 W 33.3 mW/ ° C 2.67 W 2.16 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See the PowerPAD Thermally Enhanced Package application note
(SLMA002 ).
(1) (2)
TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
RECOMMENDED OPERATING CONDITIONS
V
CC
V
IH
V
IL
I
IH
I
IL
T
A
Supply voltage PVCC, AVCC 10 30 V
High-level input voltage SD, MUTE, GAIN0, GAIN1 2 V
Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V
High-level input current MUTE, VI= VCC, V
Low-level input current MUTE, VI= 0 V, V
Operating free-air temperature – 40 85 ° C
SD, VI= VCC, V
= 30 V 125
CC
= 30 V 125 μ A
CC
GAIN0, GAIN1, VI= VCC, V
SD, VI= 0, V
= 30 V 1
CC
= 30 V 1 μ A
CC
GAIN0, GAIN1, VI= 0 V, V
MIN MAX UNIT
= 24 V 125
CC
= 24 V 1
CC
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPA3120D2
www.ti.com
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
DC CHARACTERISTICS
TA= 25 ° C, V
| V
| (measured differentially in BTL VI= 0 V, AV= 36 dB 7.5 50 mV
OS
V
(BYPASS)
I
CC(q)
I
CC(q)
I
CC(q)
r
DS(on)
G Gain dB
= 24 V, RL= 4 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage
mode as shown in Fig 30)
Bypass output voltage No load AVCC/8 V
Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mA
Quiescent supply current in
mute mode
Quiescent supply current in
shutdown mode
Drain-source on-state
resistance
MUTE = 0.8 V, No load 23 mA
SD = 0.8 V , No load 0.39 1 mA
200 m Ω
GAIN1 = 0.8 V
GAIN = 2 V
GAIN0 = 0.8 V 18 20 22
GAIN0 = 2 V 24 26 28
GAIN0 = 0.8 V 30 32 34
GAIN0 = 2 V 34 36 38
Mute Attenuation VI= 1Vrms – 82 dB
AC CHARACTERISTICS
TA= 25 ° C, V
ksvr Supply ripple rejection dB
P
O
THD+N
V
n
SNR Signal-to-noise ratio 99 dB
f
OSC
= 24 V, RL= 4 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Output power at 1% THD+N
Output power at 10% THD+N
Total harmonic distortion +
noise
Output integrated noise floor
= 24, V
CC
Gain = 20 dB
V
= 24 V, RL= 4 Ω , f = 1 kHz 16
CC
V
= 24 V, RL= 8 Ω , f = 1 kHz 8
CC
VCC= 24 V, RL= 4 Ω , f = 1 kHz 20
V
= 24 V, RL= 8 Ω , f = 1 kHz 10
CC
RL= 4 Ω , f = 1 kHz, PO= 10 W 0.08%
RL= 8 Ω , f = 1 kHz, PO= 5 W 0.08%
20 Hz to 22 kHz, A-weighted filter,
Gain = 20 dB
= 200 mV
ripple
100 Hz – 48
PP
1 kHz – 52
85 μ V
– 80 dBV
Crosstalk PO= 1 W, f = 1 kHz; Gain = 20 dB – 60 dB
Max output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB
Thermal trip point 150 ° C
Thermal hysteresis 30 ° C
Oscillator frequency 230 250 270 kHz
W
4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPA3120D2
www.ti.com
LS
HS
LS
HS
OSC/RAMP
MUTE
CONTROL
BYPASS
AV
CONTROL
CONTROL
BIAS
THERMAL
SC
DETECT
SC
DETECT
AVDD
AVCC
LIN
RIN
MUTE
BYPASS
GAIN1
GAIN0
SD
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
PVCCR
ROUT
PGNDR
VCLAMP
VCLAMP
AVDD
AVDD
AVDD/2
AVDD
AVDD
AVDD/2
REGULATOR
FUNCTIONAL BLOCK DIAGRAM
AGND
+
-
+
-
FUNCTIONAL BLOCK DIAGRAM
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPA3120D2
www.ti.com
f − Frequency − Hz
20 100
1k
10k
THD+N
T
otalHarmonicDistortion+Noise
%
-
-
0.1
10
20k
1
0.01
V =18V
R =4 (SE)
Gain=20dB
CC
L
W
P =5W
O
P =2.5W
O
P =1W
O
f − Frequency − Hz
20 100 1k 10k
THD+N
T
otalHarmonicDistortion+Noise
%
-
-
0.1
10
20k
1
0.01
V =24V
R =4 (SE)
Gain=20dB
CC
L
W
P =10W
O
P =1W
O
P =5W
O
f − Frequency − Hz
20 100 1k 10k
THD+N
T
otalHarmonicDistortion+Noise
%
-
-
0.1
10
20k
1
0.01
V =24V
R =8 (SE)
Gain=20dB
CC
L
W
P =1W
O
P =2.5W
O
P =5W
O
P − OutputPower − W
O
10m 100m 1 10
THD+N
T
otalHarmonicDistortion+Noise
%
-
-
1
40
10
0.01
0.1
V =12V
CC
V =24V
CC
V =18V
CC
R =4 (SE)
Gain=20dB
L
W
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
All tests are made at frequency = 1 kHz unless otherwise noted.
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY OUTPUT POWER
6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Figure 3. Figure 4.
Product Folder Link(s): TPA3120D2
www.ti.com
THD+N-TotalHarmonicDistortion+Noise-%
P − OutputPower − W
O
R =8 (SE)
Gain=20dB
L
W
1
10
0.01
0.1
10m 100m 1 10 40
V =12V
CC
V =24V
CC
V =18V
CC
-100
20 100
1k
20k
f − Frequency − Hz
Crosstalk
dB
-
10k
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
RtoL
L toR
V =18V
V =1Vrms
R =4 (SE)
Gain=20dB
CC
O
L
W
-300
200
-200
-100
0
100
0
20
5
10
15
20 100k100 200 1k 2k 10k 20k
f − Frequency − Hz
Gain dB
-
Phase
-
o
Gain
Phase
V =24V
R =4 (SE)
Gain=20dB
L =33 H
C =1 F
C =470 F
CC
L
filt
filt
dc
W
m
m
m
-100
20 100
1k
20k
f − Frequency − Hz
10k
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Crosstalk
dB
-
L toR
RtoL
V =18V,
V =1V,
R =8 ,
Gain=20dB
CC
O
L
W
TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
TOTAL HARMONIC DISTORTION + NOISE CROSSTALK
vs vs
OUTPUT POWER FREQUENCY
Figure 5. Figure 6.
CROSSTALK GAIN/PHASE
vs vs
FREQUENCY FREQUENCY
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
Figure 7. Figure 8.
Product Folder Link(s): TPA3120D2
www.ti.com
-250
200
-200
-150
-100
-50
0
50
100
150
5
22.5
7.5
10
12.5
15
17.5
20
20 100k100 200 1k 2k 10k 20k
f − Frequency − Hz
Gain dB
-
Phase
-
o
Gain
Phase
V =24V
R =8 (SE)
Gain=20dB
L =47 H
C =0.22 F
C =470 F
CC
L
filt
filt
dc
W
m
m
m
V − SupplyVoltage − V
SS
16 26
P
OutputPower
W
O
-
-
22
30
28
4
32
12
THD=10%
THD=1%
R =4 (SE)
Gain=20dB
L
W
6
8
2
14
18
10
16
20
24
30
26
1210 14 18 20 22 24 28
THD=10%
THD=1%
V -SupplyVoltage-V
SS
P -OutputPower-W
O
R =8 (SE)
Gain=20dB
L
W
16 26 301210
7
14 18 20 22 24 28
17
16
15
14
13
12
11
10
9
6
1
8
5
4
3
2
P − OutputPower − W
O
6 16
Efficiency
%
-
80
20
10
100
30
12V
18V
24V
R =4 (SE)
Gain=20dB
L
W
0
40
60
20
50
70
90
20 4 8 10 12 14 18
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
GAIN/PHASE OUTPUT POWER
vs vs
FREQUENCY SUPPLY VOLTAGE
Figure 9.
OUTPUT POWER EFFICIENCY
vs vs
SUPPLY VOLTAGE OUTPUT POWER
8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Figure 11. Figure 12.
Product Folder Link(s): TPA3120D2
A. Dashed line represents thermally limited
region.
Figure 10.
www.ti.com
P − OutputPower − W
O
Efficiency
%
-
80
10
100
30
0
40
60
20
50
70
90
12
0 1 2 3 4 5 6 7 8 9
10 11
R =8 (SE)
Gain=20dB
L
W
12V
18V
24V
P − OutputPower − W
O
I
−
SupplyCurrent
−
A
C
C
12 32
1.6
40
0.2
2
0.6
18V
0
0.8
1.2
0.4
1
1.4
1.8
40 8 16 20 24 28 36
R =4 (SE)
Gain=20dB
L
W
24V
12V
-120
20 100
1k
20k
f − Frequency − Hz
PowerSupplyRejectionRatio
dB
-
10k
-110
-100
-90
-80
-70
-50
0
V =24V
V =0.2V
R =4 (SE)
Gain=20dB
CC
O(ripple) PP
L
W
-40
-30
-20
-10
-60
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
P -OutputPower-W
O
I -SupplyCurrent- A
CC
12V
18V
24V
R =8 ,
Gain=20dB
L
W
TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
EFFICIENCY SUPPLY CURRENT
vs vs
OUTPUT POWER OUTPUT POWER
TPA3120D2
SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
Figure 13. Figure 14.
SUPPLY CURRENT POWER SUPPLY REJECTION RATIO
vs vs
OUTPUT POWER FREQUENCY
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 15. Figure 16.
Product Folder Link(s): TPA3120D2
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