Texas Instruments TPA3122D2 Instructions Manual

1 Fm

SD

MuteControl

PVCCL

TPA3122D2

SIMPLIFIED APPLICATIONCIRCUIT

PVCCR

VCLAMP

GAIN1

BYPASS

1 Fm

1 Fm

0.22 Fm

AGND

LeftChannel

RightChannel

10Vto30V

10Vto30V

}

4-StepGain

Control

Shutdown

Control

LIN

RIN

BSR

BSL

PGNDR

PGNDL

0.22 Fm

22 Hm

22 Hm

0.68 Fm

470 Fm

0.68 Fm

1 Fm

470 Fm

GAIN0

AVCC

MUTE

ROUT

LOUT

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SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

15-W STEREO CLASS-D AUDIO POWER AMPLIFIER

1

FEATURES APPLICATIONS

• 10-W/ch into an 4- Ω Load From a 17-V Supply

• 15-W/ch into an 8- Ω Load From a 28-V Supply

• Operates from 10 V to 30 V

• Efficient Class-D Operation

• Four Selectable, Fixed Gain Settings

• Internal Oscillator (No External Components

Required) The efficiency of the TPA3122D2 eliminates the need

• Single Ended Analog Inputs

• Thermal and Short-Circuit Protection with

Auto Recovery Feature

• 20-pin DIP Package

• Televisions

DESCRIPTION

The TPA3122D2 is a 15-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
single ended speakers or mono bridge tied load. The
TPA3122D2 can drive stereo speakers as low as 4 Ω .

for an external heat sink when playing music.
The gain of the amplifier is controlled by two gain

select pins. The gain selections are 20, 26, 32, and
36 dB.

TPA3122D2

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2007, Texas Instruments Incorporated

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1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PVCCL

SD

MUTE

LIN

RIN

BYPASS

AGND
AGND

PVCCR

VCLAMP

PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

N (DIP) PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

NAME

SD 2 I
RIN 5 I Audio input for right channel.

LIN 4 I Audio input for left channel.
GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.

MUTE 3 I
BSL 18 I/O Bootstrap I/O for left channel.

PVCCL 1 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
LOUT 19 O Class-D  -H-bridge positive output for left channel.
PGNDL 20 Power ground for left channel H-bridge.
VCLAMP 9 Internally generated voltage supply for bootstrap capacitors.
BSR 13 I/O Bootstrap I/O for right channel.
ROUT 12 O Class-D  -H-bridge negative output for right channel.
PGNDR 11 Power ground for right channel H-bridge.
PVCCR 10 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
AGND 8 Analog ground for digital/analog cells in core.
AGND 7 Analog Ground for analog cells in core.

BYPASS 6 O
AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL

20-PIN

(DIP)

I/O DESCRIPTION

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC.

Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
outputs enabled). TTL logic levels with compliance to AVCC.

Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.

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TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V
V
V

T
T
T
R

ESD Electrostatic Discharge

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

Supply voltage, AVCC, PVCC – 0.3 to 36 V

CC

Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V

I

Analog input voltage RIN, LIN – 0.3 to 7 V

IN

Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range – 40 to 85 ° C

A

Operating junction temperature range – 40 to 150 ° C

J

Storage temperature range -65 to 150 ° C

stg

Load resistance (Minimum value) 3.2 kV

L

Human body model (all pins) ± 2 kV
Charged-device model (all pins) ± 500 V

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

VALUE UNIT

+0.3 – 0.3 to V

CC

+0.3 V

CC

DISSIPATION RATINGS

PACKAGE

20-pin DIP 1.87 W 15 mW/ ° C 1.20 W 0.97 W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

(1)

TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C

RECOMMENDED OPERATING CONDITIONS

V

CC

V

IH

V

IL

I

IH

I

IL

T

A

Supply voltage PVCC, AVCC 10 30 V
High-level input voltage SD, MUTE, GAIN0, GAIN1 2 V
Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V

High-level input current MUTE, VI= VCC, V

Low-level input current MUTE, VI= 0 V, V

Operating free-air temperature – 40 85 ° C

SD, VI= VCC, V

= 30 V 125

CC

= 30 V 125 µ A

CC

GAIN0, GAIN1, VI= VCC, V
SD, VI= 0, V

= 30 V 1

CC

= 30 V 1 µ A

CC

GAIN0, GAIN1, VI= 0 V, V

MIN MAX UNIT

= 24 V 125

CC

= 24 V 1

CC

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TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

DC CHARACTERISTICS

TA= 25 ° C, V

| V

| VI= 0 V, AV= 36 dB 7.5 50 mV

OS

V

(BYPASS)

I

CC(q)

I

CC(q)

I

CC(q)

r

DS(on)

G Gain dB

AC CHARACTERISTICS

TA= 25 ° C, V

K

SVR

P

O

THD+N

V

n

SNR Signal-to-noise ratio Max Output at THD+N < 1%, f = 1 kHz, Gain = 20 dB 99 dB

f

OSC

Δ t

= 24 V, RL= 4 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage
(measured differentially)

Bypass output voltage No load AV

/8 V

CC

Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mA
Quiescent supply current in mute mode MUTE = 2 V, No load 23 mA
Quiescent supply current in shutdown 1

mode

SD = 0.8 V , No load 0.39 mA

Drain-source on-state resistance 200 m Ω

Gain1 = 0.8 V

Gain1 = 2 V

Gain0 = 0.8 V 18 20 22
Gain0 = 2 V 24 26 28
Gain0 = 0.8 V 30 32 34
Gain0 = 2 V 34 36 38

Mute Attenuation VI= 1Vrms – 82

= 24V, RL= 4 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

= 12 V, V

Supply ripple rejection

Output Power at 1% THD+N

Output Power at 10%
THD+N

Total harmonic distortion +
noise

CC

Gain = 20 dB
V

= 12 V, RL= 4 Ω , f = 1 kHz 4

CC

V

= 24 V, RL= 8 Ω , f = 1 kHz 8

CC

V

= 12 V, RL= 4 Ω , f = 1 kHz 5

CC

V

= 24 V, RL= 8 Ω , f = 1 kHz 10

CC

RL= 4 Ω , f = 1 kHz, PO= 1 W 0.1%
RL= 8 Ω , f = 1 kHz, PO= 1 W 0.06%

Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

= 200 mV

ripple

PP

100 Hz – 30 dB
1 kHz -48 dB

85 µ V

– 80 dB

Crosstalk PO= 1 W, f = 1kHz; Gain = 20 dB – 60 dB

Thermal trip point 150 ° C
Thermal hysteresis 30 ° C
Oscillator frequency 10 V ≤ V

CC

230 250 270 kHz
mute delay time from mute input switches high until outputs muted 120 msec
unmute delay time from mute input switches low until outputs unmuted 120 msec

W

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LS

HS

LS

HS

OSC/RAMP

MUTE

CONTROL

BYPASS

AV

CONTROL

CONTROL

BIAS

THERMAL

SC

DETECT

SC

DETECT

AVDD

AVCC

LIN

RIN

MUTE

BYPASS

GAIN1

GAIN0

SD

BSL

PVCCL

LOUT

PGNDL

VCLAMP

BSR

PVCCR

ROUT

PGNDR

VCLAMP

VCLAMP

AVDD

AVDD

AVDD/2

AVDD

AVDD

AVDD/2

REGULATOR

AGND

+

-

+

-

FUNCTIONAL BLOCK DIAGRAM

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TPA3122D2

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f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G001

Gain = 20 dB
RL = 4 Ω (SE)
VCC = 12 V

1

10k

THD+N − %

10

PO = 1 W

PO = 0.5 W

PO = 2 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G002

Gain = 20 dB
RL = 4 Ω (SE)
VCC = 18 V

1

10k

THD+N − %

10

PO = 1 W

PO = 5 W

PO = 2.5 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G003

Gain = 20 dB
RL = 4 Ω (SE)
VCC = 24 V

1

10k

THD+N − %

10

PO = 1 W

PO = 5 W

PO = 2.5 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G004

Gain = 20 dB
RL = 8 Ω (SE)
VCC = 24 V

1

10k

THD+N − %

10

PO = 1 W

PO = 5 W

PO = 2.5 W

PO − Output Power − W

0.01 0.1 1 40

0.1

0.01

G005

1

10

THD+N − %

10

Gain = 20 dB
RL = 4 Ω (SE)

VCC = 12 V

VCC = 24 V

VCC = 18 V

PO − Output Power − W

0.01 0.1 1 40

0.1

0.01

G006

Gain = 20 dB
RL = 8 Ω (SE)

1

10

THD+N − %

10

VCC = 12 V

VCC = 24 V

VCC = 18 V

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 1. Figure 2.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER (SE) OUTPUT POWER (SE)

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Figure 5. Figure 6.

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−100

−80

−60

−40

−20

0

f − Frequency − Hz

Crosstalk −

dB

G007

20 100 1k 20k10k

Gain=20dB
PO=0.25W
RL=4 Ω (SE)
VCC=18V

RighttoLeft

LefttoRight

−100

−80

−60

−40

−20

0

f − Frequency − Hz

Crosstalk − dB

G008

Gain=20dB
PO=0.125W
RL=8 Ω (SE)
VCC=18V

20 100 1k 20k10k

RighttoLeft

LefttoRight

f − Frequency − Hz

Gain

− dBr A

G009

0

−200

200

400

Phase −

°

100 1k 100k10k

Phase

Gain

−20

−40

0

20

VCC=24V

Gain=20dB

O

P =0.125W

L

filt

=22 mH

C

filt

=0.68 Fm

C

dc

=470 Fm

RL=4 Ω (SE)

0

5

10

15

20

25

30

f − Frequency − Hz

Gain

− dBr A

G010

0

−100

−200

−300

100

200

Phase −

°

20 100 1k 200k10k

Phase

Gain

Gain=20dB
PO=0.125W
RL=8 Ω (SE)
VCC=18V

L

filt

=47 mH

C

filt

=0.22 Fm

C

dc

=470 Fm

PVCC− SupplyVoltage − V

0

5

10

15

10 12 14 16 18 20

P

O

− OutputPower

−

W

G011

THD+N=10%

THD+N=1%

Gain=20dB
R

L

=4 (SE)W

PVCC− SupplyVoltage − V

0

2

4

6

8

10

12

14

16

18

10 12 14 16 18 20 22 24 26 28 30

P

O

− OutputPower

−

W

G012

Gain=20dB
RL=8 Ω (SE)

THD+N=10%

THD+N=1%

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)

CROSSTALK CROSSTALK

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 7. Figure 8.

GAIN/PHASE GAIN/PHASE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

TPA3122D2

Figure 9. Figure 10.

OUTPUT POWER OUTPUT POWER

vs vs

SUPPLY VOLTAGE (SE) SUPPLY VOLTAGE (SE)

NOTE: Dashed line = Thermally limited

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Figure 11.

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Figure 12.