Texas Instruments TPA3122D2 Instructions Manual

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1 Fm

MuteControl

PVCCL

TPA3122D2

SIMPLIFIED APPLICATIONCIRCUIT

PVCCR

VCLAMP

GAIN1

BYPASS

1 Fm

0.22 Fm

AGND

LeftChannel

RightChannel

10Vto30V

}

4-StepGain

Control

Shutdown

Control

LIN

RIN

BSR

BSL

PGNDR

PGNDL

0.22 Fm

22 Hm

0.68 Fm

470 Fm

0.68 Fm

1 Fm

470 Fm

GAIN0

AVCC

MUTE

ROUT

LOUT

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SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

15-W STEREO CLASS-D AUDIO POWER AMPLIFIER

FEATURES APPLICATIONS

• 10-W/ch into an 4- Ω Load From a 17-V Supply

• 15-W/ch into an 8- Ω Load From a 28-V Supply

• Operates from 10 V to 30 V

• Efficient Class-D Operation

• Four Selectable, Fixed Gain Settings

• Internal Oscillator (No External Components

Required) The efficiency of the TPA3122D2 eliminates the need

• Single Ended Analog Inputs

• Thermal and Short-Circuit Protection with

Auto Recovery Feature

• 20-pin DIP Package

• Televisions

DESCRIPTION

The TPA3122D2 is a 15-W (per channel) efficient, Class-D audio power amplifier for driving stereo single ended speakers or mono bridge tied load. The TPA3122D2 can drive stereo speakers as low as 4 Ω .

for an external heat sink when playing music. The gain of the amplifier is controlled by two gain

select pins. The gain selections are 20, 26, 32, and 36 dB.

TPA3122D2

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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PVCCL

MUTE

LIN

RIN

BYPASS

AGND AGND

PVCCR

VCLAMP

PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

N (DIP) PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

NAME

SD 2 I RIN 5 I Audio input for right channel.

LIN 4 I Audio input for left channel. GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.

MUTE 3 I BSL 18 I/O Bootstrap I/O for left channel.

PVCCL 1 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. LOUT 19 O Class-D  -H-bridge positive output for left channel. PGNDL 20 Power ground for left channel H-bridge. VCLAMP 9 Internally generated voltage supply for bootstrap capacitors. BSR 13 I/O Bootstrap I/O for right channel. ROUT 12 O Class-D  -H-bridge negative output for right channel. PGNDR 11 Power ground for right channel H-bridge. PVCCR 10 Power supply for right channel H-bridge, not connected to PVCCL or AVCC. AGND 8 Analog ground for digital/analog cells in core. AGND 7 Analog Ground for analog cells in core.

BYPASS 6 O AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL

20-PIN

(DIP)

I/O DESCRIPTION

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to AVCC.

Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low = outputs enabled). TTL logic levels with compliance to AVCC.

Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via external capacitor sizing.

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TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V V V

T T T R

ESD Electrostatic Discharge

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

Supply voltage, AVCC, PVCC – 0.3 to 36 V

Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V

Analog input voltage RIN, LIN – 0.3 to 7 V

Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range – 40 to 85 ° C

Operating junction temperature range – 40 to 150 ° C

Storage temperature range -65 to 150 ° C

stg

Load resistance (Minimum value) 3.2 kV

Human body model (all pins) ± 2 kV Charged-device model (all pins) ± 500 V

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

VALUE UNIT

+0.3 – 0.3 to V

+0.3 V

DISSIPATION RATINGS

PACKAGE

20-pin DIP 1.87 W 15 mW/ ° C 1.20 W 0.97 W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

(1)

TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C

RECOMMENDED OPERATING CONDITIONS

Supply voltage PVCC, AVCC 10 30 V High-level input voltage SD, MUTE, GAIN0, GAIN1 2 V Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V

High-level input current MUTE, VI= VCC, V

Low-level input current MUTE, VI= 0 V, V

Operating free-air temperature – 40 85 ° C

SD, VI= VCC, V

= 30 V 125

= 30 V 125 µ A

GAIN0, GAIN1, VI= VCC, V SD, VI= 0, V

= 30 V 1

= 30 V 1 µ A

GAIN0, GAIN1, VI= 0 V, V

MIN MAX UNIT

= 24 V 125

= 24 V 1

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TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

DC CHARACTERISTICS

TA= 25 ° C, V

| V

| VI= 0 V, AV= 36 dB 7.5 50 mV

(BYPASS)

CC(q)

DS(on)

G Gain dB

AC CHARACTERISTICS

TA= 25 ° C, V

SVR

THD+N

SNR Signal-to-noise ratio Max Output at THD+N < 1%, f = 1 kHz, Gain = 20 dB 99 dB

OSC

Δ t

= 24 V, RL= 4 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage (measured differentially)

Bypass output voltage No load AV

/8 V

Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mA Quiescent supply current in mute mode MUTE = 2 V, No load 23 mA Quiescent supply current in shutdown 1

mode

SD = 0.8 V , No load 0.39 mA

Drain-source on-state resistance 200 m Ω

Gain1 = 0.8 V

Gain1 = 2 V

Gain0 = 0.8 V 18 20 22 Gain0 = 2 V 24 26 28 Gain0 = 0.8 V 30 32 34 Gain0 = 2 V 34 36 38

Mute Attenuation VI= 1Vrms – 82

= 24V, RL= 4 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 12 V, V

Supply ripple rejection

Output Power at 1% THD+N

Output Power at 10% THD+N

Total harmonic distortion + noise

Gain = 20 dB V

= 12 V, RL= 4 Ω , f = 1 kHz 4

= 24 V, RL= 8 Ω , f = 1 kHz 8

= 12 V, RL= 4 Ω , f = 1 kHz 5

= 24 V, RL= 8 Ω , f = 1 kHz 10

RL= 4 Ω , f = 1 kHz, PO= 1 W 0.1% RL= 8 Ω , f = 1 kHz, PO= 1 W 0.06%

Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

= 200 mV

ripple

100 Hz – 30 dB 1 kHz -48 dB

85 µ V

– 80 dB

Crosstalk PO= 1 W, f = 1kHz; Gain = 20 dB – 60 dB

Thermal trip point 150 ° C Thermal hysteresis 30 ° C Oscillator frequency 10 V ≤ V

230 250 270 kHz mute delay time from mute input switches high until outputs muted 120 msec unmute delay time from mute input switches low until outputs unmuted 120 msec

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OSC/RAMP

MUTE

CONTROL

BYPASS

CONTROL

BIAS

THERMAL

DETECT

AVDD

AVCC

LIN

RIN

MUTE

BYPASS

GAIN1

GAIN0

BSL

PVCCL

LOUT

PGNDL

VCLAMP

BSR

PVCCR

ROUT

PGNDR

VCLAMP

AVDD

AVDD/2

AVDD

AVDD/2

REGULATOR

AGND

FUNCTIONAL BLOCK DIAGRAM

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TPA3122D2

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f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G001

Gain = 20 dB RL = 4 Ω (SE) VCC = 12 V

10k

THD+N − %

PO = 1 W

PO = 0.5 W

PO = 2 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G002

Gain = 20 dB RL = 4 Ω (SE) VCC = 18 V

10k

THD+N − %

PO = 1 W

PO = 5 W

PO = 2.5 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G003

Gain = 20 dB RL = 4 Ω (SE) VCC = 24 V

10k

THD+N − %

PO = 1 W

PO = 5 W

PO = 2.5 W

f − Frequency − Hz

20 100 1k 20k

0.1

0.01

G004

Gain = 20 dB RL = 8 Ω (SE) VCC = 24 V

10k

THD+N − %

PO = 1 W

PO = 5 W

PO = 2.5 W

PO − Output Power − W

0.01 0.1 1 40

0.1

0.01

G005

THD+N − %

Gain = 20 dB RL = 4 Ω (SE)

VCC = 12 V

VCC = 24 V

VCC = 18 V

PO − Output Power − W

0.01 0.1 1 40

0.1

0.01

G006

Gain = 20 dB RL = 8 Ω (SE)

THD+N − %

VCC = 12 V

VCC = 24 V

VCC = 18 V

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 1. Figure 2.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER (SE) OUTPUT POWER (SE)

Figure 5. Figure 6.

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−100

−80

−60

−40

−20

f − Frequency − Hz

Crosstalk −

G007

20 100 1k 20k10k

Gain=20dB PO=0.25W RL=4 Ω (SE) VCC=18V

RighttoLeft

LefttoRight

−100

−80

−60

−40

−20

f − Frequency − Hz

Crosstalk − dB

G008

Gain=20dB PO=0.125W RL=8 Ω (SE) VCC=18V

20 100 1k 20k10k

RighttoLeft

LefttoRight

f − Frequency − Hz

Gain

− dBr A

G009

−200

200

400

Phase −

100 1k 100k10k

Phase

Gain

−20

−40

VCC=24V

Gain=20dB

P =0.125W

filt

=22 mH

filt

=0.68 Fm

=470 Fm

RL=4 Ω (SE)

f − Frequency − Hz

Gain

− dBr A

G010

−100

−200

−300

100

200

Phase −

20 100 1k 200k10k

Phase

Gain

Gain=20dB PO=0.125W RL=8 Ω (SE) VCC=18V

filt

=47 mH

filt

=0.22 Fm

=470 Fm

PVCC− SupplyVoltage − V

10 12 14 16 18 20

− OutputPower

−

G011

THD+N=10%

THD+N=1%

Gain=20dB R

=4 (SE)W

PVCC− SupplyVoltage − V

10 12 14 16 18 20 22 24 26 28 30

− OutputPower

−

G012

Gain=20dB RL=8 Ω (SE)

THD+N=10%

THD+N=1%

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)

CROSSTALK CROSSTALK

vs vs

FREQUENCY (SE) FREQUENCY (SE)

Figure 7. Figure 8.

GAIN/PHASE GAIN/PHASE

vs vs

FREQUENCY (SE) FREQUENCY (SE)

TPA3122D2

Figure 9. Figure 10.

OUTPUT POWER OUTPUT POWER

vs vs

SUPPLY VOLTAGE (SE) SUPPLY VOLTAGE (SE)

NOTE: Dashed line = Thermally limited

Figure 11.

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Figure 12.

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PO − Output Power − W

100

0 1 2 3 4 5 6 7

Efficiency − %

G013

Gain = 20 dB RL = 4 Ω (SE) VCC = 12 V

PO − Output Power − W

100

0 2 4 6 8 10 12 14

Efficiency − %

G014

Gain = 20 dB RL = 8 Ω (SE)

VCC = 12 V

VCC = 18 V

VCC = 24 V

PO − T otal Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 2 4 6 8 10 12 14

− Supply Current − A

G015

Gain = 20 dB RL = 4 Ω (SE) VCC = 12 V

PO − T otal Output Power − W

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 2 4 6 8 10 12 14

− Supply Current − A

G016

Gain = 20 dB RL = 8 Ω (SE)

VCC = 18 V

VCC = 24 V

VCC = 12 V

−120

−100

−80

−60

−40

−20

f − Frequency − Hz

PSRR − dB

G017

Gain = 20 dB R

= 4 Ω (SE)

= 12 V

ripple

= 200 mV

p-p

20 100 1k 20k10k

f − Frequency − Hz

0.1

0.01

0.001

G018

Gain=20dB RL=8 Ω (BTL) VCC=24V

THD+N − %

PO=20W

PO=1W

PO=5W

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY EFFICIENCY

OUTPUT POWER (SE) OUTPUT POWER (SE)

vs vs

Figure 13. Figure 14.

SUPPLY CURRENT SUPPLY CURRENT

vs vs

TOTAL OUTPUT POWER (SE) TOTAL OUTPUT POWER (SE)

Figure 15. Figure 16.

POWER SUPPLY REJECTION RATIO TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY (SE) FREQUENCY (BTL)

Figure 17. Figure 18.

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−30

−20

−10

f − Frequency − Hz

Gain

− dBr A

G020

−400

−500

−600

−700

−300

−200

Phase −

20 100 1k 200k10k

Phase

Gain

Gain=20dB PO=0.125W RL=8 Ω (BTL) VCC=24V

filt

=33 mH

filt

=1 Fm

PO − Output Power − W

0.1

0.01

0.001

G019

Gain = 20 dB RL = 8 Ω (BTL)

THD+N − %

0.01 0.1 1 5010

VCC = 24 V

VCC = 18 V

VCC = 12 V

PVCC − Supply Voltage − V

10 12 14 16 18 20 22 24 26 28 30

− Output Power − W

G021

Gain = 20 dB RL = 8 Ω (BTL)

THD+N = 10%

THD+N = 1%

PO − Output Power − W

100

0 4 8 12 16 20 24 28

Efficiency − %

G022

Gain = 20 dB RL = 8 Ω (BTL)

VCC = 12 V

VCC = 18 V

VCC = 24 V

PO − T otal Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 4 8 12 16 20 24 28

− Supply Current − A

G023

Gain = 20 dB RL = 8 Ω (BTL)

VCC = 24 V

VCC = 12 V

VCC = 18 V

−120

−100

−80

−60

−40

−20

f − Frequency − Hz

PSRR − dB

G024

Gain = 20 dB RL = 8 Ω (BTL) VCC = 24 V V

ripple

= 200 mV

p-p

20 100 1k 20k10k

TYPICAL CHARACTERISTICS (continued)

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

TOTAL HARMONIC DISTORTION + NOISE GAIN/PHASE

vs vs

OUTPUT POWER (BTL) FREQUENCY (BTL)

Figure 19. Figure 20.

OUTPUT POWER EFFICIENCY

vs vs

SUPPLY VOLTAGE (BTL) OUTPUT POWER (BTL)

Figure 21. Figure 22.

SUPPLY CURRENT POWER SUPPLY REJECTION RATIO

vs vs

TOTAL OUTPUT POWER (BTL) FREQUENCY (BTL)

Figure 23. Figure 24.

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0V

-12V

+12V

Current

OUTP

DifferentialVoltage

AcrossLoad

OUTN

0V

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

APPLICATION INFORMATION

CLASS-D OPERATION

This section focuses on the class-D operation of the TPA3122D2.

Traditional Class-D Modulation Scheme

The TPA3122D2 operates in AD mode. There are two main configurations that may be used. For stereo operation, the TPA3122D2 should be configured in a single-ended (SE) half bridge amplifier. For mono applications, TPA3122D2 may be used as a bridge tied load (BTL) amplifier. The traditional class-D modulation scheme, which is used in the TPA3122D2 BTL configuration, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, V output varies between positive and negative V

, where filtered 50% duty cycle yields

0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in

Figure 25 .

. Therefore, the differential pre-filtered

Supply Pumping

One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate, which temporarily shuts down the audio output.

Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out of phase 180 ° and reverse the speaker connections. Because most audio is highly correlated, this causes the supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby, sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at low frequencies and high output levels.

Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3122D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside

the amplifier. This causes the input impedance (Z are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ± 20% due to shifts in the actual resistance of the input resistors.

Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an

Inductive Load With No Input

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) to be dependent on the gain setting. The actual gain settings

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Input

Signal

f=

2 Z Cp

i i

f =

2 Z Cp

i i

–3dB

C =

2 Z fp

i c

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 8 k Ω , which is the absolute minimum input impedance of the TPA3122D2. At the higher gain settings, the input impedance could increase as high as 72 k Ω

Table 1. Gain Setting

GAIN1 GAIN0

0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9

INPUT RESISTANCE

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 k Ω ± 20%, to the largest value, 60 k Ω ± 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps.

AMPLIFIER GAIN (dB) INPUT IMPEDANCE (k Ω )

TYPICAL TYPICAL

The -3-dB frequency can be calculated using Equation 1 . Use the ZIvalues given in Table 1 .

INPUT CAPACITOR, C

In the typical application, an input capacitor I) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C high-pass filter with the corner frequency determined in Equation 2 .

The value of C

is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider

the example where ZIis 20 k Ω and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3 .

In this example, CIis 0.4 µF; so, one would likely choose a value of 0.47 µ F as this value is commonly used. If the gain is known and is constant, use ZIfrom Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network I) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially

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and the input impedance of the amplifier (Z

) form a

(1)

(2)

(3)

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LOUT /ROUT

filter

LOUT

filter

ROUT

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly.

Single Ended Output Capacitor, C

In single ended (SE) applications, the DC blocking capacitor forms a high pass filter with speaker impedance. The frequency response rolls of with decreasing frequency at a rate of 20dB/decade. The cutoff frequency is determined by

fc = 1/2 × π CoZ

Table 2 shows some common component values and the associated cutoff frequencies:

Table 2. Common Filter Responses

– DC Blocking Capacitor ( µ F)

Speaker Impedance ( Ω )

fc= 60 Hz fc= 40 Hz fc= 20 Hz

4 680 1000 2200 8 330 470 1000

Output Filter and Frequency Response

For the best frequency response, a flat passband output filter (second order Butterworth) may be used. The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins. There are several possible configurations depending on the speaker impedance and whether the output configuration is Single Ended (SE) or Bridge Tied Load (BTL). Table 3 list several possible arrangements.

Table 3. Recommended Filter Output Components

Output Configuration Speaker Impedance ( Ω ) Filter Inductor ( µ H) Filter Capacitor (nF)

Single Ended (SE)

Bridge Tied Load

4 22 680 8 47 390 4 10 1500 8 22 680

Figure 26. BTL Filter Configuration Figure 27. SE Filter Configuration

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TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

Power Supply Decoupling, C

The TPA3122D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ F to 1 µF placed as close as possible to the device V

lead works best. For

filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µ F or greater placed near the audio power amplifier is recommended. The 220- µ F capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-µF capacitor on the AVCC terminal is adequate.

BSN and BSP Capacitors

The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.

The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

VCLAMP Capacitor

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one internal regulator clamps the gate voltage. One 1- µ F capacitor must be connected from VCLAMP (pin 11 for PWP and pin 9 for DIP package) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with V

and may not be used for powering any other circuitry.

Capacitor Selection

BYP

The scaled supply reference (V external capacitor for this reference C start-up or recovery from shutdown mode, C

) nominally provides an AVcc/8 internal bias for the preamplifier stages. The

BYP

) is a critical component and serves several important functions. During

BYP

determines the rate at which the amplifier starts up. The second

BSP

function is to reduce noise produced by the power supply caused by coupling with the output drive signal. This noise could result in degraded PSRR and THD + N.

The circuit is designed for a C

value of 1 µ F for best pop performance. The inputs caps should be the same

BSP

value. A ceramic or tantalum low-ESR capacitor is recommended.

SHUTDOWN OPERATION

The TPA3122D2 employs a shutdown mode of operation designed to reduce supply current (I minimum level during periods of non-use for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable.

For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the power supply voltage.

) to the absolute

MUTE Operation

The MUTE pin is an input for controlling the output state of the TPA3122D2. A logic high on this terminal causes the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or switching between different audio sources.

The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level.

Product Folder Link(s) :TPA3122D2

www.ti.com

RIGHT_OUT

LEFT_OUT

VCC

ShutdownControl

MuteControl

LeftInput

RightInput

470uF470uF

0.68uF0.68uF

0.22uF0.22uF

4.7K4.7K

22uH22uH

10uF10uF

0.1uF0.1uF

470uF470uF

1.0uF1.0uF

0.22uF0.22uF

TPA3122_PDIPTPA3122_PDIP

PVCCL

MUTE

LIN

RIN

BYPASS

AGND1

AGND2

VCLAMP

PVCCR10PGNDR

ROUT

BSR

GAIN1

GAIN0

AVCC2

AVCC1

BSL

LOUT

PGNDL

1.0uF1.0uF

470uF470uF

1.0uF1.0uF

0.68uF0.68uF

0.1uF0.1uF

4.7K4.7K

22uH22uH

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

SHORT-CIRCUIT PROTECTION

The TPA3122D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is removed.

THERMAL PROTECTION

Thermal protection on the TPA3122D2 prevents damage to the device when the internal die temperature exceeds 150 ° C. There is a ± 15 ° C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30 ° C. The device begins normal operation at this point with no external system interaction.

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3122D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.

• Decoupling capacitors — The high-frequency 0.1µF decoupling capacitors should be placed as close to the PVCC (pins 1 and 10) and AVCC (pins 16 and 17) terminals as possible. The VBYP (pin 6) capacitor and VCLAMP (pin 9) capacitor should also be placed as close to the device as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3122D2 on the PVCCL and PVCCR terminals.

• Grounding — The AVCC (pins 16 and 17) decoupling capacitor and VBYP (pin 6) capacitor should each be grounded to analog ground (AGND, pins 7 and 8). The PVCCx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 11 and 20). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3122D2.

• Output filter — The EMI filter (L1, L2, C9, and C16) should be placed as close to the output terminals as possible for the best EMI performance. The capacitors should be grounded to power ground.

For an example layout, see the TPA3122D2 Evaluation Module (TPA3122D2EVM) User Manual, (SLOU214 ). Both the EVM user manual and the thermal pad application note are available on the TI Web site at

http://www.ti.com .

Figure 28. SE 4- Ω Application Schematic

Product Folder Link(s) :TPA3122D2

www.ti.com

RIGHT_OUT

LEFT_OUT

VCC

ShutdownControl

MuteControl

PlusInput

MinusInput

0.68uF0.68uF

4.7K4.7K

0.22uF0.22uF

10uF10uF

22uH22uH

0.1uF0.1uF

1.0uF1.0uF

470uF470uF

1.0uF1.0uF

TPA3122_PDIPTPA3122_PDIP

PVCCL

MUTE

LIN

RIN

BYPASS

AGND1

AGND2

VCLAMP

PVCCR10PGNDR

ROUT

BSR

GAIN1

GAIN0

AVCC2

AVCC1

BSL

LOUT

PGNDL

0.22uF0.22uF

470uF470uF1.0uF1.0uF

0.1uF0.1uF

0.68uF0.68uF

4.7K4.7K

0.1uF0.1uF

22uH22uH

Figure 29. BTL 8- Ω Application Schematic

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:

• Audio analyzer or spectrum analyzer

• Digital multimeter (DMM)

• Oscilloscope

• Twisted-pair wires

• Signal generator

• Power resistor(s)

• Linear regulated power supply

• Filter components

• EVM or other complete audio circuit

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

Figure 30 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine

wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, C

), so no additional coupling is required. The generator output impedance should be low to avoid

attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer-input impedance should be high. The output resistance, R milliohms and can be ignored for all but the power-related calculations.

Figure 30 (a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal

output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 30 (b), which requires low-pass filters in most

cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.

Product Folder Link(s) :TPA3122D2

, of the APA is normally in the hundreds of

OUT

www.ti.com

Analyzer

20Hz-20kHz

(a)BasicClass-AB

APA

Signal

Generator

PowerSupply

Analyzer

20Hz-20kHz

(b)TraditionalClass-D

Class-D APA

Signal

Generator

PowerSupply

filt

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

Figure 30. Audio Measurement Systems

Product Folder Link(s) :TPA3122D2

www.ti.com

GEN

Twisted-PairWire

Generator

EvaluationModule

AudioPower

Amplifier

Twisted-PairWire

ANA

Analyzer

ANA

filt

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

SE Input and SE Output (TPA3122D2 Stereo Configuration)

The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE measurement circuit is shown in Figure 31 . SE inputs normally have one input pin per channel. In some cases, two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through an output ac coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.

The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that will effect the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode noise in the measurement.

Figure 31. SE Input — SE Output Measurement Circuit

The following general rules should be followed when connecting to APAs with SE inputs and outputs:

• Use an unbalanced source to supply the input signal.

• Use an analyzer with balanced inputs.

• Use twisted pair wire for all connections.

• Use shielding when the system environment is noisy.

• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large

currents (see Table 4 )

Product Folder Link(s) :TPA3122D2

www.ti.com

AudioPower

Amplifier

Generator

GEN

Analyzer

ANA

Twisted-PairWire

EvaluationModule

Twisted-PairWire

filt

TPA3122D2

SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007

DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3122D2 Mono Configuration)

Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in Figure 32 . The differential input is a balanced input, meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the SE output equates to a balanced output.

Figure 32. Differential Input, BTL Output Measurement Circuit

The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:

• Use a balanced source to supply the input signal.

• Use an analyzer with balanced inputs.

• Use twisted-pair wire for all connections.

• Use shielding when the system environment is noisy.

• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large

currents (see Table 4 ).

Table 4 shows the recommended wire size for the power supply and load cables of the APA system. The real

concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25 ° C.

Table 4. Recommended Minimum Wire Size for Power Cables

(W) RL( Ω ) AWG Size

OUT

10 4 18 22 16 40 18 42

2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1

< 0.75 8 22 28 1.5 6.1 1.6 6.2

Product Folder Link(s) :TPA3122D2

DC POWER LOSS AC POWER LOSS

(MW) (MW)

PACKAGE OPTION ADDENDUM

www.ti.com

10-Apr-2008

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TPA3122D2N ACTIVE PDIP N 20 20 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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Texas Instruments TPA3122D2 Instructions Manual

Specifications and Main Features

Frequently Asked Questions

User Manual