Texas Instruments TPA3111D1 Schematic [ru]

INP

INN

SDSD

FaultFault

PLIMITPLIMIT

PVCC 8to26V

1uF

OUTN

FERRITE

BEAD

FILTER

OUTP

10W

8Ω

OUTN

FERRITE

BEAD

FILTER

FERRITE

BEAD

FILTER

OUTP

10W

8Ω

OUT+

-

OUT

Audio
Source

TPA3111D1

GAIN0

GAIN0
GAIN1GAIN1

TPA3111D1

www.ti.com

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

10-W FILTER-FREE MONO CLASS-D AUDIO POWER AMPLIFIER with SPEAKER GUARD™

Check for Samples: TPA3111D1

1

FEATURES

2

• 10-W into an 8-Ω Load at 10% THD+N From a
12-V Supply

• 7-W into an 4-Ω Load at 10% THD+N From a 8­V Supply

• 94% Efficient Class-D Operation into 8-Ω Load
Eliminates Need for Heat Sinks

• Wide Supply Voltage Range Allows Operation
from 8 to 26 V

• Filter-Free Operation

• SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter plus DC Protection

• Flow Through Pin Out Facilitates Easy Board
Layout

• Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection with Auto-Recovery Option

• Excellent THD+N/ Pop Free Performance

• Four Selectable, Fixed Gain Settings

• Differential Inputs

APPLICATIONS

• Televisions

• Monitor/Laptop

• Consumer Audio Equipment

DESCRIPTION

The TPA3111D1 is a 10-W efficient, Class-D audio
power amplifier for driving a bridge tied speaker.
Advanced EMI Suppresion Technology enables the
use of inexpensive ferrite bead filters at the outputs
while meeting EMC requirements. SpeakerGuard™
speaker protection system includes an adjustable
power limiter and a DC detection circuit. The
adjustable power limiter allows the user to set a
"virtual" voltage rail lower than the chip supply to limit
the amount of current through the speaker. The DC
detect circuit measures the frequency and amplitude
of the PWM signal and shuts off the output stage if
the input capacitors are damaged or shorts exist on
the inputs.

The TPA3111D1 can drive a mono speaker as low as
4Ω. The high efficiency of the TPA3111D1, > 90%,
eliminates the need for an external heat sink when
playing music.

The outputs are fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an auto­recovery feature.

Figure 1. Simplified Application Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SpeakerGuard is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009–2012, Texas Instruments Incorporated

TPA3111D1

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

V

T
T
T
R

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
(3) The TPA3111D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

(4) In accordance with JEDEC Standard 22, Test Method A114-B.
(5) In accordance with JEDEC Standard 22, Test Method C101-A

Supply voltage AVCC, PVCC –0.3 V to 30 V

CC

SD, FAULT,GAIN0, GAIN1, AVCC (Pin 14)

Interface pin voltage

I

PLIMIT –0.3 V toGVDD + 0.3 V

INN, INP –0.3 V to 6.3 V
Continuous total power dissipation See Thermal Inforamtion Table
Operating free-air temperature range –40°C to 85°C

A

Operating junction temperature range

J

Storage temperature range –65°C to 150°C

stg

Minimum Load Resistance BTL 3.2

L

Electrostatic discharge

(3)

Human body model

Charged-device model

(4)

(all pins) ±2 kV

(5)

only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

with the pins.
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.

(1)

UNIT

(2)

–0.3 V to VCC+ 0.3 V

< 10 V/ms

–40°C to 150°C

(all pins) ±500 V

THERMAL INFORMATION

(1) (2)

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 30.3
Junction-to-case (top) thermal resistance 33.5
Junction-to-board thermal resistance 17.5
Junction-to-top characterization parameter 0.9
Junction-to-board characterization parameter 7.2
Junction-to-case (bottom) thermal resistance 0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

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TPA3111D1

PWP (28 PINS)

UNITS

°C/W

TPA3111D1

www.ti.com

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

V
V
V
V
I
I
T

Supply voltage PVCC, AVCC 8 26 V

CC

High-level input voltage SD, GAIN0, GAIN1 2 V

IH

Low-level input voltage SD, GAIN0, GAIN1 0.8 V

IL

Low-level output voltage FAULT, R

OL

High-level input current SD, GAIN0, GAIN1, VI= 2, VCC= 18 V 50 µA

IH

Low-level input current SD, GAIN0, GAIN1, VI= 0.8V, VCC= 18 V 5 µA

IL

Operating free-air temperature –40 85 °C

A

= 100kΩ, VCC=26V 0.8 V

PULLUP

DC CHARACTERISTICS

TA= 25°C, VCC= 24 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

| VOS| VI= 0 V, Gain = 36 dB 1.5 15 mV
I

CC

I

CC(SD)

r

DS(on)

G Gain

t

ON

t

OFF

GVDD Gate Drive Supply I

Class-D output offset voltage (measured
differentially)

Quiescent supply current SD = 2 V, no load, PVcc=21V 40 mA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=21V 400 µA

Drain-source on-state resistance mΩ

IO= 500 mA,
TJ= 25°C

GAIN1 = 0.8 V dB

GAIN1 = 2 V dB

High Side 240
Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN0 = 2 V 25 26 27
GAIN0 = 0.8 V 31 32 33

GAIN0 = 2 V 35 36 37
Turn-on time SD = 2 V 10 ms
Turn-off time SD = 0.8 V 2 μs

= 2mA 6.5 6.9 7.3 V

GVDD

DC CHARACTERISTICS

TA= 25°C, VCC= 12 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

| VOS| VI= 0 V, Gain = 36 dB 1.5 15 mV
I

CC

I

CC(SD)

r

DS(on)

G Gain

t

ON

t

OFF

GVDD Gate Drive Supply I
PLIMIT Output Voltage maximum under PLIMIT V

Class-D output offset voltage (measured
differentially)

Quiescent supply current SD = 2 V, no load, PVcc=12V 20 mA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=12V 200 µA

Drain-source on-state resistance mΩ

IO= 500 mA,
TJ= 25°C

GAIN1 = 0.8 V dB

GAIN1 = 2 V dB

High Side 240

Low side 240

GAIN0 = 0.8 V 19 20 21

GAIN0 = 2 V 25 26 27

GAIN0 = 0.8 V 31 32 33

GAIN0 = 2 V 35 36 37
Turn-on time SD = 2 V 10 ms
Turn-off time SD = 0.8 V 2 μs

= 2mA 6.5 6.9 7.3 V

GVDD

=2.0 V; VI=6.0V differential 6.75 7.90 8.75 V

control

PLIMIT

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Product Folder Links: TPA3111D1

1

2

3

4

5

6

7

8

9

10

28

27

26

25

24

23

22

21

20

19

SD

FAULT

GND

GND
GAIN0
GAIN1

AVCC

AGND

GVDD

PLIMIT

PVCC
PVCC

BSN
OUTN
PGND
OUTN

BSN
BSP
OUTP
PGND

PWP (TSSOP)Package

(TopView)

INN

INP

NC

11

12

13

14

18

17

16

15

OUTP

BSP
PVCC
PVCC

AVCC

TPA3111D1

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

www.ti.com

AC CHARACTERISTICS

TA= 25°C, VCC= 24 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

K
P

Power Supply ripple rejection –70 dB

SVR

Continuous output power THD+N ≤ 0.1%, f = 1 kHz, VCC= 24 V 10 W

O

THD+N Total harmonic distortion + noise VCC= 24 V, f = 1 kHz, PO= 5 W (half-power) <0.05 %

V

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

n

Crosstalk VO= 1 Vrms, Gain = 20 dB, f = 1 kHz –70 dB
SNR Signal-to-noise ratio 102 dB
f

OSC

Oscillator frequency 250 310 350 kHz

Thermal trip point 150 °C

Thermal hysteresis 15 °C

200 mVPPripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND

65 µV

–80 dBV

Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted

AC CHARACTERISTICS

TA= 25°C, VCC= 12 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

K
P

P

Supply ripple rejection –70 dB

SVR

Continuous output power THD+N ≤ 10%, f = 1 kHz , RL= 8Ω 10 W

O

Continuous output power THD+N ≤ 0.1%, f = 1 kHz , RL= 4Ω 10 W

O

THD+N Total harmonic distortion + noise RL= 8 Ω, f = 1 kHz, PO= 5 W (half-power) <0.06 %

V

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

n

Crosstalk Po= 1 W, Gain = 20 dB, f = 1 kHz –70 dB
SNR Signal-to-noise ratio 102 dB
f

OSC

Oscillator frequency 250 310 350 kHz

Thermal trip point 150 °C

Thermal hysteresis 15 °C

200 mVPPripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND

65 µV

–80 dBV

Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted

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TPA3111D1

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SLOS618E –AUGUST 2009–REVISED AUGUST 2012

PIN FUNCTIONS

PIN

NAME Pin #

SD 1 I

FAULT 2 O

GND 3 Connect to local ground
GND 4 Connect to local ground
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
AVCC 7 P Analog supply.
AGND 8 Analog supply ground. Connect to the thermal pad.

GVDD 9 O

PLIMIT 10 I
INN 11 I Negative audio input. Biased at 3V.

INP 12 I Positive audio input. Biased at 3V.
NC 13 Not connected
AVCC 14 P Connect AVCC supply to this pin
PVCC 15 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 16 P Power supply for H-bridge. PVCC pins are also connected internally.
BSP 17 I Bootstrap I/O for positive high-side FET.
OUTP 18 O Class-D H-bridge positive output.
PGND 19 Power ground for the H-bridges.
OUTP 20 O Class-D H-bridge positive output.
BSP 21 I Bootstrap I/O for positive high-side FET.
BSN 22 I Bootstrap I/O for negative high-side FET.
OUTN 23 O Class-D H-bridge negative output.
PGND 24 Power ground for the H-bridges.
OUTN 25 O Class-D H-bridge negative output.
BSN 26 I Bootstrap I/O for negative high-side FET.
PVCC 27 P Power supply for H-bridge. PVCC pins are also connected internally.
PVCC 28 P Power supply for H-bridge. PVCC pins are also connected internally.

I/O DESCRIPTION

Shutdown logic input for audio amp(LOW = outputs Hi-Z, HIGH = outputs enabled).
TTL logic levels with compliance to AVCC.

Open drain output used to display short circuit or dc detect fault status. Voltage
compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting
FAULT pin to SD pin. Otherwise bothe short circuit faults and dc detect faults must
be reset by cycling PVCC.

High-side FET gate drive supply. Nominal voltage is 7V. May also be used as
supply for PLILMIT divider. Add a 1μF cap to ground at this pin.

Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a
1μF cap to ground at this pin.

Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TPA3111D1

PWM
Logic

Gate
Drive

PVCC

PVCC

GVDD

BSP

PGND

OUTP

Gate
Drive

PVCC

PVCC

GVDD

BSN

PGND

OUTN

INP

INN

UVLO/OVLO

SC Detect

DC Detect

Thermal

Detect

Startup Protection

Logic

Biases and
References

FAULT

SD

GAIN0

PLIMIT

AGND

AVCC

GAIN1

Gain

Control

TTL

Buffer

Ramp

Generator

AVDD

GVDD

GVDD

LDO

Regulator

Gain

Control

PLIMIT

PLIMIT

Reference

OUTP FB

OUTN FB

OUTN FB

OUTP FB

TPA3111D1

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

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Product Folder Links: TPA3111D1

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G003

PO = 10 W

Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH

PO = 1 W

PO = 5 W

PO − Output Power − W

0.01 0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

20

0.01

1

G004

f = 1 kHz

Gain = 20 dB
VCC = 12 V
ZL = 8 Ω + 66 µH

f = 20 Hz

f = 10 kHz

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G001

PO = 2.5 W

PO = 5 W

Gain = 20 dB
VCC = 12 V
ZL = 8 Ω + 66 µH

PO = 1 W

f − Frequency − Hz

20 100 1k 10k

THD − Total Harmonic Distortion − %

0.001

0.1

10

20k

0.01

1

G002

Gain = 20 dB
VCC = 24 V
ZL = 8 Ω + 66 µH

PO = 10 W

PO = 5 W

PO = 1 W

TPA3111D1

www.ti.com

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

TYPICAL CHARACTERISTICS

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is

available at ti.com.)

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

vs vs

FREQUENCY FREQUENCY

Figure 2. Figure 3.

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY OUTPUT POWER

Figure 4. Figure 5.

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V

PLIMIT

− PLIMIT Voltage − V

0

5

10

15

20

25

0.0 0.5 1.0 1.5 2.0 2.5 3.0

P

O(Max)

− Maximum Output Power − W

G007

Gain = 20 dB
VCC = 24 V
ZL = 8 Ω + 66 µH

V

PLIMIT

− PLIMIT Voltage − V

0

5

10

15

20

0.0 0.5 1.0 1.5 2.0

P

O

− Output Power − W

G008

Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH

PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

0.01

1

G005

f = 1 kHz

Gain = 20 dB
VCC = 24 V
ZL = 8 Ω + 66 µH

f = 20 Hz

f = 10 kHz

0.01 0.1 1 10 20

0.01 0.1 1 10 20
PO − Output Power − W

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.1

10

0.01

1

G006

f = 1 kHz

Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH

f = 20 Hz

f = 10 kHz

TPA3111D1

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is
available at ti.com.)

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 6. Figure 7.

MAXIMUM OUTPUT POWER OUTPUT POWER

vs vs

PLIMIT VOLTAGE PLIMIT VOLTAGE

Note: Dashed line represents thermally limited region.

Figure 8. Figure 9.

Note: Dashed line represents thermally limited region.

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PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8 9 10

η − Efficiency − %

G013

Gain = 20 dB
VCC = 12 V
ZL = 4 Ω + 33 µH

P

O(Tot)

− Total Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0 1 2 3 4 5 6 7 8 9 10

I

CC

− Supply Current − A

G014

VCC = 12 V

VCC = 24 V

Gain = 20 dB
ZL = 8 Ω + 66 µH

PO − Output Power − W

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8 9 10

η − Efficiency − %

G012

VCC = 24 V

Gain = 20 dB
ZL = 8 Ω + 66 µH

VCC = 12 V

f − Frequency − Hz

Phase − °

100

50

0

−300

0

5

10

15

20

25

30

35

40

Gain − dB

−50

−100

−150

10 100 10k 100k1k

G009

Phase

Gain

−200

−250

CI = 1 µF
Gain = 20 dB
Filter = Audio Precision AUX-0025
VCC = 12 V
VI = 0.1 Vrms
ZL = 8 Ω + 66 µH

TPA3111D1

www.ti.com

SLOS618E –AUGUST 2009–REVISED AUGUST 2012

TYPICAL CHARACTERISTICS (continued)

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3110D2 EVM which is
available at ti.com.)

GAIN/PHASE EFFICIENCY

vs vs

FREQUENCY OUTPUT POWER

OUTPUT POWER TOTAL OUTPUT POWER

Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 10. Figure 11.

EFFICIENCY SUPPLY CURRENT

vs vs

Figure 12. Figure 13.

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