TEXAS INSTRUMENTS TPA3101D2 Technical data
QFN
HTQFP
Simplified ApplicationCircuit
TV Audio
Processor
RINP
BSRN
BSRP
VCLAMPR
VCLAMPL
PGNDR
PGNDL
VREG
VBYP
ROSC
BSLN
ROUTN
LOUTN
LOUTP
BSLP
ROUTP
TPA3101D2
LINN
RINN
LINP
MUTE
GAIN0
GAIN1
SYNC
FAULT
PVCCR
PVCCL
AVCC
AGND
MSTR/SLV
SHUTDOWN
Shutdown
Control
MuteControl
SyncControl
FaultFlag
10Vto26V
GainSelect
1 Fm
1 Fm
1 Fm
1 Fm
10nF
100kW
0.22 Fm
0.22 Fm
0.22 Fm
0.22 Fm
1 Fm
1 Fm
1 Fm
TPA3101D2
www.ti.com
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
10-W STEREO CLASS-D AUDIO POWER AMPLIFIER
1
FEATURES APPLICATIONS
• 10-W/ch into an 8- Ω Load From a 13-V Supply
• 9.2-W/ch into an 8- Ω Load From a 12-V Supply
• Operates from 10 V to 26 V
• 87% Efficient Class-D Operation Eliminates
Need for Heat Sinks
• Four Selectable, Fixed Gain Settings
• Differential Inputs TPA3101D2, 87%, eliminates the need for an
• Thermal and Short-Circuit Protection With
Auto Recovery Feature
• Clock Output for Synchronization With
Multiple Class-D Devices
• Surface Mount 7 mm × 7 mm, 48-pin QFN
Package
• Surface Mount 7 mm × 7 mm, 48-pin HTQFP
Package
• Televisions
DESCRIPTION
The TPA3101D2 is a 10-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. The TPA3101D2 can drive stereo
speakers as low as 4 Ω . The high efficiency of the
external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The outputs are fully protected against shorts to
GND, V
recovery feature and monitor output.
, and output-to-output shorts with an auto
CC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005 – 2007, Texas Instruments Incorporated
www.ti.com
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
V
T
T
T
R
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
(2) The TPA3101D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method A115-A
(5) In accordance with JEDEC Standard 22, Test Method C101-A
Supply voltage AVCC, PVCC – 0.3 V to 30 V
CC
SHUTDOWN, MUTE – 0.3 V to V
Input voltage
I
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/ SLV,
SYNC
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range – 40 ° C to 85 ° C
A
Operating junction temperature range
J
Storage temperature range – 65 ° C to 150 ° C
stg
(2)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
Load Resistance 3.2 Ω Minimum
(Load)
Human body model
Electrostatic discharge Machine model
Charged-device model
(3)
(all pins) ± 2 kV
(4)
(all pins) ± 200 V
(5)
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
(1)
UNIT
– 0.3 V to VREG + 0.5 V
– 40 ° C to 150 ° C
(all pins) ± 500 V
+ 0.3 V
CC
TYPICAL DISSIPATION RATINGS
PACKAGE TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
48-pin RGZ (QFN) 4.39 W 35.1 mW/ ° C
48-pin PHP (HTQFP) 4.82 W 38.6 mW/ ° C
(1)
(2)
2.81 W 2.28 W
3.09 W 2.51 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about
using the QFN thermal pad.
(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
V
V
I
Supply voltage PVCC, AVCC 10 26 V
CC
High-level input voltage 2 V
IH
Low-level input voltage 0.8 V
IL
High-level input current µA
IH
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/ SLV,
SYNC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/ SLV,
SYNC
SHUTDOWN, VI= VCC, V
MUTE, VI= VCC, V
CC
= 24 V 125
CC
= 24 V 75
GAIN0, GAIN1, MSTR/ SLV, SYNC, VI= VREG,
V
= 24 V
CC
2
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TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
SHUTDOWN, VI= 0, V
I
V
V
f
T
Low-level input current µA
IL
High-level output voltage FAULT, IOH= 1 mA VREG - 0.6 V
OH
Low-level output voltage FAULT, IOL= -1 mA AGND + 0.4 V
OL
Oscillator frequency R
OSC
Operating free-air temperature – 40 85 ° C
A
SYNC, MUTE, GAIN0, GAIN1, MSTR/ SLV, VI= 0 1
V, V
= 24 V
CC
Resistor = 100 k Ω , MSTR/ SLV = 2 V 200 300 kHz
osc
DC CHARACTERISTICS
TA= 25 ° C, V
| V
| VI= 0 V, Gain = 36 dB 5 50 mV
OS
PSRR DC Power supply rejection ratio -70 dB
I
CC
I
CC(SD)
I
CC(MUTE)
r
DS(on)
G Gain
t
ON
t
OFF
= 24 V, RL= 8 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V
4-V internal supply voltage VREG, no load, V
V
CC
Gain = 36 dB
Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load, filter 22 26.5 mA
or snubber
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter or snubber 300 400 µA
Quiescent supply current in mute mode MUTE = 2 V, no load, filter or snubber 8 10 mA
V
Drain-source on-state resistance Low side 370 m Ω
CC
TJ= 25 ° C
GAIN1 = 0.8 V dB
GAIN1 = 2 V dB
Gain matching Between channels 2%
Turn-on time C
Turn-off time C
(VBYP)
(VBYP)
= 24 V 2
CC
= 10 V to 26 V 3.75 4 4.25 V
CC
= 12 V to 24 V, inputs ac coupled to AGND,
High Side 370
= 12 V, IO= 500 mA,
Total 780 950
GAIN0 = 0.8 V 19 20 21
GAIN0 = 2 V 25 26 27
GAIN0 = 0.8 V 31 32 33
GAIN0 = 2 V 35 36 37
= 1 µF, SHUTDOWN = 2 V 25 ms
= 1 µF, SHUTDOWN = 0.8 V 0.1 ms
DC CHARACTERISTICS
TA= 25 ° C, V
| V
| VI= 0 V, Gain = 36 dB 5 50 mV
OS
PSRR DC Power supply rejection ratio -70 dB
I
CC
I
CC(SD)
I
CC(MUTE)
r
DS(on)
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
= 12 V, RL= 8 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V
4-V internal supply voltage VREG, no load 3.75 4 4.25 V
V
= 12 V to 24 V, Inputs ac coupled to AGND,
CC
Gain = 36 dB
Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load, filter 18 22.5 mA
or snubber
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter or snubber 180 300 µA
Quiescent supply current in mute mode MUTE = 2 V, no load, filter or snubber 7 9 mA
High Side 370
V
= 12 V, IO= 500 mA,
Drain-source on-state resistance Low side 370 m Ω
CC
TJ= 25 ° C
Total 780 950
Product Folder Link(s): TPA3101D2
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TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
DC CHARACTERISTICS (continued)
TA= 25 ° C, V
G Gain
t
ON
t
OFF
AC CHARACTERISTICS
TA= 25 ° C, V
K
SVR
P
O
THD+N Total harmonic distortion + noise f = 1 kHz, PO= 5 W (half-power) 0.09%
V
n
SNR Signal-to-noise ratio 102 dB
= 12 V, RL= 8 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAIN0 = 0.8 V 19 20 21
GAIN0 = 2 V 25 26 27
GAIN0 = 0.8 V 31 32 33
GAIN0 = 2 V 35 36 37
Turn-on time C
Turn-off time C
= 24 V, RL= 8 Ω (unless otherwise noted)
CC
GAIN1 = 0.8 V dB
GAIN1 = 2 V dB
= 1 µF, SHUTDOWN = 2 V 25 ms
(VBYP)
= 1 µF, SHUTDOWN = 0.8 V 0.1 ms
(VBYP)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply ripple rejection – 70 dB
200 mV
Gain = 20 dB, Inputs ac-coupled to AGND
ripple from 20 Hz – 1 kHz,
PP
Continuous output power THD+N = 0.09%, f = 1 kHz (thermally limited) 10 W
Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
100 µV
– 80 dBV
Crosstalk VO= 1 Vrms, Gain = 20 dB, f = 1 kHz – 92 dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point 150 ° C
Thermal hysteresis 30 ° C
AC CHARACTERISTICS
TA= 25 ° C, V
K
SVR
P
O
THD+N Total harmonic distortion + noise RL= 8 Ω , f = 1 kHz, PO= 4.5 W (half-power) 0.08%
V
n
SNR Signal-to-noise ratio 98 dB
= 12 V, RL= 8 Ω (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply ripple rejection – 70 dB
200 mV
Gain = 20 dB, Inputs ac-coupled to AGND
ripple from 20 Hz – 1 kHz,
PP
THD+N = 7%, f = 1 kHz 8.7
THD+N = 10%, f = 1 kHz 9.2
Continuous output power W
THD+N = 10%, f = 1 kHz, V
= 13 V 10
CC
THD+N = 0.26%, f = 1 kHz, RL= 4 Ω (thermally 10
limited)
RL= 4 Ω , f = 1 kHz, PO= 5 W (half-power) 0.11%
Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
100 µV
– 80 dBV
Crosstalk Po= 1 W, Gain = 20 dB, f = 1 kHz – 94 dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point 150 ° C
Thermal hysteresis 30 ° C
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32
5
27
10
25
12
PVCCR
RINP
PGNDR
AGND
AVCC
NC
MUTE
VBYP
ROUTP
LOUTP
NC
NC
BSRN
BSLN
LOUTN
ROUTN
F
AUL
T
VREG
SHUTDOWN
AGND
NC
ROSC
BSRP
BSLP
ROUTP
ROUTN
LOUTN
LOUTP
PVCCR
Exposed
ThermalPad
RINN
NC
NC
NC
NC
PGNDR
LINP
VCLAMPR
LINN
VCLAMPL
NC
PGNDL
GAIN0
PGNDL
GAIN1
PVCCL
MSTR/SLV
PVCCL
SYNC
33
4
28
9
26
11
34
3
29
8
35
2
30
7
36
1
31
6
44
17
38
23
43
18
37
24
45
16
39
22
46
15
40
21
47
14
41
20
48
13
42
19
AVCC
A
VCC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
GND
GND
PVCCR
PVCCR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PVCCL
PVCCL
GND
GND
RINN
RINP
AGND
LINP
LINN
GAIN0
GAIN1
MSTR/SLV
SYNC
GND
GND
ROSC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
GND
PGNDR
PGNDL
GAIN0
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
Exposed
ThermalPad
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
48 PIN, QFN PACKAGE 48 PIN, HTQFP PACKAGE
(TOP VIEW) (TOP VIEW)
TPA3101D2
TERMINAL FUNCTIONS
TERMINAL
NAME
QFN HTQFP
NO. NO.
SHUTDOWN 44 44 I
RINN 2 2 I Negative audio input for right channel. Biased at VREG/2.
RINP 3 3 I Positive audio input for right channel. Biased at VREG/2.
LINN 6 6 I Negative audio input for left channel. Biased at VREG/2.
LINP 5 5 I Positive audio input for left channel. Biased at VREG/2.
GAIN0 8 7, 8 I Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1 9 9 I Gain select most significant bit. TTL logic levels with compliance to VREG.
1, 12, 13,
GND 24, 25, 36, Connect to the thermal pad.
37
MUTE 45 45 I
FAULT 46 46 O
BSLP 18 18 I/O Bootstrap I/O for left channel, positive high-side FET.
PVCCL 26, 27 26, 27
LOUTP 19, 20 19, 20 O Class-D 1/2-H-bridge positive output for left channel.
PGNDL 28, 29 28, 29 Power ground for left channel H-bridge.
LOUTN 21, 22 21, 22 O Class-D 1/2-H-bridge negative output for left channel.
BSLN 23 23 I/O Bootstrap I/O for left channel, negative high-side FET.
VCLAMPL 30 30 Internally generated voltage supply for left channel bootstrap capacitor.
VCLAMPR 31 31 Internally generated voltage supply for right channel bootstrap capacitor.
BSRN 38 38 I/O Bootstrap I/O for right channel, negative high-side FET.
ROUTN 39, 40 39, 40 O Class-D 1/2-H-bridge negative output for right channel.
PGNDR 32, 33 32, 33 Power ground for right channel H-bridge.
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
I/O DESCRIPTION
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
levels with compliance to AVCC.
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only
reports short-circuit faults. Thermal faults are not reported on this terminal.
Power supply for left channel H-bridge, not internally connected to PVCCR
or AVCC.
Product Folder Link(s): TPA3101D2
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TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
ROUTP 41, 42 41, 42 O Class-D 1/2-H-bridge positive output for right channel.
PVCCR 34, 35 34, 35 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
BSRP 43 43 I/O Bootstrap I/O for right channel, positive high-side FET.
AGND 4, 17 4, 17 Analog ground for digital/analog cells in core.
ROSC 14 14 I/O I/O for current setting resistor of ramp generator.
MSTR/ SLV 10 10 I
SYNC 11 11 I/O
VBYP 16 16 O
VREG 15 15 O
AVCC 48 47, 48
NC 13, 24, 25, Not internally connected.
Thermal Pad - - - should connect this pad to a large copper area on an internal or bottom
QFN HTQFP
NO. NO.
1, 7, 12,
36, 37, 47
I/O DESCRIPTION
Master/Slave select for determining direction of SYNC terminal.
HIGH=Master mode, SYNC terminal is an output; LOW = slave mode,
SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
Clock input/output for synchronizing multiple class-D devices. Direction
determined by MSTR/ SLV terminal. Input signal not to exceed VREG.
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up
time via external capacitor sizing.
4-V regulated output for use by internal cells, GAINx, MUTE, and
MSTR/ SLV pins only. Not specified for driving other external circuitry.
High-voltage analog power supply. Not internally connected to PVCCR or
PVCCL.
Connect to AGND and PGND – should be star point for both grounds.
Internal resistive connection to AGND and PGND. Thermal vias on the PCB
layer for the best thermal performance. The Thermal Pad must be soldered
to the PCB for mechanical reliability.
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Biases
and
References
Startup
Protection
Logic
VREGok
RINP
RINN
Ramp
Generator
ROSC
VCCok
4VReg
AVCC
VREG
PWM
Logic
Gain
Control
Gain
Control
LINP
LINN
SHUTDOWN
VBYP
VBYP
MSTR/SLV
PWM
Logic
SYNC
AVCC
AVCC
AVCC
Gain
Control
GAIN0
GAIN1
8
ToGain Adj.
Blocksand
StartupLogic
MUTE
FAULT
VREG
AGND
VBYP
VBYP
VREG
VBYP
VClamp
Gen
PVCCR
Gate
Drive
Gate
Drive
VClamp
Gen
Gate
Drive
Thermal
SC
Detect
PVCCR
Gate
Drive
BSLN
VCLAMPL
PVCCL
PVCCL
BSLP
LOUTN
BSRN
VCLAMPR
PVCCR
PVCCR
ROUTN
BSRP
ROUTP
PGNDR
PVCCL
PVCCL
PGNDL
LOUTP
Gain
Gain
Gain
Gain
TLL Input
Buffer
(VCCCompliant)
TLL Input
Buffer
(VCCCompliant)
FUNCTIONAL BLOCK DIAGRAM
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
FIGURE
(1)
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
Closed-loop response vs Frequency 9, 10
Output power vs Supply voltage 11. 12
Efficiency vs Output power 13, 14
Supply current vs Total output power 15, 16
Crosstalk vs Frequency 17, 18
Supply ripple rejection ratio vs Frequency 19, 20
THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4
THD+N Total harmonic distortion + noise vs Output power 5, 6, 7, 8
V
CC
k
SVR
(1) All graphs were measured using the TPA3101D2 EVM.
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
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0.003
10
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
V =18V,
R =8 ,
Gain=20dB
CC
L
W
P =2.5W
O
P =1W
O
P =10W
O
20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
0.003
10
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
V =12V,
R =8 ,
Gain=20dB
CC
L
W
P =5W
O
P =2.5W
O
P =1W
O
0.003
10
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
V =24V,
R =8 ,
Gain=20dB
CC
L
W
P =5W
O
P =10W
O
P =1W
O
0.003
10
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
20 20k50 100 200 500 1k 2k 5k 10k
f-Frequency-Hz
V =12V,
R =4 ,
Gain=20dB
CC
L
W
P =2.5W
O
P =1W
O
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
NOTE: Power above 10 W may require increased NOTE: Power above 10 W may require increased
heatsinking. heatsinking.
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
NOTE: Power above 10 W may require increased NOTE: Power above 10 W may require increased
heatsinking. heatsinking.
8 Submit Documentation Feedback Copyright © 2005 – 2007, Texas Instruments Incorporated
vs vs
FREQUENCY FREQUENCY
Figure 3. Figure 4.
Product Folder Link(s): TPA3101D2
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0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
10m 4050m 100m 200m 1 2 5 10 20
P -OutputPower-W
O
10kHz
20Hz
1kHz
V =18V,
R =8 ,
Gain=32dB
CC
L
W
10m 4050m 100m 200m 1 2 5 10 20
P -OutputPower-W
O
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
10kHz
20Hz
1kHz
V =12V,
R =8 ,
Gain=32dB
CC
L
W
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
10m 4050m 100m 200m 1 2 5 10 20
P -OutputPower-W
O
10kHz
20Hz
1kHz
V =24V,
R =8 ,
Gain=32dB
CC
L
W
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD-TotalHarmonicDistortion-%
10m 4050m 100m 200m 1 2 5 10 20
P -OutputPower-W
O
V =12V,
R =4 ,
Gain=32dB
CC
L
W
10kHz
20Hz
1kHz
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
NOTE: Power above 10 W may require increased NOTE: Power above 10 W may require increased
heatsinking. heatsinking.
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
NOTE: Power above 10 W may require increased NOTE: Power above 10 W may require increased
heatsinking. heatsinking.
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 7. Figure 8.
Product Folder Link(s): TPA3101D2
www.ti.com
-200
200
-150
-100
-50
0
50
100
150
0
40
5
10
15
20
25
30
35
f-Frequency-Hz
10 100 1k 10k 100k
Gain
−
dB
Phase
−
o
Gain
Phase
V =12V
R =8
V =0.1V
C =10 F
Gain=32dB
RCfilter=100 ,10nF
CC
L
I rms
I
W
m
W
-200
200
-150
-100
-50
0
50
100
150
0
40
5
10
15
20
25
30
35
f-Frequency-Hz
10 100 1k 10k 100k
Gain
−
dB
Phase
−
o
Gain
Phase
V =24V
R =8
V =0.1V
C =10 F
Gain=32dB
RCfilter=100 ,10nF
CC
L
I rms
I
W
m
W
V -SupplyVoltage-V
CC
5
7.5
10
12.5
15
17.5
22.5
20
30
25
35
27.5
32.5
37.5
10
12 14
16
18 20 22
24 26
P
O
−
OutputPower
−
W
THD+N=10%
THD+N=1%
R =8
Gain=20dB
L
W
PowerBeyond10W
MayRequireMore
Heatsinking.
V -SupplyVoltage-V
CC
0
2
4
6
8
10
12
18
14
16
20
10
11 12
13
P
O
−
OutputPower
−
W
THD+N=10%
THD+N=1%
R =4
Gain=20dB
L
W
PowerBeyond10W
MayRequireMore
Heatsinking.
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
OUTPUT POWER OUTPUT POWER
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
10 Submit Documentation Feedback Copyright © 2005 – 2007, Texas Instruments Incorporated
Figure 11. Figure 12.
Product Folder Link(s): TPA3101D2
www.ti.com
PO− OutputPower(PerChannel) − W
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12 14 16 18 20
RL=8 W
Gain=20dB
Efficiency
−
%
VCC=24V
V =18V
CC
VCC=12V
PO− OutputPower(PerChannel) − W
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12 14 15
RL=4 Ω
Gain=32dB
Efficiency
−
%
VCC=12V
PO− TotalOutputPower − W
0
0.5
1
1.5
2
2.5
0 10 20 30 40
RL=8 Ω
Gain=32dB
I
C
C
−
SupplyCurrent
−
A
VCC=24V
VCC=12V
VCC=18V
PowerBeyond10W
MayRequireMore
Heatsinking.
PO− TotalOutputPower − W
0
0.5
1
1.5
2
2.5
0 10 20 30 40
RL=4 Ω
Gain=32dB
I
C
C
−
SupplyCurrent
−
A
VCC=12V
PowerBeyond10W
MayRequireMore
Heatsinking.
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
EFFICIENCY EFFICIENCY
vs vs
OUTPUT POWER OUTPUT POWER
TPA3101D2
SUPPLY CURRENT SUPPLY CURRENT
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
Figure 13. Figure 14.
vs vs
Figure 15. Figure 16.
Product Folder Link(s): TPA3101D2
www.ti.com
−140
−120
−100
−80
−60
-40
f − Frequency − Hz
Crosstalk
−
dB
20 100 1k 10k 20k
VCC=12V
RL=8 Ω
Gain=20dB
V =1Vrms
O
L toR
RtoL
−140
−120
−100
−80
−60
-40
f − Frequency − Hz
Crosstalk
−
dB
20 100 1k 10k 20k
VCC=24V
RL=8 Ω
Gain=20dB
V =1Vrms
O
L toR
RtoL
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
k
S
V
R
−
SupplyRippleRejectionRatio
−
dB
20 100 1k 10k 20k
V =12V
CC
R =8
Gain=20dB
V =200mV
L
(RIPPLE) PP
W
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
k
S
V
R
−
SupplyRippleRejectionRatio
−
dB
20 100 1k 10k 20k
V =18V
CC
R =8
Gain=20dB
V =200mV
L
(RIPPLE) PP
W
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
Figure 17. Figure 18.
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 19. Figure 20.
12 Submit Documentation Feedback Copyright © 2005 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPA3101D2
www.ti.com
TPA3101D2
GAIN1
LINP
RINN
RINP
AGND
LINN
GAIN0
SYNC
MSTR/SLV
NC
NC
NC
AVCC
NC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
NC
10V-26V
NC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
NC
ROSC
220nF 220nF
220nF
220nF
PVCCR
NC
NC
PGNDR
PVCCR
PGNDR
VCLAMPR
VCLAMPL
PVCCL
PGNDL
PGNDL
PVCCL
10V-26V
10V-26V
FaultOutput
Shutdown
andMute
Control
10 Fm
33 Hm
33 Hm
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
220 Fm
1 Fm
1 Fm
1 Fm
220 Fm
1 Fm
1 Fm
10nF
100kW
1 Fm
1 Fm
Differential
Analog
Inputs
4-Step
GainControl
SynchronizeMultiple
Class-DDevices
33 Hm
33 Hm
1 Fm
8 W
8 W
1 Fm
470pF
470pF
20 W
20 W
20 W
20 W
20 W
470pF
470pF
TPA3101D2
SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007
APPLICATION INFORMATION
Figure 21. Stereo Class-D With Differential Inputs (QFN)
Copyright © 2005 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPA3101D2
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