Texas Instruments TPA3008D2 User Manual

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10 µF

220 nF 220 nF

PVCC PVCC

220 nF 220 nF

PVCC PVCC

220 pF

Left Differential Inputs

Right Differential Inputs

Shutdown/Mute

Gain Control

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

PVCCL

BSLN

TPA3008D2

VCLAMPR

SHUTDOWN

V2P5

RINP

LINN

LINP

AVDDREF NC GAIN0 GAIN1

NC

AVDD

AGND

COSC ROSC

AVCC

VCLAMPL

BSRP

PVCCR

ROUTP

PGNDR

ROUTN

PVCCR

BSRN

RINN

AVCC

AGND

10 µF

0.1 µF

0.47 µF

0.1 µF

10 µF

1 µF

120 kΩ

1 µF

NC

FAULT

0.1 µF

10 µF

1 µF

Control

†Optional output filter for EMI suppression

†

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

FEATURES DESCRIPTION

• 10-W/Channel Into an 16-Ω Load From a

17-V Supply

• Up to 92% Efficient, Class-D Operation

Eliminates Need For Heatsinks

• 8.5-V to 18-V Single-Supply Operation

• Four Selectable, Fixed Gain Settings

• Differential Inputs Minimizes Common-Mode

Noise

• Space-Saving, Thermally Enhanced

PowerPAD™ Packaging

• Thermal and Short-Circuit Protection

With Auto Recovery Option

• Pinout Similar to TPA3000D Family

APPLICATIONS

• LCD Monitors and TVs

• All-In-One PCs

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

The TPA3008D2 is a 10-W (per channel) efficient, class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3008D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3008D2 eliminates the need for external heatsinks when playing music.

The gain of the amplifier is controlled by two gain select pins. The gain selections are 15.3, 21.2, 27.2, and 31.8 dB.

The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts. A fault terminal allows short-circuit fault reporting and automatic recovery. Thermal protection ensures that the maximum junction temperature is not exceeded.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range AV Load Impedance, R

Input voltage range, V

L

I

Continuous total power dissipation See Dissipation Rating Table Operating free–air temperature range, T Operating junction temperature range, T Storage temperature range, T

stg

A J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

, PV

CC

SHUTDOWN -0.3 V to VCC + 0.3 V GAIN0, GAIN1, RINN, RINP, LINN, LINP -0.3 V to 6 V

(1)

TPA3008D2

-0.3 V to 20 V ≥ 6 Ω

- 40°C to 85°C

- 40°C to 150°C

- 65°C to 150°C

DISSIPATION RATING TABLE

(1)

DERATING

FACTOR TA= 70°C TA= 85°C

(1/θJA)

34.7 mW/°C

(1)

2.7 W 2.2 W

PACKAGE TA≤ 25°C θ

JC

PHP 4.3 W 1.14 °C/W

(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the

printed-circuit board. See the PowerPAD Thermally Enhanced Package application note (SLMA002). The PowerPAD must be soldered to the PCB.

RECOMMENDED OPERATING CONDITIONS

TA= 25°C (unless otherwise noted)

Supply voltage, V High-level input voltage, V Low-level input voltage, V

High-level input current, I

Low-level input current, I

High-level output voltage, V Low-level output voltage, V

Oscillator frequency, f Operating free–air temperature, T

CC

IH

IL

IH

IL

OSC

MIN MAX UNIT

PV

, AV

CC

8.5 18 V SHUTDOWN, GAIN0, GAIN1 2 V SHUTDOWN, GAIN0, GAIN1 0.8 V SHUTDOWN, VI= V GAIN0, GAIN1, VI= 5.5 V, V SHUTDOWN, VI= 0 V, V GAIN0, GAIN1, VI= 5.5 V, V FAULT, IOH= 100 µA AV

OH

FAULT, IOL= -100 µA AGND + 0.8 V V

OL

Frequency is set by selection of ROSC and COSC (see the Application Information Section).

A

= 18 V 10 µA

CC

= 18 V 1 µA

CC

= 18 V 1 µA

CC

= 18 V 1 µA

CC

- 0.8 V V

DD

200 300 kHz

-40 85 °C

2

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

AVAILABLE OPTIONS

T

A

-40°C to 85°C TPA3008D2PHP

(1) The PHP package is available taped and reeled. To order a taped

and reeled part, add the suffix R to the part number (e.g., TPA3008D2PHPR).

DC ELECTRICAL CHARACTERISTICS

TA= 25°C, V

|V

| 2 5 55 mV

OO

V2P5 2.5-V Bias voltage No load 2.5 V AV

DD

PSRR Power supply rejection ratio V I

CC

I

CC(SD)

r

DS(on)

G Gain dB

t

on

t

off

= 12 V, RL= 8 Ω (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage INN and INP connected together, (measured differentially) Gain = 31.8 dB

+5-V internal supply voltage 4.5 5 5.5 V

IL= 10 mA, SHUTDOWN = 2 V, V

= 8.5 V to 18 V

CC

= 11.5 V to 12.5 V -76 dB

CC

Quiescent supply current SHUTDOWN = 2 V, no load 11 22 mA Quiescent supply current in shut-

down mode

Drain-source on-state resistance IO= 1 A, Low side 500 mΩ

SHUTDOWN = 0 V 1.6 25 µA

V

= 12 V,

CC

TJ= 25°C

GAIN1 = 0.8 V

GAIN1 = 2 V

Turnon time C Turnoff time C

= 1 µF, SHUTDOWN = 2 V 16 ms

(V2P5)

= 1 µF, SHUTDOWN = 0.8 V 60 µs

(V2P5)

PACKAGED DEVICE

48-PIN HTQFP (PHP)

(1)

High side 600

Total 1100 1300 GAIN0 = 0.8 V 14.6 15.3 16.2 GAIN0 = 2 V 20.5 21.2 21.8 GAIN0 = 0.8 V 26.4 27.2 27.8 GAIN0 = 2 V 31.1 31.8 32.5

AC ELECTRICAL CHARACTERISTICS

TA= 25°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

k

SVR

P

O

THD+N PO= 1 W, f = 1 kHz, RL= 8 Ω 0.1%

V

n

SNR Signal-to-noise ratio 97 dB

= 12 V, RL= 8 Ω, (unless otherwise noted)

CC

Supply voltage rejection ratio -70 dB

200 mV Gain = 15.6 dB, Inputs ac-coupled to GND

ripple from 20 Hz to 1 kHz,

PP

THD+N = 0.13%, f = 1 kHz, RL= 8 Ω 5 THD+N = 10%, f = 1 kHz, RL= 8 Ω 8.5

Continuous output power W

THD+N = 0.16%, f = 1 kHz, RL= 16 Ω, V

= 17 V

CC

THD+N = 10%, f = 1 kHz, RL= 16 Ω, V

= 17 V

CC

5

10

Total harmonic distortion plus noise

Output integrated noise floor -80 dB

20 Hz to 22 kHz, A-weighted filter, Gain = 15.6 dB

Crosstalk PO= 1 W, RL= 8 Ω, Gain = 15.6 dB, -93 dB

f = 1 kHz Maximum output at THD+N < 0.5%,

f = 1 kHz, Gain = 15.6 dB Thermal trip point 150 °C Thermal hystersis 20 °C

3

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Biases

and

References

TTL Input

Buffer

(VCC Compl)

Start-up and

Protection

Logic

SC

Detect

Thermal

VDDok

RINP

RINN

Ramp Generator

COSC

ROSC

VCCok

5-V LDO

AVCC

AVDD

VDD

and PWM Mode Logic

Gain

Adj.

Gain

Control

Deglitch

and PWM Mode Logic

Gain

Adj.

LINP

LINN

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSRP PVCCR(2)

ROUTP(2)

PGNDR

ROUTN(2)

PVCCR(2)

BSRN

Gate Drive

VClamp

Gen

Gate

Drive

PVCC

BSLP PVCCL(2)

LOUTP(2)

PGNDL

LOUTN(2)

PVCCL(2)

BSLN

VCLAMPL

VCLAMPR

GAIN0

4

To Gain Adj. Blocks and Start-up Logic

SHUTDOWN

V2P5

AVCC AGND(2)

V2P5

Deglitch

GAIN1

AVDDREF

FAULT

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM

4

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13 14 15 16 17 18 19 20 21 22 23 24

25

26

27

28

29

30

31

32

33

34

35

36

48 47 46 45 44 43 42 41 40 39 38 37

1 2 3 4 5 6 7 8 9 10 11 12

BSRN

PVCCR

ROUTN

PGNDR

ROUTP

PVCCR

BSRP

VCLAMPR NC NC

NC NC AGND

COSC ROSC AGND VCLAMPL

SHUTDOWN

RINN RINP V2P5

LINP

LINN

NC GAIN0 GAIN1 FAULT

NC

BSLN

PVCCL

LOUTN

PGNDL

LOUTP

PVCCL

BSLP

TPA3008D2

AV

CC

AV

DD

AVDDREF

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

PHP PACKAGE

(TOP VIEW)

5

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TERMINAL FUNCTIONS

PIN NAME PIN NUMBER I/O DESCRIPTION

AGND 26, 30 - Analog ground for digital/analog cells in core AV

CC

AV

DD

AV

REF 7 O 5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1.

DD

BSLN 13 - Bootstrap I/O for left channel, negative high-side FET BSLP 24 - Bootstrap I/O for left channel, positive high-side FET BSRN 48 - Bootstrap I/O for right channel, negative high-side FET BSRP 37 - Bootstrap I/O for right channel, positive high-side FET COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator.

FAULT 11 O

GAIN0 9 I Gain select least significant bit. TTL logic levels with compliance to AV GAIN1 10 I Gain select most significant bit. TTL logic levels with compliance to AV LINN 6 I Negative audio input for left channel LINP 5 I Positive audio input for left channel LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel

NC - No internal connection PGNDL 18, 19 - Power ground for left channel H-bridge

PGNDR 42, 43 - Power ground for right channel H-bridge PVCCL 14, 15 -

PVCCL 22, 23 -

PVCCR 38, 39 -

PVCCR 46, 47 RINP 3 I Positive audio input for right channel

RINN 2 I Negative audio input for right channel ROSC 27 I/O I/O current setting resistor for ramp generator. ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel

SHUTDOWN 1 I VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors.

VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors. V2P5 4 O 2.5-V Reference for analog cells.

Thermal Pad - -

33 - High-voltage analog power supply, not connected internally to PVCCR or PVCCL 29 O

5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. Not specified for driving other external circuitry.

Short-circuit detect fault output. FAULT = high, short-circuit detected. FAULT = low, normal operation. Status is reset when power is cycled or SHUTDOWN is cycled.

8, 12, 31, 32,

34, 35

Power supply for left channel H-bridge (internally connected to pins 22 and 23), not connected to PVCCR or AV

.

CC

Power supply for left channel H-bridge (internally connected to pins 14 and 15), not connected to PVCCR or AV

.

CC

Power supply for right channel H-bridge (internally connected to pins 46 and 47), not connected to PVCCL or AV

.

CC

Power supply for right channel H-bridge (internally connected to pins 38 and 39), not connected to PVCCL or AV

.

CC

Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.

Connect to AGND and PGND—should be the center point for both grounds. Internal resistive connection to AGND.

.

DD

.

DD

6

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0.01 20

20 k

100

1 k 10 k

THD+N −Total Harmonic Distortion + Noise − %

VCC = 18 V , RL = 16  Gain = 21.6 dB

f − Frequency − Hz

10

0.1

PO = 2.5 W

PO = 0.5 W

PO = 1 W

1

0.005

10

0.01

0.1

20

20 k

100

1 k

10 k

PO = 2.5 W

THD+N −Total Harmonic Distortion + Noise − %

VCC = 12 V , RL = 16 , Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

1

PO = 0.5 W

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4 THD+N Total harmonic distortion + noise vs Output power 5, 6

Closed-loop response 7 Output power vs Supply voltage 8, 9 Efficiency vs Output power 10 Efficiency vs Total output power 11

V

CC

k

SVR

CMRR Commom-mode rejection ratio vs Frequency 15

Supply current vs Total output power 12 Crosstalk vs Frequency 13 Supply ripple rejection ratio vs Frequency 14

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 1. Figure 2.

7

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0.005

10

0.01

0.1

20

20 k

100

1 k 10 k

PO = 5 W

THD+N −Total Harmonic Distortion + Noise − %

VCC = 18 V , RL = 8 , Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

PO = 2.5 W

1

0.01

0.1

10

20

20 k

100

1 k 10 k

THD+N −Total Harmonic Distortion + Noise − %

VCC = 12 V , RL = 8  Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

PO = 2.5 W

PO = 0.5 W

1

0.01

10

0.1

1

20m 10100 m 1

THD+N −Total Harmonic Distortion + Noise − %

PO− Output Power − W

VCC = 12 V , RL = 8 , Gain = 21.6 dB

20200 m 2

1 kHz

20

20 Hz

20 kHz

0.01

10

0.1

1

20m 10100 m 1

THD+N −Total Harmonic Distortion + Noise − %

PO− Output Power − W

VCC = 18 V , RL = 16 , Gain = 21.6 dB

20 Hz

20200 m 2

20 kHz

1 kHz

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

8

Figure 5. Figure 6.

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28

24

20

16

10 100 1k

Gain − dB

32

36

f − Frequency − Hz

40

10k

12

8

4

0

80k

VCC = 12 V , RL = 8 Ω, Gain = 32 dB 33 kHz, RC LPF

Gain

Phase

Phase −

50

0

100

−150



−100

−50

150

0

1

2

3

4

5

6

7

8

9

10

11

12

8 9

10 11 12 13 14 15 16 17 18

P

O

− Output Power − W

THD+N = 10%

THD+N = 1%

RL = 16 

VCC − Supply Voltage − V

2

3

4

5

6

7

8

9

8 9 10 11 12 13 14

THD+N = 1%

THD+N = 10%

RL = 8 

VCC − Supply Voltage − V

P

O

− Output Power − W

10

11

12

Power represented by dashed line may require external heatsinking

0

10

20

30

40

50

60

70

0 1 2 3 4 5 6

PO − Output Power (Per Channel) − W

Efficiency − %

80

90

100

7 8 9 10

VCC = 18 V , RL = 16 

CLOSED-LOOP RESPONSE SUPPLY VOLTAGE

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

OUTPUT POWER

vs

OUTPUT POWER EFFICIENCY

SUPPLY VOLTAGE OUTPUT POWER

Figure 7. Figure 8.

vs vs

Figure 9. Figure 10.

9

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0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency − %

16 

8 

PO − Total Output Power − W

11 12

VCC = 12 V , LC Filter, Resistive Load, Stereo Operation

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 2 4 6 8 10 12

PO − Total Output Power − W

1.6

1.8

2.0

14 16 18 20

LC Filter, Resistive Load, Stereo Operation

− Supply Current − AV CC

VCC = 18 V , RL = 16 

VCC = 12 V ,

RL = 16 

VCC = 12 V ,

RL = 8 

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

20 100 1 k 10 k

Crosstalk − dB

f − Frequency − Hz

VCC = 12 V , PO = 2.5 W, Gain = 21.6 dB RL = 8

20 k

−100

−90

−80

−70

−60

−50

−40

20 100 1 k 10 k

f − Frequency − Hz

k

SVR

− Supply Ripple Rejection Ratio − dB

VCC = 12 V , V

(RIPPLE)

= 200 mVPP, RL = 8 , Gain = 15.6 dB

20 k

−30

−20

−10

0

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TOTAL OUTPUT POWER TOTAL OUTPUT POWER

EFFICIENCY SUPPLY CURRENT

vs vs

10

Figure 11. Figure 12.

CROSSTALK SUPPLY RIPPLE REJECTION RATIO

vs vs

FREQUENCY FREQUENCY

Figure 13. Figure 14.

Texas Instruments TPA3008D2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

AVAILABLE OPTIONS

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS