Texas Instruments TPA3008D2 User Manual

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10 µF

220 nF 220 nF

PVCC PVCC

220 nF 220 nF

PVCC PVCC

220 pF

Left Differential Inputs

Right Differential Inputs

Shutdown/Mute

Gain Control

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

PVCCL

BSLN

TPA3008D2

VCLAMPR

SHUTDOWN

V2P5

RINP

LINN

LINP

AVDDREF NC GAIN0 GAIN1

AVDD

AGND

COSC ROSC

AVCC

VCLAMPL

BSRP

PVCCR

ROUTP

PGNDR

ROUTN

PVCCR

BSRN

RINN

AVCC

AGND

10 µF

0.1 µF

0.47 µF

0.1 µF

10 µF

1 µF

120 kΩ

1 µF

FAULT

0.1 µF

10 µF

1 µF

Control

†Optional output filter for EMI suppression

†

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

FEATURES DESCRIPTION

• 10-W/Channel Into an 16-Ω Load From a

17-V Supply

• Up to 92% Efficient, Class-D Operation

Eliminates Need For Heatsinks

• 8.5-V to 18-V Single-Supply Operation

• Four Selectable, Fixed Gain Settings

• Differential Inputs Minimizes Common-Mode

Noise

• Space-Saving, Thermally Enhanced

PowerPAD™ Packaging

• Thermal and Short-Circuit Protection

With Auto Recovery Option

• Pinout Similar to TPA3000D Family

APPLICATIONS

• LCD Monitors and TVs

• All-In-One PCs

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

The TPA3008D2 is a 10-W (per channel) efficient, class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3008D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3008D2 eliminates the need for external heatsinks when playing music.

The gain of the amplifier is controlled by two gain select pins. The gain selections are 15.3, 21.2, 27.2, and 31.8 dB.

The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts. A fault terminal allows short-circuit fault reporting and automatic recovery. Thermal protection ensures that the maximum junction temperature is not exceeded.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range AV Load Impedance, R

Input voltage range, V

Continuous total power dissipation See Dissipation Rating Table Operating free–air temperature range, T Operating junction temperature range, T Storage temperature range, T

stg

A J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

, PV

SHUTDOWN -0.3 V to VCC + 0.3 V GAIN0, GAIN1, RINN, RINP, LINN, LINP -0.3 V to 6 V

(1)

TPA3008D2

-0.3 V to 20 V ≥ 6 Ω

- 40°C to 85°C

- 40°C to 150°C

- 65°C to 150°C

DISSIPATION RATING TABLE

(1)

DERATING

FACTOR TA= 70°C TA= 85°C

(1/θJA)

34.7 mW/°C

(1)

2.7 W 2.2 W

PACKAGE TA≤ 25°C θ

PHP 4.3 W 1.14 °C/W

(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the

printed-circuit board. See the PowerPAD Thermally Enhanced Package application note (SLMA002). The PowerPAD must be soldered to the PCB.

RECOMMENDED OPERATING CONDITIONS

TA= 25°C (unless otherwise noted)

Supply voltage, V High-level input voltage, V Low-level input voltage, V

High-level input current, I

Low-level input current, I

High-level output voltage, V Low-level output voltage, V

Oscillator frequency, f Operating free–air temperature, T

OSC

MIN MAX UNIT

, AV

8.5 18 V SHUTDOWN, GAIN0, GAIN1 2 V SHUTDOWN, GAIN0, GAIN1 0.8 V SHUTDOWN, VI= V GAIN0, GAIN1, VI= 5.5 V, V SHUTDOWN, VI= 0 V, V GAIN0, GAIN1, VI= 5.5 V, V FAULT, IOH= 100 µA AV

FAULT, IOL= -100 µA AGND + 0.8 V V

Frequency is set by selection of ROSC and COSC (see the Application Information Section).

= 18 V 10 µA

= 18 V 1 µA

- 0.8 V V

200 300 kHz

-40 85 °C

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

AVAILABLE OPTIONS

-40°C to 85°C TPA3008D2PHP

(1) The PHP package is available taped and reeled. To order a taped

and reeled part, add the suffix R to the part number (e.g., TPA3008D2PHPR).

DC ELECTRICAL CHARACTERISTICS

TA= 25°C, V

| 2 5 55 mV

V2P5 2.5-V Bias voltage No load 2.5 V AV

PSRR Power supply rejection ratio V I

CC(SD)

DS(on)

G Gain dB

off

= 12 V, RL= 8 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage INN and INP connected together, (measured differentially) Gain = 31.8 dB

+5-V internal supply voltage 4.5 5 5.5 V

IL= 10 mA, SHUTDOWN = 2 V, V

= 8.5 V to 18 V

= 11.5 V to 12.5 V -76 dB

Quiescent supply current SHUTDOWN = 2 V, no load 11 22 mA Quiescent supply current in shut-

down mode

Drain-source on-state resistance IO= 1 A, Low side 500 mΩ

SHUTDOWN = 0 V 1.6 25 µA

= 12 V,

TJ= 25°C

GAIN1 = 0.8 V

GAIN1 = 2 V

Turnon time C Turnoff time C

= 1 µF, SHUTDOWN = 2 V 16 ms

(V2P5)

= 1 µF, SHUTDOWN = 0.8 V 60 µs

(V2P5)

PACKAGED DEVICE

48-PIN HTQFP (PHP)

(1)

High side 600

Total 1100 1300 GAIN0 = 0.8 V 14.6 15.3 16.2 GAIN0 = 2 V 20.5 21.2 21.8 GAIN0 = 0.8 V 26.4 27.2 27.8 GAIN0 = 2 V 31.1 31.8 32.5

AC ELECTRICAL CHARACTERISTICS

TA= 25°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVR

THD+N PO= 1 W, f = 1 kHz, RL= 8 Ω 0.1%

SNR Signal-to-noise ratio 97 dB

= 12 V, RL= 8 Ω, (unless otherwise noted)

Supply voltage rejection ratio -70 dB

200 mV Gain = 15.6 dB, Inputs ac-coupled to GND

ripple from 20 Hz to 1 kHz,

THD+N = 0.13%, f = 1 kHz, RL= 8 Ω 5 THD+N = 10%, f = 1 kHz, RL= 8 Ω 8.5

Continuous output power W

THD+N = 0.16%, f = 1 kHz, RL= 16 Ω, V

= 17 V

THD+N = 10%, f = 1 kHz, RL= 16 Ω, V

= 17 V

Total harmonic distortion plus noise

Output integrated noise floor -80 dB

20 Hz to 22 kHz, A-weighted filter, Gain = 15.6 dB

Crosstalk PO= 1 W, RL= 8 Ω, Gain = 15.6 dB, -93 dB

f = 1 kHz Maximum output at THD+N < 0.5%,

f = 1 kHz, Gain = 15.6 dB Thermal trip point 150 °C Thermal hystersis 20 °C

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Biases

and

References

TTL Input

Buffer

(VCC Compl)

Start-up and

Protection

Logic

Detect

Thermal

VDDok

RINP

RINN

Ramp Generator

COSC

ROSC

VCCok

5-V LDO

AVCC

AVDD

VDD

and PWM Mode Logic

Gain

Adj.

Gain

Control

Deglitch

and PWM Mode Logic

Gain

Adj.

LINP

LINN

Gate

Drive

VClamp

Gen

Gate

Drive

PVCC

BSRP PVCCR(2)

ROUTP(2)

PGNDR

ROUTN(2)

PVCCR(2)

BSRN

Gate Drive

VClamp

Gen

Gate

Drive

PVCC

BSLP PVCCL(2)

LOUTP(2)

PGNDL

LOUTN(2)

PVCCL(2)

BSLN

VCLAMPL

VCLAMPR

GAIN0

To Gain Adj. Blocks and Start-up Logic

SHUTDOWN

V2P5

AVCC AGND(2)

V2P5

Deglitch

GAIN1

AVDDREF

FAULT

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM

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13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

1 2 3 4 5 6 7 8 9 10 11 12

BSRN

PVCCR

ROUTN

PGNDR

ROUTP

PVCCR

BSRP

VCLAMPR NC NC

NC NC AGND

COSC ROSC AGND VCLAMPL

SHUTDOWN

RINN RINP V2P5

LINP

LINN

NC GAIN0 GAIN1 FAULT

BSLN

PVCCL

LOUTN

PGNDL

LOUTP

PVCCL

BSLP

TPA3008D2

AVDDREF

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

PHP PACKAGE

(TOP VIEW)

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TERMINAL FUNCTIONS

PIN NAME PIN NUMBER I/O DESCRIPTION

AGND 26, 30 - Analog ground for digital/analog cells in core AV

REF 7 O 5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1.

BSLN 13 - Bootstrap I/O for left channel, negative high-side FET BSLP 24 - Bootstrap I/O for left channel, positive high-side FET BSRN 48 - Bootstrap I/O for right channel, negative high-side FET BSRP 37 - Bootstrap I/O for right channel, positive high-side FET COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator.

FAULT 11 O

GAIN0 9 I Gain select least significant bit. TTL logic levels with compliance to AV GAIN1 10 I Gain select most significant bit. TTL logic levels with compliance to AV LINN 6 I Negative audio input for left channel LINP 5 I Positive audio input for left channel LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel

NC - No internal connection PGNDL 18, 19 - Power ground for left channel H-bridge

PGNDR 42, 43 - Power ground for right channel H-bridge PVCCL 14, 15 -

PVCCL 22, 23 -

PVCCR 38, 39 -

PVCCR 46, 47 RINP 3 I Positive audio input for right channel

RINN 2 I Negative audio input for right channel ROSC 27 I/O I/O current setting resistor for ramp generator. ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel

SHUTDOWN 1 I VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors.

VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors. V2P5 4 O 2.5-V Reference for analog cells.

Thermal Pad - -

33 - High-voltage analog power supply, not connected internally to PVCCR or PVCCL 29 O

5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. Not specified for driving other external circuitry.

Short-circuit detect fault output. FAULT = high, short-circuit detected. FAULT = low, normal operation. Status is reset when power is cycled or SHUTDOWN is cycled.

8, 12, 31, 32,

34, 35

Power supply for left channel H-bridge (internally connected to pins 22 and 23), not connected to PVCCR or AV

Power supply for left channel H-bridge (internally connected to pins 14 and 15), not connected to PVCCR or AV

Power supply for right channel H-bridge (internally connected to pins 46 and 47), not connected to PVCCL or AV

Power supply for right channel H-bridge (internally connected to pins 38 and 39), not connected to PVCCL or AV

Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.

Connect to AGND and PGND—should be the center point for both grounds. Internal resistive connection to AGND.

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0.01 20

20 k

100

1 k 10 k

THD+N −Total Harmonic Distortion + Noise − %

VCC = 18 V , RL = 16  Gain = 21.6 dB

f − Frequency − Hz

0.1

PO = 2.5 W

PO = 0.5 W

PO = 1 W

0.005

0.01

0.1

20 k

100

1 k

10 k

PO = 2.5 W

THD+N −Total Harmonic Distortion + Noise − %

VCC = 12 V , RL = 16 , Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

PO = 0.5 W

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4 THD+N Total harmonic distortion + noise vs Output power 5, 6

Closed-loop response 7 Output power vs Supply voltage 8, 9 Efficiency vs Output power 10 Efficiency vs Total output power 11

SVR

CMRR Commom-mode rejection ratio vs Frequency 15

Supply current vs Total output power 12 Crosstalk vs Frequency 13 Supply ripple rejection ratio vs Frequency 14

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 1. Figure 2.

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0.005

0.01

0.1

20 k

100

1 k 10 k

PO = 5 W

THD+N −Total Harmonic Distortion + Noise − %

VCC = 18 V , RL = 8 , Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

PO = 2.5 W

0.01

0.1

20 k

100

1 k 10 k

THD+N −Total Harmonic Distortion + Noise − %

VCC = 12 V , RL = 8  Gain = 21.6 dB

f − Frequency − Hz

PO = 1 W

PO = 2.5 W

PO = 0.5 W

0.01

0.1

20m 10100 m 1

THD+N −Total Harmonic Distortion + Noise − %

PO− Output Power − W

VCC = 12 V , RL = 8 , Gain = 21.6 dB

20200 m 2

1 kHz

20 Hz

20 kHz

0.01

0.1

20m 10100 m 1

THD+N −Total Harmonic Distortion + Noise − %

PO− Output Power − W

VCC = 18 V , RL = 16 , Gain = 21.6 dB

20 Hz

20200 m 2

20 kHz

1 kHz

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 5. Figure 6.

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10 100 1k

Gain − dB

f − Frequency − Hz

10k

80k

VCC = 12 V , RL = 8 Ω, Gain = 32 dB 33 kHz, RC LPF

Gain

Phase

Phase −

100

−150



−100

−50

150

8 9

10 11 12 13 14 15 16 17 18

− Output Power − W

THD+N = 10%

THD+N = 1%

RL = 16 

VCC − Supply Voltage − V

8 9 10 11 12 13 14

THD+N = 1%

THD+N = 10%

RL = 8 

VCC − Supply Voltage − V

− Output Power − W

Power represented by dashed line may require external heatsinking

0 1 2 3 4 5 6

PO − Output Power (Per Channel) − W

Efficiency − %

100

7 8 9 10

VCC = 18 V , RL = 16 

CLOSED-LOOP RESPONSE SUPPLY VOLTAGE

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

OUTPUT POWER

OUTPUT POWER EFFICIENCY

SUPPLY VOLTAGE OUTPUT POWER

Figure 7. Figure 8.

vs vs

Figure 9. Figure 10.

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100

0 1 2 3 4 5 6 7 8 9 10

Efficiency − %

16 

8 

PO − Total Output Power − W

11 12

VCC = 12 V , LC Filter, Resistive Load, Stereo Operation

0.2

0.4

0.6

0.8

1.2

1.4

0 2 4 6 8 10 12

PO − Total Output Power − W

1.6

1.8

2.0

14 16 18 20

LC Filter, Resistive Load, Stereo Operation

− Supply Current − AV CC

VCC = 18 V , RL = 16 

VCC = 12 V ,

RL = 16 

VCC = 12 V ,

RL = 8 

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

20 100 1 k 10 k

Crosstalk − dB

f − Frequency − Hz

VCC = 12 V , PO = 2.5 W, Gain = 21.6 dB RL = 8

20 k

−100

−90

−80

−70

−60

−50

−40

20 100 1 k 10 k

f − Frequency − Hz

SVR

− Supply Ripple Rejection Ratio − dB

VCC = 12 V , V

(RIPPLE)

= 200 mVPP, RL = 8 , Gain = 15.6 dB

20 k

−30

−20

−10

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

TOTAL OUTPUT POWER TOTAL OUTPUT POWER

EFFICIENCY SUPPLY CURRENT

vs vs

Figure 11. Figure 12.

CROSSTALK SUPPLY RIPPLE REJECTION RATIO

vs vs

FREQUENCY FREQUENCY

Figure 13. Figure 14.

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−70

−60

−50

−40

−30

−20

−10

100 1 k 10 k20

VCC = 12 V , Gain = 15.6 dB, RL = 8  Output Referred

f − Frequency − Hz

CMRR − Common-Mode Rejection Ratio − dB

20 k

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

COMMON-MODE REJECTION RATIO

FREQUENCY

Figure 15.

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220 nF

PVCC PVCC

220 nF 220 nF

PVCC PVCC

220 pF

Right Differential

Inputs

Shutdown/Mute

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

PVCCL

BSLN

TPA3008D2

VCLAMPR

SHUTDOWN

V2P5

RINP

LINN

LINP

AVDDREF NC GAIN0 GAIN1

AVDD

AGND

COSC ROSC

AVCC

VCLAMPL

BSRP

PVCCR

ROUTP

PGNDR

ROUTN

PVCCR

BSRN

RINN

AVCC

AGND

10 F10 F

0.1 F

0.47 F

0.1 F 0.1 F

10 F 10 F

1 F

120 k

1 F

FAULT

0.1 F

10 F

1 F

Control

Left Differential

Inputs

Gain

Control

1 nF1 nF

 



Chip ferrite bead (example: Fair-Rite 251206700743) shown for EMI suppression.

1 nF



Fault Reporting

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

APPLICATION INFORMATION

Figure 16. Stereo Class-D With Differential Inputs

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0 V

−12 V

+12 V

Current

OUTP

Differential Voltage

Across Load

OUTN

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

APPLICATION INFORMATION (continued) CLASS-D OPERATION

This section focuses on the class-D operation of the TPA3008D2.

Traditional Class-D Modulation Scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, V the differential prefiltered output varies between positive and negative V

, where filtered 50% duty cycle yields

0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 17 . Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current.

. Therefore,

TPA3008D2 Modulation Scheme

The TPA3008D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

Figure 17. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an

Inductive Load With No Input

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0 V

−12 V

+12 V

Current

OUTP

OUTN

Differential

Voltage

Across

Load

0 V

−12 V

+12 V

Current

OUTP

OUTN

Differential

Voltage

Across

Load

Output = 0 V

Output > 0 V

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

APPLICATION INFORMATION (continued)

Figure 18. The TPA3008D2 Output Voltage and Current Waveforms Into an Inductive Load

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x V the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3008D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is V ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most

instead of 2 x V

. As the output power increases, the pulses widen, making the

applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow

through the filter instead of the load. The filter has less resistance than the speaker, which results in less power dissipation, therefore increasing efficiency.

, and the time at each voltage is half the period for

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Efficiency (theoretical, %) 



RL r

ds(on)



 100% 

(8  1.3)

 100%  86%

(total)



Efficiency



8.5 W

0.86

 9.88 W

Other losses  P

(total)

(measured)  P

(total)

(theoretical)  10.49  9.88  0.61 W

(dis)

 0.61 W  (12 V  22 mA)  0.35 W

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

APPLICATION INFORMATION (continued) Effects of Applying a Square Wave Into a Speaker

Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f frequencies beyond the audio band.

Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency switching current. The amount of power dissipated in the speaker may be estimated by first considering the overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the dominant loss in the system, then the maximum theoretical efficiency for the TPA3008D2 with an 8-Ω load is as follows:

The maximum measured output power is approximately 8.5 W with an 12-V power supply. The total theoretical power supplied (P(total)) for this worst-case condition would therefore be as follows:

The efficiency measured in the lab using an 8-Ω speaker was 81%. The power not accounted for as dissipated across the r

may be calculated by simply subtracting the theoretical power from the measured power:

DS(on)

for

(1)

(2)

The quiescent supply current at 12 V is measured to be 22 mA. It can be assumed that the quiescent current encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any remaining power is dissipated in the speaker and is calculated as follows:

Note that these calculations are for the worst-case condition of 8.5 W delivered to the speaker. Because the 0.35 W is only 4% of the power delivered to the speaker, it may be concluded that the amount of power actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the power generated from a clipping waveform.

When to Use an Output Filter for EMI Suppression

Design the TPA3008D2 without the filter if the traces from amplifier to speaker are short (< 50 cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter.

Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies.

Use a LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker.

When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter.

(3)

(4)

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0.1 µF

0.47 µF

33 µH

OUTP

OUTN

1 nF

Ferrite

Chip Bead

OUTP

OUTN

Ferrite

Chip Bead

1 nF

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

APPLICATION INFORMATION (continued)

Figure 19. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

Figure 20. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)

Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3008D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This

causes the input impedance (Z

) to be dependent on the gain setting. The actual gain settings are controlled by

ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift by 20% due to shifts in the actual resistance of the input resistors.

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 26 kΩ, which is the absolute minimum input impedance of the TPA3008D2. At the lower gain settings, the input impedance could increase as high as 165 kΩ

Table 1. Gain Setting

GAIN1 GAIN0

0 0 15.3 137 0 1 21.2 88 1 0 27.2 52 1 1 31.8 33

AMPLIFIER GAIN (dB)

TYP TYP

INPUT IMPEDANCE

(kΩ)

INPUT RESISTANCE

Each gain setting is achieved by varying the input resistance of the amplifier that can range from its smallest value, 33 kΩ, to the largest value, 137 kΩ. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency changes when changing gain steps.

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Input

Signal

f 

2 Z

iCi



2 ZiC

−3 dB



2 Z

The -3-dB frequency can be calculated using Equation 5. Use Table 1 for Zivalues.

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

(5)

INPUT CAPACITOR, C

In the typical application, an input capacitor (C proper dc level for optimum operation. In this case, C

) is required to allow the amplifier to bias the input signal to the

and the input impedance of the amplifier (Z

) form a

high-pass filter with the corner frequency determined in Equation 6 .

The value of Ciis important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where Ziis 137 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is reconfigured as Equation 7 .

In this example, Ciis 58 nF; so, one would likely choose a value of 0.1 µF as this value is commonly used. If the gain is known and is constant, use Zifrom Table 1 to calculate Ci. A further consideration for this capacitor is the leakage path from the input source through the input network (C

) and the feedback network to the load. This

leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

For the best pop performance, CIshould be less than or equal to 1µF.

(6)

(7)

Power Supply Decoupling,C

The TPA3008D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device V lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio

lead works best. For filtering

power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from xOUTP to xBSP, and one 220-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit diagram in Figure 16 .)

The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

VCLAMP Capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25) and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary with V

and may not be used for powering any other circuitry.

Internal Regulated 5-V Supply (AV

The AV

terminal (pin 29) is the output of an internally generated 5-V supply, used for the oscillator,

)

preamplifier, and volume control circuitry. It requires a 1-µF capacitor, placed close to the pin, to keep the regulator stable.

This regulated voltage can be used to control GAIN0 and GAIN1 terminals, but should not be used to drive external circuitry.

Differential Input

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3008D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3008D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance.

SHUTDOWN OPERATION

The TPA3008D2 employs a shutdown mode of operation designed to reduce supply current (I minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage.

) to the absolute

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

The TPA3008D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-V outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state for normal operation. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates.

The fault terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO.

THERMAL PROTECTION

Thermal protection on the TPA3008D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20°C. The device begins normal operation at this point with no external system interaction.

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3008D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.

• Decoupling capacitors—The high-frequency 0.1-µF decoupling capacitors should be placed as close to the PVCC (pins 14, 15, 22, 23, 38, 39, 46, and 47) and AV capacitor, AV to the device as possible. Large (10 µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3008D2 on the PVCCL, PVCCR, and AV

• Grounding—The AV (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pins 26 and 30). The PVCC decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42, and 43). Analog ground and power ground may be connected at the PowerPAD, which should be used as a central ground connection or star ground for the TPA3008D2. Basically, an island should be created with a single connection to PGND at the PowerPAD.

• Output filter—The ferrite EMI filter (Figure 20 ) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 19 ) should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC filter should be placed first, following the outputs.

• PowerPAD—The PowerPAD must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils). The PowerPAD size measures 4,55 x 4,55 mm. Four rows of solid vias (four vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For additional information, see the PowerPAD Thermally Enhanced Package application note, (SLMA002).

For an example layout, see the TPA3008D2 Evaluation Module (TPA3008D2EVM) User Manual, (SLOU165). Both the EVM user manual and the PowerPAD application note are available on the TI Web site at http://www.ti.com.

(pin 29) capacitor, and VCLAMP (pins 25 and 36) capacitor should also be placed as close

(pin 33) decoupling capacitor, AV

shorts. When a short circuit is detected on the

(pin 33) terminals as possible. The V2P5 (pin 4)

terminals.

(pin 29) capacitor, V2P5 (pin 4) capacitor, COSC

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TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:

• Audio analyzer or spectrum analyzer

• Digital multimeter (DMM)

• Oscilloscope

• Twisted-pair wires

• Signal generator

• Power resistor(s)

• Linear regulated power supply

• Filter components

• EVM or other complete audio circuit

Figure 21 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (C attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer-input impedance should be high. The output impedance, R of milliohms and can be ignored for all but the power-related calculations.

Figure 21 (a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.

This is not true of the class-D amplifier system shown in Figure 21 (b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.

), so no additional coupling is required. The generator output impedance should be low to avoid

, of the APA is normally in the hundreds

OUT

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Analyzer

20 Hz − 20 kHz

(a) Basic Class−AB

APA

Signal

Generator

Power Supply

Analyzer

20 Hz − 20 kHz

(b) Filter-Free and Traditional Class-D

Class-D APA

Signal

Generator

Power Supply

Low-Pass RC

Filter

Low-Pass RC

Filter

(A)

For efficiency measurements with filter-free class-D, RL should be an inductive load like a speaker.

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

Figure 21. Audio Measurement Systems

The TPA3008D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave.

DIFFERENTIAL INPUT AND BTL OUTPUT

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in Figure 22 . The differential input is a balanced input, meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output.

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Audio Power

Amplifier

Generator

Low−Pass

RC Filter

GEN

OUT

Analyzer

ANA

Low−Pass

RC Filter

ANA

Twisted-Pair Wire

Evaluation Module

Twisted-Pair Wire

TPA3008D2

SLOS435A – MAY 2004 – REVISED JULY 2004

Figure 22. Differential Input, BTL Output Measurement Circuit

The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:

• Use a balanced source to supply the input signal.

• Use an analyzer with balanced inputs.

• Use twisted-pair wire for all connections.

• Use shielding when the system environment is noisy.

• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large

currents (see Table 2 ).

Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.

Table 2. Recommended Minimum Wire Size for Power Cables

(W) RL(Ω) AWG Size

OUT

10 4 18 22 16 40 18 42

2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1

< 0.75 8 22 28 1.5 6.1 1.6 6.2

DC POWER LOSS AC POWER LOSS

(MW) (MW)

CLASS-D RC LOW-PASS FILTER

An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).

The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 23 . R is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for R system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops.

and C

ANA

. The filter components, R

ANA

FILT

and C

, can then be derived for the

FILT

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FILT

VL= V

OUT

ANA

FILT

To APA

GND

AP Analyzer Input

RC Low-Pass Filters

Load



OUT







ANA

ANARFILT



1  j







fC 2 f

MAX

FILT



2  fC R

FILT

SLOS435A – MAY 2004 – REVISED JULY 2004

Figure 23. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs

TPA3008D2

The transfer function for this circuit is shown in Equation 8 where ω C

= (C

+ C

FILT

). The filter frequency should be set above f

ANA

MAX

, the highest frequency of the measurement

= R

, R

= R

|| R

FILT

ANA

bandwidth, to avoid attenuating the audio signal. Equation 9 provides this cutoff frequency, fC. The value of R must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R that R 1% for R

An exception occurs with the efficiency measurements, where R reduce the current shunted through the filter. C

should be small (~100 Ω) for most measurements. This reduces the measurement error to less than

FILT

≥ 10 kΩ.

ANA

must be increased by a factor of ten to

must be decreased by a factor of ten to maintain the same

FILT

and R

FILT

. A rule of thumb is

ANA

cutoff frequency. See Table 3 for the recommended filter component values. Once fCis determined and R

is selected, the filter capacitance is calculated using Equation 9 . When the

FILT

calculated value is not available, it is better to choose a smaller capacitance value to keep fCabove the minimum desired value calculated in Equation 10 .

Table 3 shows recommended values of R was originally calculated to be 28 kHz for an f

and C

FILT

MAX

of 20 kHz. C

based on common component values. The value of f

FILT

, however, was calculated to be 57,000 pF, but

FILT

the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and fCis 34 kHz, which is above the desired value of 28 kHz.

and

FILT

(8) (9)

(10)

MEASUREMENT R

All other measurements 100 Ω 56,000 pF

Table 3. Typical RC Measurement Filter Values

FILT

Efficiency 1000 Ω 5,600 pF

FILT

PACKAGE OPTION ADDENDUM

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26-Mar-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPA3008D2PHP ACTIVE HTQFP PHP 48 250 Green (RoHS &

no Sb/Br)

TPA3008D2PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS &

no Sb/Br)

TPA3008D2PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS &

no Sb/Br)

TPA3008D2PHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-4-260C-72HR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX INFORMATION

5-Oct-2007

Device Package Pins Site Reel

Diameter

(mm)

TPA3008D2PHPR PHP 48 SITE60 330 16 9.6 9.6 1.5 12 16 Q2

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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5-Oct-2007

Device Package Pins Site Length (mm) Width (mm) Height (mm)

TPA3008D2PHPR PHP 48 SITE 60 346.0 346.0 33.0

Pack Materials-Page 2

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Texas Instruments TPA3008D2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

AVAILABLE OPTIONS

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

Traditional Class-D Modulation Scheme

TPA3008D2 Modulation Scheme

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

When to Use an Output Filter for EMI Suppression

Gain setting via GAIN0 and GAIN1 inputs

INPUT RESISTANCE

BSN and BSP Capacitors

VCLAMP Capacitors

Differential Input

SHUTDOWN OPERATION

USING LOW-ESR CAPACITORS

SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

THERMAL PROTECTION

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

BASIC MEASUREMENT SYSTEM

DIFFERENTIAL INPUT AND BTL OUTPUT

CLASS-D RC LOW-PASS FILTER