Texas Instruments TPA3003D2 User Manual
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
FEATURES
D
3-W/Ch Into an 8-Ω Load From 12-V Supply
D Efficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
D 32-Step DC Volume Control From −40 dB
to 36 dB
D Third Generation Modulation Techniques
− Replaces Large LC Filter With Small
Low-Cost Ferrite Bead Filter
D Thermal and Short-Circuit Protection
APPLICATIONS
D
LCD Monitors and TVs
D Powered Speakers
PVCC PVCC
10 nF
Cs
0.1 µF
Cbs
Cs
BSRN
PVCCR
PVCCR
ROUTN
BSLN
PVCCL
PVCCL
ROUTN
TPA3003D2
LOUTN
LOUTN
SYSTEM CONTROL
RINN
RINP
LINP
LINN
VOLUME
Crinp
1 µF
Clinp
1 µF
Crinn
1 µF
C2p5
1 µF
Clinn
1 µF
RINN
RINP
V2P5
LINP
LINN
AVDDREF
VREF
AGND
AGND
VOLUME
REFGND
PGNDR
PGNDL
10 µF10 µF
Cs
0.1 µF
Cs
PGNDR
PGNDL
ROUTP
LOUTP
DESCRIPTION
The TPA3003D2 is a 3-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3003D2 can drive stereo speakers
as low as 8 Ω. The high efficiency of the TPA3003D2
eliminates the need for external heatsinks when playing
music.
Stereo speaker volume is controlled with a dc voltage
applied to the volume control terminal offering a range
of gain from –40 dB to 36 dB.
10 nF
Cbs
ROUTP
LOUTP
PVCCR
PVCCL
PVCCR
VCLAMPRSD
VCLAMPL
PVCCL
BSRP
MUTE
AVCC
FADE
AVDD
COSC
ROSC
AGND
BSLP
Ccpr
1 µF
NC
NC
NC
AVDD
Cvdd
Cosc
100 nF
Rosc
220 pF
120 kΩ
Ccpl
1 µF
MUTE CONTROL
SYSTEM CONTROL
Cs
0.1 µF
AVCC
Cvcc
10 µF
Cbs
0.1 µF
Cs
10 nF
10 µF
PVCC PVCC
0.1 µF
Cs
10 µF
Cbs
10 nF
Cs
Cs
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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#- && $##(
Copyright 2003, Texas Instruments Incorporated
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1
T
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
−40°C to 85°C TPA3003D2PFB
†
The PFB package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3003D2PFBR).
BSRN
48 47 46 45 44 43 42 41 40 39 38 37
A
PVCCR
AVAILABLE OPTIONS
PHP PACKAGE
(TOP VIEW)
PVCCR
ROUTN
ROUTN
PGNDR
PACKAGED DEVICE
48-PIN TQFP (PFB)
PGNDR
ROUTP
ROUTP
PVCCR
PVCCR
†
BSRP
SD
RINN
RINP
V2P5
LINP
LINN
AVDDREF
VREF
AGND
AGND
VOLUME
REFGND
1
2
3
4
5
6
7
8
9
10
11
12
TPA3003D2
13
14 15 16 17 18 19 20 21 22 23 24
BSLN
PVCCL
PVCCL
LOUTN
LOUTN
PGNDL
LOUTP
PGNDL
LOUTP
PVCCL
PVCCL
36
35
34
33
32
31
30
29
28
27
26
25
BSLP
VCLAMPR
NC
MUTE
AV
CC
NC
NC
FADE
AV
DD
COSC
ROSC
AGND
VCLAMPL
2
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)
functional block diagram
V2P5
V2P5
RINN
RINP
VREF
VOLUME
FADE
REFGND
ROSC
COSC
AVDDREF
AVDD
SD
MUTE
V2P5
Gain
Gain
Control
Adj.
TTL Input
Buffer
AVDD
To Gain Adj.
Blocks
Ramp
Generator
5V LDO
V2P5
Biases
References
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
PVCC
VClamp
Gen
Gate
Drive
Deglitch &
Modulation
Logic
Gate
Drive
Short Circuit
Detect
Startup
PVCC
VClamp
Gen
Protection
Logic
&
Thermal
VDDok
VCCok
VDD
AVCC
VCLAMPR
BSRN
PVCCR(2)
ROUTN(2
PGNDR
BSRP
PVCCR(2)
ROUTP(2)
PGNDR
AVCC
AGND
VCLAMPL
BSLN
PVCCL(2)
LINN
LINP
V2P5
Gain
Adj.
Rfdbk2
Rfdbk2
Cint2
Cint2
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Deglitch &
Modulation
Logic
Gate
Drive
Gate
Drive
LOUTN(2)
PGNDL
BSLP
PVCCL(2)
LOUTP(2)
PGNDL
3
I/O
DESCRIPTION
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
Terminal Functions
TERMINAL
NO. NAME
AGND 9, 10, 26 − Analog ground for digital/analog cells in core
AV
CC
AV
DD
AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET
BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET
BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET
BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET
COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
FADE 30 I Input for controlling volume ramp rate when cycling SD or during power-up. A logic low on this pin places
LINN 6 I Negative differential audio input for left channel
LINP 5 I Positive differential audio input for left channel
LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel
LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel
MUTE 34 I A logic high on this pin disables the outputs. A low on this pin enables the outputs.
NC 31, 32,
PGNDL 18, 19 − Power ground for left channel H-bridge
PGNDR 42, 43 − Power ground for right channel H-bridge
PVCCL 14, 15 − Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or
PVCCL 22, 23 − Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or
PVCCR 38,39 − Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or
PVCCR 46, 47 − Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or
REFGND 12 − Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
RINP 3 I Positive differential audio input for right channel
RINN 2 I Negative differential audio input for right channel
ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*V
ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel
ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel
SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VCLAMPL 25 − Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR 36 − Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME 11 I DC voltage that sets the gain of the amplifier.
VREF 8 I Analog reference for gain control section.
V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended
33 − High-voltage analog power supply (8.5 V to 14 V)
29 O 5-V Regulated output
the amplifier in fade mode. A logic high on this pin allows a quick transition to the desired volume setting.
− Not internally connected
35
AVCC.
AVCC.
AVCC.
AVCC.
ground to this terminal.
CC
inputs.
4
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IH
High-level input voltage, V
IH
V
IL
Low-level input voltage, V
IL
V
IH
High-level input current, I
IH
µA
IL
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: AV
Input voltage range, V
: MUTE, VREF, VOLUME, FADE 0 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Supply current, AV
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Operating junction temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
PFB 2.8 W 22.2 mW/°C 1.8 W 1.4 W
recommended operating conditions
Supply voltage, V
Volume reference voltage VREF 3.0 5.5 V
Volume control pins, input voltage VOLUME 5.5 V
High-level input voltage, V
Low-level input voltage, V
High-level input current, I
Low-level input current, I
Oscillator frequency, f
Operating free-air temperature, T
CC
OSC
SD
CC,
PV
CC
−0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RINN, RINP, LINN, LINP −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
AVDDREF 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
J
stg
DISSIPATION RATING TABLE
TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PVCC, AV
SD 2
MUTE 3.5
FADE 4
SD 0.8
MUTE 2
FADE 2
MUTE, VI= 5 V, VCC = 14 V 1
SD, VI= 14 V, VCC = 14 V 50
FADE, VI= 5 V, VCC = 14 V 150
MUTE, SD, FADE, VI= 0 V, VCC = 14 V 1 µA
A
CC
225 275 kHz
−40 85 °C
MIN MAX UNIT
8.5 14 V
−40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
V
µA
†
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5
V
= 12 V,
VCC = 12 V,
r
ds(on)
Drain-source on-state resistance
IO = 1 A,
m
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
dc characteristics, T
| VOS |
V2P5 (terminal 4) 2.5-V Bias voltage No load
PSRR Power supply rejection ratio VCC = 11.5 V to 12.5 V −80 dB
I
CC
I
CC(MUTE)
I
CC(max power)
I
CC(SD)
r
ds(on)
ac characteristics, T
k
SVR
P
O(max)
V
n
SNR Signal-to-noise ratio
Supply ripple rejection ratio
Maximum continuous output power
Output integrated noise floor
Crosstalk, Left → Right Gain = 13.2 dB, PO = 1 W, RL = 8 Ω −77 dB
Thermal trip point 150 °C
Thermal hystersis 20 °C
= 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
A
PARAMETER
Output offset voltage (measured
differentially)
Supply quiescent current MUTE = 2 V, SD = 2 V 16 28.5 mA
MUTE mode quiescent current MUTE = 3.5 V, SD = 2 V 7 9 mA
Supply current at max power RL = 8 Ω, PO = 3 W 0.6 A
Supply current in shutdown mode SD = 0.8 V 1 10 µA
Drain-source on-state resistance
= 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
A
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
VCC = 11.5 V to 12.5 V from 10 Hz
to 1 kHz, Gain = 36 dB
THD+N = 1%, f = 1 kHz, RL = 8 Ω 3 W
THD+N = 10%, f = 1 kHz, RL = 8 Ω
20 Hz to 22 kHz, No weighting filter,
Gain = 0.5 dB
Maximum output at THD+N < 0.5%,
f= 1 kHz, Gain = 0.5 dB
TEST CONDITIONS MIN TYP MAX UNIT
INN and INP connected together,
Gain = 36 dB
High side
IO = 1 A,
TJ = 25°C
Low side
Total
0.45x
AV
DD
10 65 mV
0.5x
AV
AV
DD
600
600
1200
−67 dB
3.75 W
−82 dBV
102 dB
0.55x
DD
700
700
1400
V
mΩ
6
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Table 1. DC Volume Control
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (INCREASING
VOLUME OR FIXED
GAIN)
% %
0 − 4.5 0 − 2.9 −75
4.5 − 6.7 2.9 − 5.1 −40.0
6.7 − 8.91 5.1 − 7.2 −37.5
8.9 − 11.1 7.2 − 9.4 −35.0
11.1 − 13.3 9.4 − 11.6 −32.4
13.3 − 15.5 11.6 − 13.8 −29.9
15.5 − 17.7 13.8 − 16.0 −27.4
17.7 − 19.9 16.0 − 18.2 −24.8
19.9 − 22.1 18.2 − 20.4 −22.3
22.1 − 24.3 20.4 − 22.6 −19.8
24.3 − 26.5 22.6 − 24.8 −17.2
26.5 − 28.7 24.8 − 27.0 −14.7
28.7 − 30.9 27.0 − 29.1 −12.2
30.9 − 33.1 29.1 − 31.3 −9.6
33.1 − 35.3 31.3 − 33.5 −7.1
35.3 − 37.5 33.5 − 35.7 −4.6
37.5 − 39.7 35.7 − 37.9 −2.0
39.7 − 41.9 37.9 − 40.1 0.5
41.9 − 44.1 40.1 − 42.3 3.1
44.1 − 46.4 42.3 − 44.5 5.6
46.4 − 48.6 44.5 − 46.7 8.1
48.6 − 50.8 46.7 − 48.9 10.7
50.8 − 53.0 48.9 − 51.0 13.2
53.0 − 55.2 51.0 − 53.2 15.7
55.2 − 57.4 53.2 − 55.4 18.3
57.4 − 59.6 55.4 − 57.6 20.8
59.6 − 61.8 57.6 − 59.8 23.3
61.8 − 64.0 59.8 − 62.0 25.9
64.0 − 66.2 62.0 − 64.2 28.4
66.2 − 68.4 64.2 − 66.4 30.9
68.4 − 70.6 66.4 − 68.6 33.5
> 70.6 >68.6 36.0
†
Tested in production. Remaining steps are specified by design.
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (DECREASING
VOLUME)
GAIN OF AMPLIFIER
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
dB
†
†
†
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7
O
POOutput power
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
Efficiency vs Output power 1
P
I
Q
I
CC
I
Q(sd)
THD+N Total harmonic distortion + noise
k
SVR
Output power
Quiescent supply current vs Supply voltage 4
Supply current vs Output Power 5
Quiescent shutdown supply current vs Supply voltage 6
Input impedance vs Gain 7
Supply ripple rejection ratio vs Frequency 12
Closed loop response 13, 14
Intermodulation performance 15
Input offset voltage vs Common-mode input voltage 16
Crosstalk vs Frequency 17
Mute attenuation
Shutdown attenuation
Common-mode rejection ratio vs Frequency 20
Table of Graphs
vs Load resistance
vs Supply voltage
vs Frequency
vs Output power
vs Frequency
FIGURE
2
3
8, 9
10, 11
18
19
8
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OUTPUT POWER
OUTPUT POWER
80
70
60
50
40
30
Efficiency − %
20
10
EFFICIENCY
vs
OUTPUT POWER
VCC = 12 V, RL = 8 Ω
VCC = 8.5 V, RL = 8 Ω
LC Filter
Resistive Load
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
8
7
6
VCC = 12 V,
THD = 10%
5
4
3
− Output Power − W
O
P
2
1
vs
LOAD RESISTANCE
Thermally Limited
VCC = 8.5 V,
THD = 10%
VCC = 12 V,
THD = 1%
VCC = 8.5 V,
THD = 1%
0
0 0.5 1 1.5 2 2.5 3
PO − Output Power − W
Figure 1
vs
SUPPLY VOLTAGE
6
5
4
3
− Output Power − W
O
P
2
1
8.5 9 10 11 12 13 14
VDD − Supply Voltage − V
Thermally Limited
8 Ω, THD = 10%
8 Ω, THD = 1%
0
8 9 10 11 12 13 14 15 16
RL − Load Resistance − Ω
Figure 2
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
18
17
16
15
14
13
12
Q
I − Quiescent Supply Current − mA
11
10
8.59 1011121314
TA = 25°C
VCC − Supply Voltage − V
Figure 3
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Figure 4
9
QUIESCENT SHUTDOWN SUPPLY CURRENT
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
OUTPUT POWER (TOTAL)
0.8
VCC = 12 V,
RL = 8 Ω
0.7
0.6
0.5
vs
SUPPLY VOLTAGE
Aµ
1
0.8
0.4
− Supply Current − A
0.3
CC
I
0.2
0.1
0
0123456
PO − Output Power (Total) − W
Figure 5
INPUT IMPEDANCE
vs
GAIN
120
100
Ω
80
60
40
− Input Impedance − k
i
Z
20
0
−50 −30 −10 10
Gain − dB
30 50
0.6
0.4
0.2
− Quiescent Shutdown Supply Current −
CC
I
0
8.5 9 10 11 12 13 14
VSD = 0.8 V
VSD = 0 V
VCC − Supply Voltage − V
Figure 6
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 12 V,
RL = 8 Ω,
5
TA = 25°C
2
1
0.5
PO = 1 W
0.2
0.1
0.05
0.02
THD+N − Total Harmonic Distortion + Noise − %
0.01
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
PO = 3 W
f − Frequency − Hz
PO = 0.5 W
10
Figure 7
Figure 8
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TOTAL HARMONIC DISTORTION + NOISE
SUPPLY RIPPLE REJECTION RATIO
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 12 V,
5
RL = 8 Ω,
TA = 25°C
2
1
0.5
0.2
0.1
0.05
0.02
THD+N − Total Harmonic Distortion + Noise − %
0.01
PO = 0.5 W
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
PO = 1 W
PO = 3.5 W
f − Frequency − Hz
Figure 9
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
10
VCC = 8.5 V,
RL = 8 Ω,
5
TA = 25°C
2
1
0.5
0.2
0.1
0.05
0.02
THD+N − Total Harmonic Distortion + Noise − %
0.01
f = 20 KHz
20m 50m 100m 200m 500m 1 2 5 10
vs
OUTPUT POWER
f = 1 kHz
f = 20 Hz
PO − Output Power − W
Figure 10
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 12 V,
RL = 8 Ω,
5
TA = 25°C
2
1
0.5
0.2
0.1
0.05
0.02
THD+N − Total Harmonic Distortion + Noise − %
0.01
f = 1 kHz
f = 20 Hz
f = 20 kHz
20m 50m 100m 200m 500m 1 2 5 10
PO − Output Power − W
Figure 11
vs
FREQUENCY
−40
VCC = 12 V,
−45
RL = 8 Ω
−50
−55
−60
−65
−70
−75
− Supply Ripple Rejection Ratio − dB
−80
SVR
−85
k
−90
20 100 1 k 10 k 100 k
f − Frequency − Hz
Figure 12
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11
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