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0
10
20
30
40
50
60
70
80
90
0 4 8 12 16 20
PO − Output Power − W
EFFICIENCY
vs
OUTPUT POWER
4 Ω
8 Ω
Efficiency − %
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA = 25°C,
10% THD Maximum
RL − Load Impedance − Ω
− Output Power − W
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
P
O
VCC = 18 V
20-W MONO CLASS-D AUDIO POWER AMPLIFIER
FEATURES DESCRIPTION
• 20 W Into 8- Ω Load From 18-V Supply (10%
THD+N)
• Short Circuit Protection (Short to V
to GND, Short Between Outputs)
• Third-Generation Modulation Technique:
– Replaces Large LC Filter With Small,
Low-Cost Ferrite Bead Filter in Most
Applications
– Improved Efficiency
– Improved SNR
• Low Supply Current: 8 mA Typ at 12 V
• Shutdown Control: < 1 µ A Typ
• Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
APPLICATIONS
• LCD Monitors/TVs
• Hands-Free Car Kits
• Powered Speakers
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
The TPA3001D1 (sometimes referred to as
TPA3001) is a 20-W mono bridge-tied load (BTL)
, Short
CC
class-D audio power amplifier (class-D amp) with
high efficiency, eliminating the need for heat sinks.
The TPA3001D1 (TPA3001) can drive 4- Ω or 8- Ω
speakers with only a ferrite bead filter required to
reduce EMI.
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the
amplifier to be configured for a gain of 12, 18, 23.6,
and 36 dB. The differential input stage provides high
common mode rejection and improved power supply
rejection.
The amplifier also includes depop circuitry to reduce
the amount of pop at power-up and when cycling
SHUTDOWN.
The TPA3001D1 (TPA3001) is available in the 24-pin
thermally enhanced TSSOP package (PWP) which
eliminates the need for an external heat sink.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
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1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
INN
INP
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
BSN
PV
CC
OUTN
OUTN
PGND
V
CC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PV
CC
OUTP
OUTP
PGND
PWP PACKAGE
(TOP VIEW)
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
(1) For the most current package and ordering information, see the
(2) The PWP package is available taped and reeled. To order a taped
AVAILABLE OPTIONS
T
A
–40 ° C to 85 ° C TPA3001D1PWP
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
and reeled part, add the suffix R to the part number (e.g.,
TPA3001D1PWPR).
PACKAGED DEVICES
(1)
TSSOP (PWP)
(2)
Terminal Functions
TERMINAL
NAME NO.
AGND 18, 19 Analog ground terminal
BSN 8 I
BSP 17 I
BYPASS 22 I Connect 1- µ F capacitor to ground for BYPASS voltage filtering
COSC 21 I Connect a 220-pF capacitor to ground to set oscillation frequency
GAIN0 3 I Bit 0 of gain control (see Table 1 for gain settings)
GAIN1 4 I Bit 1 of gain control (see Table 1 for gain settings)
INN 1 I Negative differential input
INP 2 I Positive differential input
OUTN 10, 11 O Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit protection
OUTP 14, 15 O Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection
PGND 6, 12, 13 Power ground
PV
CC
ROSC 20 I Connect 120 k Ω resistor to ground to set oscillation frequency
SHUTDOWN 5 I Shutdown terminal (negative logic), TTL compatible, 21-V compliant
V
CC
VCLAMP 7 O Connect 1- µ F capacitor to ground to provide reference voltage for H-bridge gates
VREF 23 O 5-V internal regulator for control circuitry (connect a 0.1- µ F to 1- µ F capacitor to ground)
Thermal Pad - -
2
9, 16 I High-voltage power supply (for output stages)
24 I Analog high-voltage power supply
I/O DESCRIPTION
Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22- µ F capacitor
with a 51- Ω resistor in series from OUTN to BSN)
Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22- µ F capacitor
with a 51- Ω resistor in series from OUTP to BSP)
Connect to AGND and PGND - should be star point for both grounds. Internal resistive connection
to AGND. Thermal vias on the PCB should connect this pad to a large copper area on an internal
or bottom layer for the best thermal performance. The PAD must be soldered to the PCB for
mechanical reliability.
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FUNCTIONAL BLOCK DIAGRAM
Gate
Drive
_
+
Gate
Drive
_
+
_
+
_
+
Gain
Adjust
Gain
Adjust
Start-Up
Protection
Logic
Short-Circuit
Detect
Thermal VCC OK
Ramp
Generator
Biases
and
References
Gain
2
AGNDVREF
VREF
PV
CC
INN
OUTN
PGND
PV
CC
OUTP
PGND
INP
SHUTDOWN
GAIN1
GAIN0
COSC
ROSC
BYPASS
SD
_
+
_
+
Deglitch
Logic
Deglitch
Logic
V
CC
V
CC
BSP
BSN
Clamp
Reference
VCLAMP
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage: V
Load impedance, R
CC,
PV
CC
L
SHUTDOWN -0.3 V to V
Input voltage GAIN0, GAIN1 -0.3 V to 5.5 V
INN, INP -0.3 V to 7 V
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range, T
Operating junction temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
stg
A
J
DISSIPATION RATING TABLE
PACKAGE TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
PWP 4.16 W 33.33 mW/ ° C
(1) The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD Thermally Enhanced
Package application note (SLMA002).
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(1)
(1)
2.67 W 2.16 W
UNIT
-0.3 V to 21 V
≥ 3.6 Ω
-40 ° C to 85 ° C
-40 ° C to 150 ° C
-65 ° C to 150 ° C
+ 0.3 V
CC
3
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TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Supply voltage, V
Load impedance, R
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T
PV
CC,
CC
L
IH
IL
A
(1) The TPA3001D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 3.6 Ω over the
audio frequency band.
ELECTRICAL CHARACTERISTICS
TA= 25 ° C, PV
|V
| mV
OS
PSRR Power supply rejection ratio PV
|IIH| High-level input current PV
|IIL| Low-level input current PV
I
CC
I
CC(SD)
f
s
r
ds(on)
G Gain
= V
CC
= 12 V (unless otherwise noted)
CC
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
Output offset voltage (measured
differentially)
VI= 0 V, AV= 12 dB, 18, 23.6 dB 50
VI= 0 V, AV= 36 dB 100
SHUTDOWN = 2.0 V, No load 8 15 mA
Supply current
SHUTDOWN = VCC, V
8 Ω
Supply current, shutdown mode SHUTDOWN = 0.8 V 1 2 µ A
Switching frequency R
OSC
Output transistor on resistance (total) IO= 1 A, TJ= 25 ° C 0.2 0.3 0.7 Ω
GAIN1 = 0.8 V, GAIN0 = 0.8 V 10.9 12 12.8 dB
GAIN1 = 0.8 V, GAIN0 = 2 V 17.1 18 18.5 dB
GAIN1 = 2 V, GAIN0 = 0.8 V 23 23.6 24.3 dB
GAIN1 = 2 V, GAIN0 = 2 V 33.9 36 36.5 dB
(1)
RL≥ 3.6
8 18 V
3.6 Ω
GAIN0, GAIN1, SHUTDOWN 2 V
GAIN0, GAIN1, SHUTDOWN 0.8 V
-40 85 ° C
= 11.5 V to 12.5 V -73 dB
CC
= 12 V, VI= PV
CC
= 12 V, VI= 0 V 1 µ A
CC
= 120 k Ω , C
CC
= 18 V, PO= 20 W, RL=
CC
= 220 pF 250 kHz
OSC
1.3 A
1 µ A
OPERATING CHARACTERISTICS
PV
= V
CC
P
O
THD + N Total harmonic distortion plus noise PO= 10 W, RL= 4 Ω , f = 20 Hz to 20 kHz 0.2%
B
OM
k
SVR
SNR Signal-to-noise ratio PO= 10 W, RL= 4 Ω 95 dB
V
n
Z
i
4
= 12 V, TA= 25 ° C (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Continuous output power at 10%
THD+N
Continuous output power at 1%
THD+N
f = 1 kHz, RL= 4 Ω 12.8
f = 1 kHz, RL= 8 Ω 9
f = 1 kHz, RL= 4 Ω 10.3
f = 1 kHz, RL= 8 Ω 7.2
Maximum output power bandwidth THD = 1% 20 kHz
Supply ripple rejection ratio f = 1 kHz, C
C
(BYPASS)
filter used, Gain = 12 dB
Noise output voltage
C
(BYPASS)
filter, Gain = 12 dB
(BYPASS)
= 1 µ F, f = 20 Hz to 22 kHz,No weighting
= 1 µ F, f = 20 Hz to 22 kHz,A-weighted
= 1 µ F -70 dB
86 µ V(rms)
-81 dBV
66 µ V(rms)
-84 dBV
Input impedance See Table 1, page 21 >23 k Ω
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TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
OPERATING CHARACTERISTICS
PV
= V
CC
P
O
THD + N Total harmonic distortion plus noise
B
OM
k
SVR
SNR Signal-to-noise ratio PO= 15 W, RL= 8 Ω 102 dB
V
n
Z
i
= 18 V, TA= 25 ° C (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output power at 10% THD+N
Output power at 1% THD+N
f = 1 kHz, RL= 4 Ω 12.8
f = 1 kHz, RL= 8 Ω 20
f = 1 kHz, RL= 4 Ω 10.3
f = 1 kHz, RL= 8 Ω 16
PO= 15 W, RL= 8 Ω , f = 20 Hz to 20 kHz 1%
PO= 2 W, RL= 8 Ω , f = 20 Hz to 20 kHz 0.3%
Maximum output power bandwidth THD = 1% 20 kHz
Supply ripple rejection ratio f = 1 kHz, C
C
(BYPASS)
filter used, Gain = 12 dB
Noise output voltage
C
(BYPASS)
filter, Gain = 12 dB
= 1 µ F, f = 20 Hz to 20 kHz, No weighting
= 1 µ F, f = 20 Hz to 22 kHz, A-weighted
= 1 µ F -70 dB
BYPASS
86 µ V(rms)
-81 dBV
66 µ V(rms)
84 dBV
Input impedance See Table 1, page 21 >23 k Ω
W
TYPICAL CHARACTERISTICS
Table of Graphs
Efficiency vs Output power 1
P
O
I
CC
I
CC(SD)
THD+N Total harmonic distortion + noise
k
SVR
CMRR Common-mode rejection ratio 28
V
IO
Output power vs Load Impedance 2, 3, 4
Supply current 5
Shutdown current 6
vs Supply voltage
vs Output power
7, 8, 9, 10, 11, 12, 13, 14, 15,
vs Frequency 19, 20, 21, 22, 23, 24, 25
Supply voltage rejection ratio 26
Gain and phase vs Frequency 27
Input offset voltage vs Common-mode input voltage 29
FIGURE
16, 17, 18
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0
10
20
30
40
50
60
70
80
90
0 2 4 6 8 10 12 14
PO − Output Power − W
4 Ω
8 Ω
Efficiency − %
VCC = 12 V
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA = 25°C,
10% THD Maximum
Load Impedance − Ω
− Output Power − WP
O
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
− Maximum Output Power − WP
O
ZL − Load Impedance − Ω
TA = 45°C
5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
− Maximum Output Power − WP
O
ZL − Load Impedance − Ω
TA = 60°C
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
EFFICIENCY MAXIMUM OUPUT POWER
vs vs
OUTPUT POWER LOAD IMPEDANCE
Figure 1. Figure 2.
MAXIMUM OUPUT POWER MAXIMUM OUTPUT POWER
LOAD IMPEDANCE LOAD IMPEDANCE
6
Figure 3. Figure 4.
vs vs
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6
7
8
9
10
11
8 10 12 14 16 18
VCC − Supply Voltage − V
I
CC
− Supply Current − mA
VCC − Supply Voltage − V
0
1
2
3
4
5
8 10 12 14 16 18
I
CC(SD)
− Shutdown Current − µA
SHUTDOWN = 0.8 V
0.001
0.01
0.1
1
10
0 5 10 15 20
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 18 V ,
RL = 8 Ω,
Gain = 12 dB
0.01
0.1
1
10
0 5 10 15 20
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 18 V ,
RL = 8 Ω,
Gain = 36 dB
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
SUPPLY CURRENT SHUTDOWN CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 7. Figure 8.
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0.01
0.1
10
0 5 10 15 20
1
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 15 V ,
RL = 8 Ω,
Gain = 36 dB
0.001
0.01
0.1
10
0 5 10 15 20
1
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 15 V ,
RL = 8 Ω,
Gain = 12 dB
0.01
0.1
10
0 5 10
1
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 15 V ,
RL = 4 Ω,
Gain = 12 dB
0.01
0.1
1
10
0 5 10
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 15 V ,
RL = 4 Ω,
Gain = 36 dB
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 9. Figure 10.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
8
Figure 11. Figure 12.
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0.01
0.1
1
10
0 5 10 15
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 12 V ,
RL = 8 Ω,
Gain = 12 dB
0.001
0.01
0.1
1
0 5 10 15
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 12 V ,
RL = 8 Ω,
Gain = 36 dB
10
0.001
0.01
0.1
1
10
0 5 10
1 kHz
20 Hz
20 kHz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 12 V ,
RL = 4 Ω,
Gain = 12 dB
0.01
0.1
1
10
0 5 10
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 12 V ,
RL = 4 Ω,
Gain = 36 dB
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 13. Figure 14.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 15. Figure 16.
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0.01
0.1
1
10
0 2 4 6
1 kHz
20 Hz
20 kHz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 8 V ,
RL = 4 Ω,
Gain = 12 dB
0.01
0.1
1
10
0 2 4 6
1 kHz
20 kHz
20 Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO − Output Power − W
VCC = 8 V ,
RL = 4 Ω,
Gain = 36 dB
0.001
0.01
0.1
1
20 100 1 k 10 k 20 k
VCC = 18 V
RL = 8 Ω
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO = 500 mW
PO = 2 W
PO = 10 W
PO = 500 mW
0.001
0.01
0.1
1
20 100 1 k 10 k 20 k
VCC = 15 V
RL = 8 Ω
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO = 10 W
PO = 2 W
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 17. Figure 18.
vs vs
FREQUENCY FREQUENCY
10
Figure 19. Figure 20.
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0.001
0.01
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
VCC = 12 V
RL = 8 Ω
PO = 5 W
PO = 250 mW
PO = 1 W
0.001
0.01
0.1
1
20 100 1 k 10 k 20 k
VCC = 15 V
RL = 4 Ω
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
PO = 10 W
PO = 2 W
PO = 500 mW
0.001
0.01
0.1
10
20 100 1 k 10 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
VCC = 8 V
RL = 8 Ω
1
PO = 3 W
PO = 250 mW
PO = 1 W
0.001
0.01
0.1
1
20 100 1 k 10 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
VCC = 12 V
RL = 4 Ω
PO = 2 W
PO = 500 mW
PO = 7.5 W
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY FREQUENCY
Figure 21. Figure 22.
vs vs
FREQUENCY FREQUENCY
Figure 23. Figure 24.
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0.001
0.01
0.1
10
20 100 1 k
10 k
20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion Plus Noise − %
VCC = 8 V
RL = 4 Ω
1
PO = 5 W
PO = 1 W
PO = 250 mW
−90
−80
−70
−60
−50
f − Frequency − Hz
VDD = 15 V
k
SVR
− Supply Voltage Rejection Ratio − dB
20 100 1k 10k
C
(Bypass)
= 1 µF
RL = 8 Ω
VCC = 8 V
−40
−41
−42
−43
−44
−45
−46
f − Frequency − Hz
CMRR − Common-Mode Rejection Ratio − dB
VCC = 8 V to 18 V
RL = 8 Ω
20 100 1 k 10 k
f − Frequency − Hz
Phase
Gain
20 100 1k 10k 100k
VCC = 8 V
RL = 8 Ω
Gain = 12 dB
8
6
2
0
Gain − dB
10
12
14
4
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
Phase −
°
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
TOTAL HARMONIC DISTORTION PLUS NOISE SUPPLY VOLTAGE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 25. Figure 26.
GAIN AND PHASE COMMON-MODE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
12
Figure 27. Figure 28.
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VIC − Common-Mode Input Voltage − V
−4
−3
−2
−1
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VCC = 8 V to 18 V
V
IO
− Input Offset Voltage − mV
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
INPUT OFFSET VOLTAGE
COMMON-MODE INPUT VOLTAGE
vs
Figure 29.
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INN
INP
GAIN0
SHUTDOWN
PGND
VCLAMP
BSN
PV
CC
OUTN
OUTN
PGND
V
CC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PV
CC
OUTP
GAIN1
OUTP
PGND
PowerPAD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
R3
51 Ω
C9
0.22 µF
C6
1 µF
D1
V
CC
C12
220 pF
C11
1 µF
C3
1 µF
C4
1 µF
V
CC
L2
(Ferrite
Bead)
L1
(Ferrite
Bead)
C15
1 nF
C14
1 nF
D2
R2
51 Ω
C8
0.22 µF
C5
1 µF
C7
10 µF
C10
1 µF
C1
0.47 µF
C2 0.47 µF
IN–
IN+
GAIN SELECT
GAIN SELECT
SHUTDOWN
CONTROL
U1
TPA3001D1
L1, L2: Fair-Rite, Part Number 2512067007Y3
D1, D2: Diodes, Inc., Part Number B130
V
CC
R1
120 kΩ
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION CIRCUIT
APPLICATION INFORMATION
Figure 30. Typical Application Circuit
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3001D1.
TRADITIONAL CLASS-D MODULATION SCHEME
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, V
the differential prefiltered output varies between positive and negative V
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 31 . Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
14
, where filtered 50% duty cycle yields
CC
. Therefore,
CC
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0 V
–12 V
+12 V
Current
OUTP
Differential Voltage
Across Load
OUTN
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
Figure 31. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3001D1 MODULATION SCHEME
The TPA3001D1 uses a modulation scheme that still has each output switching from ground to V
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is
greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See
Figure 32 on the following page.)
. However,
CC
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0 V
–12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
0 V
–12 V
+12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
Output > 0 V
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
Figure 32. The TPA3001D1 Output Voltage and Current Waveforms Into an Inductive Load
MAXIMUM ALLOWABLE OUTPUT POWER (SAFE OPERATING AREA)
The TPA3001D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to
18 V. To prevent device failure, however, the output power of the TPA3001D1 must be limited. Figure 33 shows
the maximum allowable output power versus load impedance for three power supply voltages at an ambient
temperature of 25 ° C. (For ambient temperatures of 45 ° C and 60 ° C, see Figures 3 and 4 on page 6.)
16
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5
7
9
11
13
15
17
19
21
3.6 4 5 6 7 8 9 10
VCC = 18 V
VCC = 15 V
VCC = 12 V
TA = 25°C,
10% THD Maximum
Load Impedance – Ω
– Output Power – W
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
P
O
V
in(pp),max
+
8P
O(avg),max
R
L
Ǹ
A
v
where
P
O(avg), max
= maximum continuous output power (W)
RL = load impedance (Ω)
Av+ voltage gain (VńV) +
ǒ
G(dB)
20
Ǔ
APPLICATION INFORMATION (continued)
Figure 33. Output Power
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
driving a low-impedance load from a high power supply voltage
When driving low-impedance loads (e.g., a 4- Ω speaker), the output power can be limited by reducing the
maximum audio input signal level or by reducing the gain of the TPA3001D1. The maximum input voltage may
be calculated with Equation 1 .
For example, consider an application in which the TPA3001D1 drives a 4- Ω speaker from an 18-V power supply.
The gain is selected to be 18 dB. The maximum allowable output power for a 4- Ω load impedance is 12.8 W.
From Equation 1 , the input voltage must not exceed 2.54 V
In this same example, however, if the maximum output voltage of audio signal source is 5 V
the TPA3001D1 should be reduced to 12 dB to eliminate the need for limiting the input signal.
The input voltage may be limited using a variety of methods, depending on what is known about the audio signal
source. If the maximum output voltage of the source is known, a resistive voltage divider in conjunction with
proper TPA3001D1 gain selection may be used to prevent distortion. If the maximum audio source voltage is
unknown, diodes may be used to clamp the input voltage, at the cost of distortion when the input signal level
exceeds the required clamping voltage.
DRIVING THE OUTPUT INTO CLIPPING
The output of the TPA3001D1 may be driven into clipping to attain a higher output power than is possible with
no distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power
into the load may be calculated with Equation 2 .
(1)
.
pp
, then the gain of
pp
17
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P
O(10% THD)
+ P
O(1% THD)
1.25
1 nF
Ferrite
Chip Bead
OUTP
OUTN
Ferrite
Chip Bead
1 nF
4 Ω or Greater
1 µF
15 µH
15 µH
OUTP
OUTN
4 Ω
Ferrite
Chip Bead
Ferrite
Chip Bead
0.22 mF
1 nF
0.22 mF
1 nF
0.47 µF
33 µH
33 µH
OUTP
OUTN
8 Ω
Ferrite
Chip Bead
Ferrite
Chip Bead
0.1 mF
1 nF0.1 mF
1 nF
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
For example, consider an application in which the TPA3001D1 drives an 8- Ω speaker from an 18-V power
supply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to a
maximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), the
output power is increased to 20 W.
OUTPUT FILTER CONSIDERATIONS
A ferrite bead filter (shown in Figure 34 ) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long
wires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 35 and Figure 36 .
(2)
Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
Figure 35. Typical LC Output Filter for 4- Ω Speaker, Cutoff Frequency of 27 kHz
18
Figure 36. Typical LC Output Filter for 8- Ω Speaker, Cutoff Frequency of 27 kHz
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T
Amax
+ T
Jmax
* Q
JAPDissipated
P
Dissipated
+ P
O(average)
((1ńEfficiency) * 1)
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
SHORT-CIRCUIT PROTECTION
The TPA3001D1 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-V
outputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched fault
and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state
for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed.
If the short was not removed, the protection circuitry will again activate.
Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to the
TPA3001D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTN
as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5 V at a
minimum of 1-A output current and a DC blocking voltage rating of at least 30 V. The diodes must also be rated
to operate at a junction temperature of 150 ° C.
If short-circuit protection is not required, the Schottky diodes may be omitted.
THERMAL PROTECTION
Thermal protection on the TPA3001D1 prevents damage to the device when the internal die temperature
exceeds 150 ° C. There is a ± 15 ° C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is
not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15 ° C. The device
begins normal operation at this point with no external system interaction.
shorts. When a short-circuit is detected on the
CC
THERMAL CONSIDERATION: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE
To calculate the maximum ambient temperature, Equation 3 may be used:
where: T
θ
= 1 / derating factor = 1 / 0.03333 = 30 ° C/W
JA
= 150 ° C
Jmax
(The derating factor for the 24-pin PWP package is given in the dissipation rating table on page 3.)
To estimate the power dissipation, Equation 4 may be used:
Efficiency = ~85% for an 8- Ω load
= ~75% for a 4- Ω load
Example. What is the maximum ambient temperature for an application that requires the TPA3001D1 to drive 10
W into an 8- Ω speaker?
P
Dissipated
T
Amax
= 10 W x ((1 / 0.85) - 1) = 1.76 W
= 150 ° C - (30 ° C/W x 1.76 W) = 97.2 ° C
This calculation shows that the TPA3001D1 can drive 10 W into an 8- Ω speaker up to the absolute maximum
ambient temperature rating of 85 ° C, which must never be exceeded. Also, refer to Figures 2, 3, and 4 to
determine the minimum load impedance for the desired output power.
GAIN SETTING VIA GAIN0 AND GAIN1 INPUTS
The gain of the TPA3001D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Z
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift by
30% due to shifts in the actual resistance of the input resistors.
) to be dependent on the gain setting. The actual gain settings are controlled by
i
(3)
(4)
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19
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C
i
IN
Z
i
Z
f
Input
Signal
f +
1
2p Z
iCi
f
c
+
1
2p ZiC
i
−3 dB
f
c
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 23 k Ω , which is the absolute minimum input impedance of the TPA3001D1. At the lower gain
settings, the input impedance could increase as high as 313 k Ω .
Table 1. Gain Settings
AMPLIFIER GAIN INPUT IMPEDANCE
GAIN1 GAIN0
0 0 12 241
0 1 18 168
1 0 23.6 104
1 1 36 33
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3dB
or cutoff frequency also changes by over six times.
(dB) (k Ω )
TYP TYP
The -3-dB frequency can be calculated using Equation 5 . Use Table 1 for Zivalues.
INPUT CAPACITOR, C
In the typical application an input capacitor (C
proper dc level for optimum operation. In this case, C
i
) is required to allow the amplifier to bias the input signal to the
i
and the input impedance of the amplifier (Zi) form a
i
high-pass filter with the corner frequency determined in Equation 6 .
The value of C
is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
i
the example where Ziis 241 k Ω and the specification calls for a flat bass response down to 20 Hz. Equation 6 is
reconfigured as Equation 7 .
(5)
(6)
20
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C
i
+
1
2p Z
i
f
c
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
In this example, Ciis 33 nF, so one would likely choose a value of 0.1 µ F as this value is commonly used. If the
gain is known and will be constant, use Zifrom Table 1 to calculate Ci. A further consideration for this capacitor
is the leakage path from the input source through the input network (C
This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that
it is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING
The TPA3001D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 1 µ F placed as close as possible to the device V
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µ F or greater placed near
the audio power amplifier is recommended.
) and the feedback network to the load.
i
lead works best. For
CC
(7)
BSN AND BSP CAPACITORS
The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the high
side of each output to turn on correctly. A 0.22- µ F ceramic capacitor, rated for at least 25 V, must be connected
from each output to its corresponding bootstrap input. Specifically, one 0.22- µ F capacitor must be connected
from OUTP to BSP, and one 0.22- µ F capacitor must be connected from OUTN to BSN. (See Figure 30 .)
BSN AND BSP RESISTORS
To limit the current when charging the bootstrap capacitors, a resistor with a value of approximately 50 Ω ( ± 10%
maximum) must be placed in series with each bootstrap capacitor. The current will be limited to less than 500
µ A.
VCLAMP CAPACITOR
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an
internal regulator clamps the gate voltage. A 1- µ F capacitor must be connected from VCLAMP (pin 7) to ground
and must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with V
and may not be used for
CC
powering any other circuitry.
MIDRAIL BYPASS CAPACITOR
The midrail bypass capacitor (C11 of Figure 30 ) is the most critical capacitor and serves several important
functions. During start-up or recovery from shutdown mode, C
BYPASS
starts up. The second function is to reduce noise produced by the power supply caused by coupling into the
output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as
degraded PSRR and THD+N.
Bypass capacitor (C11) values of 0.47- µ F to 1- µ F ceramic or tantalum low-ESR capacitors are recommended for
the best THD noise, and depop performance. The bypass capacitor must be a value greater than the input
capacitors for optimum depop performance.
determines the rate at which the amplifier
VREF DECOUPLING CAPACITOR
The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and gain
setting logic. It requires a 0.1- µ F to 1- µ F capacitor to ground to keep the regulator stable. The regulator may not
be used to power any additional circuitry.
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21
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f
s
+
6.6
R
OSCCOSC
t
startup
+ 8.2 ms ) 2 100 kW C
11
TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
DIFFERENTIAL INPUT
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3001D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3001D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio signal to the INP input. In a
single-ended input application, the INN input should be ac-grounded at the audio source instead of at the device
input for best noise performance.
SWITCHING FREQUENCY
The switching frequency is determined using the values of the components connected to R
(pin 21) and may be calculated with Equation 8 :
The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for R
SHUTDOWN OPERATION
The TPA3001D1 employs a shutdown mode of operation designed to reduce supply current (I
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs
to mute and the amplifier to enter a low-current state, I
CC(SD)
unconnected, because amplifier operation would be unpredictable.
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected
directly to V
.
CC
= 1 µ A. SHUTDOWN should never be left
(pin 20) and C
OSC
OSC
CC
and C
) to the absolute
.
OSC
OSC
(8)
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
STARTUP TIME
The startup time can be calculated with Equation 9 :
where C
is the value of the bypass capacitor as shown in Figure 30 .
11
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3001D1 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors — As described on page 22, the high-frequency 0.1-uF decoupling capacitors should
be placed as close to the PVCC (pin 9 and pin 16) and VCC (pin 24) terminals as possible. The BYPASS
(pin 22) capacitor, VREF (pin 23) capacitor, and VCLAMP (pin 7) capacitor should also be placed as close
to the device as possible. The large (10 µ F or greater) bulk power supply decoupling capacitor should be
placed near the TPA3001D1.
• Grounding — The VCC (pin 24) decoupling capacitor, VREF (pin 23) capacitor, BYPASS (pin 22) capacitor,
COSC (pin 21) capacitor, and ROSC (pin 20) resistor should each be grounded to analog ground (AGND,
pin 18 and pin 19). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power
ground (PGND, pin 12 and pin 13). Analog ground and power ground may be connected at the PowerPAD,
which should be used as a central ground connection or star ground for the TPA3001D1.
(9)
22
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TPA3001D1
SLOS398C – DECEMBER 2002 – REVISED JULY 2006
• Output filter — The ferrite filter (Figure 34, page 18) should be placed as close to the output terminals (pins
10, 11, 14, and 15) as possible for the best EMI performance. The LC filter (Figure 35, page 18 and Figure
36, page 19) should be placed close to the ferrite filter. The capacitors used in both the ferrite and LC filters
should be grounded to power ground.
• PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 1.6 mm by 6.0 mm (63 mils by 236.2
mils). Two rows of solid vias (four vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced
underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or
on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For additional
information, please refer to the PowerPAD Thermally Enhanced Package application note, TI literature
number SLMA002.
For an example layout, refer to the TPA3001D1 Evaluation Module (TPA3001D1EVM) User Manual, TI literature
number SLOU156. Both the EVM user manual and the PowerPAD application note are available on the TI web
site at http://www.ti.com.
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23
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TPA3001D1PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br)
TPA3001D1PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br)
TPA3001D1PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br)
TPA3001D1PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
Type
TPA3001D1PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3001D1PWPR HTSSOP PWP 24 2000 346.0 346.0 33.0
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
RF/IF and ZigBee® Solutions www.ti.com/lprf Video & Imaging www.ti.com/video
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
Wireless www.ti.com/wireless
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