TEXAS INSTRUMENTS TPA2028D1 Technical data

IN-

IN+

PGND

OUT+

OUT-

ToBattery

SDA

SCL

MasterEnable

TPA2028D1

Digital

BaseBand

Analog

Baseband

CODEC

PVDD

10 Fm

C 1 F

(Optional)

I CClock

I CData

TPA2028D1

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SLOS660 –JANUARY 2010

3-W Mono Class-D Audio Amplifier with Fast Gain Ramp SmartGain™ AGC/DRC

Check for Samples: TPA2028D1

FEATURES

• Fast AGC Start-up Time: 5 ms

• Pin-out Compatible with TPA2018D1

• Filter-Free Class-D Architecture

• 3 W Into 4 Ω at 5 V (10% THD+N)

• 880 mW Into 8 Ω at 3.6 V (10% THD+N)

• Power Supply Range: 2.5 V to 5.5 V

• Flexible Operation With/Without I2C™

• Programmable DRC/AGC Parameters

• Digital I2C™ Volume Control

• Selectable Gain from –28 dB to 30 dB in 1-dB speaker from damage at high power levels and

Steps (when compression is used)

• Selectable Attack, Release and Hold Times

• 4 Selectable Compression Ratios

• Low Supply Current: 1.8 mA

• Low Shutdown Current: 0.2 mA

• High PSRR: 80 dB

• AGC Enable/Disable Function

• Limiter Enable/Disable Function

• Short-Circuit and Thermal Protection

• Space-Saving Package – 1,63 mm × 1,63 mm Nano-Free™ WCSP

(YZF)

DESCRIPTION

The TPA2028D1 is a mono, filter-free Class-D audio power amplifier with volume control, dynamic range compression (DRC) and automatic gain control (AGC). It is available in a 1,63 mm x 1,63 mm wafer chip-scale package (WCSP).

The DRC/AGC function in the TPA2028D1 is programmable via a digital I2C interface. The DRC/AGC function can be configured to automatically prevent distortion of the audio signal and enhance quiet passages that are normally not heard. The DRC/AGC can also be configured to protect the

compress the dynamic range of music to fit within the dynamic range of the speaker. The gain can be selected from –28 dB to +30 dB in 1-dB steps. The TPA2028D1 is capable of driving 3 W at 5 V into 4 Ω load or 880 mW at 3.6 V into 8 Ω load. The device features hardware and software shutdown controls and also provides thermal and short-circuit protection. The TPA2028D1 has faster AGC gain ramp during start-up than TPA2018D1.

In addition to these features, a fast start-up time and small package size make the TPA2028D1 an ideal choice for cellular handsets, PDAs and other portable applications.

SIMPLIFIED APPLICATION DIAGRAM

APPLICATIONS

• Wireless or Cellular Handsets and PDAs

• Portable Navigation Devices

• Portable DVD Player

• Notebook PCs

• Portable Radio

• Portable Games

• Educational Toys

• USB Speakers

2Fast Gain Ramp SmartGain, Nano-Free are trademarks of Texas Instruments.

C is a trademark of NXP Semiconductors.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OUT +

OUT -

PGND

PVDD

IN +

IN -

SDA

SCL

Volume Control

1 Fm

ICEnable

Power

Stage

AGC

Reference

Biasand

References

AGC

I CInterface

Differential

Input

I CInterface

andControl

Class-D

Modulator

IN-

PGND

ENOUT+

PVDDOUT-

SCL

IN+

SDA

C1 C2 C3

B1 B3B2

A1 A 2 A3

YZF(WCSP)PACKAGE

(TOP VIEW)

TPA2028D1

SLOS660 –JANUARY 2010

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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FUNCTIONAL BLOCK DIAGRAM

DEVICE PINOUT

Product Folder Link(s): TPA2028D1

TPA2028D1

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SLOS660 –JANUARY 2010

TERMINAL FUNCTIONS

TERMINAL I/O/P DESCRIPTION

NAME WCSP

EN B2 I Enable terminal (active high) IN+ B3 I Positive audio input IN– C3 I Negative audio input OUT+ B1 O Positive differential output OUT– C1 O Negative differential output PGND A1 P Power ground PVDD C2 P Power supply SCL A2 I I2C clock interface SDA A3 I/O I2C data interface

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted).

T T T ESD Electro-Static Discharge Tolerance, all pins Human Body Model (HBM) 2 kV

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

Supply voltage PVDD –0.3 V to 6.0 V

Input voltage

Continuous total power dissipation Operating free-air temperature range –40°C to +85°C

Operating junction temperature range –40°C to +150°C

Storage temperature range –65°C to +150°C

stg

Minimum load resistance 3.2 Ω

LOAD

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

VALUE / UNIT

EN, IN+, IN– –0.3 V to VDD+0.3 V SDA, SCL –0.3 V to 6.0 V

See Dissipation Ratings

Table

Charged Device Model (CDM) 500 V

DISSIPATION RATINGS TABLE

PACKAGE TA≤ +25°C DERATING FACTOR TA= +70°C TA= +85°C

9-ball WCSP 1.19 W 9.52 mW/°C 0.76 W 0.62 W

(1) Dissipation ratings are for a 2-side, 2-plane PCB.

Product Folder Link(s): TPA2028D1

(1)

TPA2028D1

SLOS660 –JANUARY 2010

AVAILABLE OPTIONS

PACKAGED DEVICES

–40°C to 85°C 9-ball, WCSP NSU

(2)

(1)

PART NUMBER SYMBOL

TPA2028D1YZFR TPA2028D1YZFT

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(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com

(2) The YZF packages are only available taped and reeled. The suffix R indicates a reel of 3000; the suffix T indicates a reel of 250.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Supply voltage PVDD 2.5 5.5 V

High-level input voltage EN, SDA, SCL 1.3 V

Low-level input voltage EN, SDA, SCL 0.6 V

Operating free-air temperature –40 +85 °C

ELECTRICAL CHARACTERISTICS

at TA= 25°C, VDD= 3.6 V, SDZ = 1.3 V, and RL= 8 Ω + 33 mH (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SDZ

SWS

START

POR Power on reset ON threshold 2 2.3 V POR Power on reset hysteresis 0.2 V

CMRR Input common mode rejection –75 dB

OUT

PSRR Power supply rejection ratio VDD= 2.5 V to 4.7 V –80 dB

Supply voltage range 2.5 3.6 5.5 V

EN = 0.35 V, VDD= 2.5 V 0.1 1

Shutdown quiescent current EN = 0.35 V, VDD= 3.6 V 0.2 1 µA

EN = 0.35 V, VDD= 5.5 V 0.3 1

EN = 1.3 V, VDD= 2.5 V 35 50 Software shutdown quiescent current

EN = 1.3 V, VDD= 3.6 V 50 70 µA

EN = 1.3 V, VDD= 5.5 V 75 100

VDD= 2.5 V 1.5 2.5 Supply current VDD= 3.6 V 1.7 2.7 mA

VDD= 5.5 V 2 3.5 Class D Switching Frequency 275 300 325 kHz High-level input current VDD= 5.5 V, EN = 5.8 V 1 µA Low-level input current VDD= 5.5 V, EN = –0.3 V –1 µA Start-up time 2.5 V ≤ VDD≤ 5.5 V no pop, CIN≤ 1 mF 5 ms

RL= 8 Ω, V

differential inputs shorted Output offset voltage 1.5 10 mV Output Impedance in shutdown 2 kΩ

mode

VDD= 3.6 V, AV= 6 dB, RL= 8 Ω, inputs ac

grounded

EN = 0.35 V

= 0.5 V and V

icm

= VDD– 0.8 V,

icm

Gain accuracy Compression and limiter disabled, Gain = 0 to 30 dB –0.5 0.5 dB

Product Folder Link(s): TPA2028D1

TPA2028D1

IN+

IN–

OUT+

OUT–

GND

Measurement

Output

–

Load

30kHz

Low-Pass

Filter

Measurement

Input

–

1 Fm

TPA2028D1

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SLOS660 –JANUARY 2010

OPERATING CHARACTERISTICS

at TA= 25°C, VDD= 3.6V, EN = 1.3 V, RL= 8 Ω +33 mH, and AV= 6 dB (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVR

THD+N Total harmonic distortion + noise

Nfo Nfo FR Frequency response Av = 6 dB 20 20000 Hz

h Efficiency

power-supply ripple rejection ratio VDD= 3.6 Vdc with ac of 200 mVPPat 217 Hz –70 dB

= 1 kHz; PO= 550 mW; VDD= 3.6 V 0.1%

aud_in

= 1 kHz; PO= 1.25 W; VDD= 5 V 0.1%

aud_in

= 1 kHz; PO= 710 mW; VDD= 3.6 V 1%

aud_in

= 1 kHz; PO= 1.4 W; VDD= 5 V 1%

aud_in

Output integrated noise Av = 6 dB 42 mV

Output integrated noise Av = 6 dB floor, A-weighted 30 mV

THD+N = 10%, VDD= 5 V, RL= 8 Ω 1.72 W THD+N = 10%, VDD= 3.6 V, RL= 8 Ω 880 mW

Maximum output power

max

THD+N = 1%, VDD= 5 V, RL= 8 Ω 1.4 W THD+N = 1% , VDD= 3.6 V, RL= 8 Ω 710 mW THD+N = 1% , VDD= 5 V, RL= 4 Ω 2.5 W THD+N = 10% , VDD= 5 V, RL= 4 Ω 3 W THD+N = 1%, VDD= 3.6 V, RL= 8 Ω, PO= 0.71 W 91% THD+N = 1%, VDD= 5 V, RL= 8 Ω, PO= 1.4 W 93%

TEST SET-UP FOR GRAPHS

(1) All measurements were taken with a 1-mF CI(unless otherwise noted.) (2) A 33-mH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (1 kΩ

4.7 nF) is used on each output for the data sheet graphs.

Product Folder Link(s): TPA2028D1

SCL

SDA

w(H)

w(L)

su1

SCL

SDA

(buf)

su2

su3

StartCondition

StopCondition

TPA2028D1

SLOS660 –JANUARY 2010

I2C TIMING CHARACTERISTICS

For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SCL

W(H)

W(L)

SU(1)

(buf)

SU2

SU3

Frequency, SCL No wait states 400 kHz Pulse duration, SCL high 0.6 ms Pulse duration, SCL low 1.3 ms Setup time, SDA to SCL 100 ns Hold time, SCL to SDA 10 ns Bus free time between stop and start 1.3 ms

condition Setup time, SCL to start condition 0.6 ms Hold time, start condition to SCL 0.6 ms Setup time, SCL to stop condition 0.6 ms

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Figure 1. SCL and SDA Timing

Figure 2. Start and Stop Conditions Timing

Product Folder Link(s): TPA2028D1

TPA2028D1

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SLOS660 –JANUARY 2010

TYPICAL CHARACTERISTICS

with C

(DECOUPLE)

All THD + N graphs are taken with outputs out of phase (unless otherwise noted).

= 1 mF, CI= 1 µF.

Table of Graphs

FIGURE

Quiescent supply current vs Supply voltage Figure 3 Supply current vs Supply voltage in shutdown Figure 4

vs Input level with limiter enabled Figure 5 vs Input level with 2:1 compression Figure 6

Output level vs Input level with 4:1 compression Figure 7

vs Input level with 8:1 compression Figure 8 vs Input level Figure 9

Supply ripple rejection ratio vs Frequency Figure 10

vs Frequency [RL= 8 Ω, VDD= 3.6 V] Figure 11

Total harmonic distortion + noise

Efficiency

Power dissipation

Supply current

Output power

Shutdown gain ramp comparison, TPA2028D1 vs TPA2018D1 Figure 25 Startup gain ramp comparison, TPA2028D1 vs TPA2018D1 Figure 26 Startup time Figure 27

vs Frequency [RL= 4 Ω, VDD= 3.6 V] Figure 12 vs Frequency [RL= 8 Ω, VDD= 5 V] Figure 13 vs Frequency [RL= 4 Ω, VDD= 5 V] Figure 14 vs Output power [RL= 8 Ω] Figure 15 vs Output power [RL= 4 Ω] Figure 16 vs Output power [per channel, RL= 8 Ω] Figure 17 vs Output power [per channel, RL= 4 Ω] Figure 18 vs Output power [RL= 8 Ω] Figure 19 vs Output power [RL= 4 Ω] Figure 20 vs Output power [RL= 8 Ω] Figure 21 vs Output power [RL= 4 Ω] Figure 22 vs Supply voltage [RL= 8 Ω] Figure 23 vs Supply voltage [RL= 4 Ω] Figure 24

Product Folder Link(s): TPA2028D1

VDD − Supply Voltage − V

2.5 3.0 3.5 4.0 4.5 5.0 5.5

− Quiescent Supply Current − mA

G001

RL = 8 Ω + 33 µH EN = V

VDD − Supply Voltage − V

100

2.5 3.0 3.5 4.0 4.5 5.0 5.5

− Supply Current − µA

G002

En = 0 V

SWS = 1

RL = 8 Ω + 33 µH

Input Level − dBV

−50

−40

−30

−20

−10

−40 −30 −20 −10 0 10

Output Level − dBV

G003

RL = 8 Ω + 33 µH VDD = 5 V Fixed Gain = Max Gain = 30 dB Compression Ratio = 1:1

Limiter Level = −6.5 Limiter Level = −4.5 Limiter Level = −2.5 Limiter Level = −0.5 Limiter Level = 1.5 Limiter Level = 3.5 Limiter Level = 5.5 Limiter Level = 7.5 Limiter Level = 9

Input Level − dBV

−50

−40

−30

−20

−10

−70 −50 −30 −10 10

Output Level − dBV

G004

Limiter Level = 9 dBV RL = 8 Ω + 33 µH VDD = 5 V Max Gain = 30 dB

Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3 Fixed Gain = 6 Fixed Gain = 9 Fixed Gain = 12

Input Level − dBV

−50

−40

−30

−20

−10

−70 −50 −30 −10 10

Output Level − dBV

G005

Limiter Level = 9 dBV RL = 8 Ω + 33 µH VDD = 5 V Max Gain = 30 dB

Fixed Gain = −15 Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3 Fixed Gain = 6

Fixed Gain = −27 Fixed Gain = −24 Fixed Gain = −21 Fixed Gain = −18

Input Level − dBV

−50

−40

−30

−20

−10

−70 −50 −30 −10 10

Output Level − dBV

G006

Limiter Level = 9 dBV RL = 8 Ω + 33 µH VDD = 5 V Max Gain = 30 dB

Fixed Gain = −12 Fixed Gain = −9 Fixed Gain = −6 Fixed Gain = −3 Fixed Gain = 0 Fixed Gain = 3

Fixed Gain = −27 Fixed Gain = −24 Fixed Gain = −21 Fixed Gain = −18 Fixed Gain = −15

TPA2028D1

SLOS660 –JANUARY 2010

QUIESCENT SUPPLY CURRENT SUPPLY CURRENT

INPUT LEVEL WITH LIMITER ENABLED INPUT LEVEL WITH 2:1 COMPRESSION

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vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE IN SHUTDOWN

Figure 3. Figure 4.

OUTPUT LEVEL OUTPUT LEVEL

vs vs

Figure 5. Figure 6.

OUTPUT LEVEL OUTPUT LEVEL

INPUT LEVEL WITH 4:1 COMPRESSION INPUT LEVEL WITH 8:1 COMPRESSION

Figure 7. Figure 8.

vs vs

Product Folder Link(s): TPA2028D1

Input Level − dBV

−50

−40

−30

−20

−10

−70 −50 −30 −10 10

Output Level − dBV

G007

Compression Ratio = 1:1 Compression Ratio = 2:1 Compression Ratio = 4:1 Compression Ratio = 8:1

Limiter Level = 9 dBV RL = 8 Ω + 33 µH VDD = 5 V Fixed Gain = 0 dB Max Gain = 30 dB

−80

−70

−60

−50

−40

−30

−20

−10

f − Frequency − Hz

SVR

− Supply Ripple Rejection Ratio − dB

G014

Gain = 6 dB RL = 8 Ω + 33 µH

20 100 1k 20k10k

VDD = 2.5 V

VDD = 5 V

VDD = 3.6 V

f − Frequency − Hz

THD+N − T otal Harmonic Distortion + Noise − %

20 100 1k 20k

0.1

0.01

0.001

G008

Gain = 6 dB RL = 8 Ω + 33 µH VDD = 3.6 V

10k

PO = 0.05 W

PO = 0.5 W

PO = 0.25 W

f − Frequency − Hz

THD+N − T otal Harmonic Distortion + Noise − %

20 100 1k 20k

0.1

0.01

0.001

G010

Gain = 6 dB RL = 4 Ω + 33 µH VDD = 3.6 V

10k

PO = 0.1 W

PO = 1 W

PO = 0.5 W

f − Frequency − Hz

THD+N − T otal Harmonic Distortion + Noise − %

20 100 1k 20k

0.1

0.01

0.001

G009

Gain = 6 dB RL = 8 Ω + 33 µH VDD = 5 V

10k

PO = 0.5 W

PO = 0.1 W

PO = 1 W

f − Frequency − Hz

THD+N − T otal Harmonic Distortion + Noise − %

20 100 1k 20k

0.1

0.01

0.001

G011

Gain = 6 dB RL = 4 Ω + 33 µH VDD = 5 V

10k

PO = 0.2 W

PO = 1 W

PO = 2 W

TPA2028D1

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SLOS660 –JANUARY 2010

OUTPUT LEVEL SUPPLY RIPPLE REJECTION RATIO

vs vs

INPUT LEVEL FREQUENCY

Figure 9. Figure 10.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 11. Figure 12.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY FREQUENCY

Figure 13. Figure 14.

vs vs

Product Folder Link(s): TPA2028D1

PO − Output Power − W

THD+N − T otal Harmonic Distortion + Noise − %

0.01 0.1 1 3

100

0.1

0.01

G012

Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz

VDD = 3.6 V

VDD = 5 V

PO − Output Power − W

THD+N − T otal Harmonic Distortion + Noise − %

0.01 0.1 1 5

100

0.1

0.01

G013

Gain = 6 dB RL = 4 Ω + 33 µH f = 1 kHz

VDD = 3.6 V

VDD = 5 V

PO − Output Power − W

100

0.0 0.5 1.0 1.5 2.0

η − Efficiency − %

G015

Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz

VDD = 2.5 V

VDD = 3.6 V

VDD = 5 V

PO − Output Power − W

100

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

η − Efficiency − %

G018

Gain = 6 dB RL = 4 Ω + 33 µH f = 1 kHz

VDD = 2.5 V

VDD = 3.6 V

VDD = 5 V

PO − Output Power − W

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.0 0.5 1.0 1.5 2.0

− Power Dissipation − W

G016

Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz

VDD = 5 V

VDD = 3.6 V

VDD = 2.5 V

PO − Output Power − W

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

− Power Dissipation − W

G019

Gain = 6 dB RL = 4 Ω + 33 µH f = 1 kHz

VDD = 5 V

VDD = 3.6 V

VDD = 2.5 V

TPA2028D1

SLOS660 –JANUARY 2010

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

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vs vs

OUTPUT POWER OUTPUT POWER

Figure 15. Figure 16.

EFFICIENCY EFFICIENCY

vs vs

OUTPUT POWER OUTPUT POWER

Figure 17. Figure 18.

POWER DISSIPATION POWER DISSIPATION

OUTPUT POWER OUTPUT POWER

Figure 19. Figure 20.

vs vs

Product Folder Link(s): TPA2028D1

PO − Output Power − W

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.0 0.5 1.0 1.5 2.0

− Supply Current − A

G017

Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz

VDD = 3.6 V

VDD = 2.5 V

VDD = 5 V

PO − Output Power − W

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

− Supply Current − A

G020

VDD = 3.6 V

VDD = 2.5 V

VDD = 5 V

Gain = 6 dB RL = 4 Ω + 33 µH f = 1 kHz

VDD − Supply Voltage − V

0.0

0.5

1.0

1.5

2.0

2.5

2.5 3.0 3.5 4.0 4.5 5.0 5.5

− Output Power − W

G021

Gain = 6 dB RL = 8 Ω + 33 µH f = 1 kHz

THD = 1%

THD = 10%

VDD − Supply Voltage − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

− Output Power − W

G022

Gain = 6 dB RL = 4 Ω + 33 µH f = 1 kHz

THD = 1%

THD = 10%

t − Time − s

V − Voltage − V

0 5m 10m 15m 20m

−4

−2

TPA2028D1 OUTP−OUTM TPA2018D1 OUTP−OUTM SCL − Speaker Enable

VDD = 5.0 V Fixed Gain = 6 dB, CR = 1:1 VIN = 707 mV

RMS

@ 1kHz

RL = 8 Ω + 33 µH

t − Time − s

V − Voltage − V

0 1 2 3 4 5

−4

−2

TPA2028D1 OUTP−OUTM TPA2018D1 OUTP−OUTM SCL − Speaker Enable

VDD = 5.0 V Fixed Gain = 6 dB, CR = 1:1 VIN = 707 mV

RMS

@ 1kHz

RL = 8 Ω + 33 µH

TPA2028D1

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SLOS660 –JANUARY 2010

SUPPLY CURRENT SUPPLY CURRENT

vs vs

OUTPUT POWER OUTPUT POWER

Figure 21. Figure 22.

OUTPUT POWER OUTPUT POWER

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 23. Figure 24.

TPA2028D1 TPA2028D1 TPA2018D1 TPA2018D1

Figure 25. Shutdown Gain Ramp Comparison Figure 26. Startup Gain Ramp Comparison

vs vs

Product Folder Link(s): TPA2028D1

0.5

0.75

0.25

-0.25

-0.5

-0.75

-1 0 2m1m 3m 4m 5m 6m 8m7m 9m 10m

t – Time – s

V – Voltage

– V

SWSDisable

Output

G024

TPA2028D1

SLOS660 –JANUARY 2010

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Figure 27. Start-Up Time

Product Folder Link(s): TPA2028D1

+ 25 hidden pages

TEXAS INSTRUMENTS TPA2028D1 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

SIMPLIFIED APPLICATION DIAGRAM

APPLICATIONS

DEVICE PINOUT

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS TABLE

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

I2C TIMING CHARACTERISTICS

TYPICAL CHARACTERISTICS

Table of Graphs