TEXAS INSTRUMENTS TPA2026D2 Technical data

YZH

AVDD

INL–

INL+

AGND

PGND

OUTL+

OUTL–

PVDDR

10 Fm

ToBattery

SDA

INR–

INR+

C 1 FINm

OUTR+

OUTR–

SCL

SDZ

I CClock

2

I CData

2

MasterShutdown

TPA2026D2

Digital

Baseband

Analog

Baseband

or

Codec

PVDDL

TPA2026D2

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SLOS649 –MARCH 2010

3.2-W/Ch Stereo Class-D Audio Amplifier with Fast Gain Ramp SmartGain™ AGC/DRC

Check for Samples: TPA2026D2

1

FEATURES

23

• Fast AGC Start-up Time: 5 ms

• Pin-Out Compatible with TPA2016D2

• Filter-Free Class-D Architecture

• 3.2 W/Ch Into 4 Ω at 5 V (10% THD+N)

• 750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N)

• Power Supply Range: 2.5 V to 5.5 V

• Flexible Operation With/Without I2C

• Programmable DRC/AGC Parameters

• Digital I2C Volume Control

• Selectable Gain from 0 dB to 30 dB in 1-dB speaker from damage at high power levels and

Steps

• Selectable Attack, Release and Hold Times

• 4 Selectable Compression Ratios

• Low Supply Current: 3.5 mA

• Low Shutdown Current: 0.2 mA

• High PSRR: 80 dB

• AGC Enable/Disable Function

• Limiter Enable/Disable Function

• Short-Circuit and Thermal Protection

• Space-Saving Package
– 2,2 mm × 2,2 mm Nano-Free™ WCSP (YZH)

DESCRIPTION

The TPA2026D2 is a stereo, filter-free Class-D audio
power amplifier with volume control, dynamic range
compression (DRC) and automatic gain control
(AGC). It is available in a 2.2 mm x 2.2 mm WCSP
package.

The DRC/AGC function in the TPA2026D2 is
programmable via a digital I2C interface. The
DRC/AGC function can be configured to automatically
prevent distortion of the audio signal and enhance
quiet passages that are normally not heard. The
DRC/AGC can also be configured to protect the

compress the dynamic range of music to fit within the
dynamic range of the speaker. The gain can be
selected from 0 dB to +30 dB in 1-dB steps. The
TPA2026D2 is capable of driving 3.2 W/Ch at 5 V
into an 4-Ω load or 750 mW/Ch at 3.6 V into an 8-Ω
load. The device features independent software
shutdown controls for each channel and also provides
thermal and short circuit protection. The TPA2026D2
has faster AGC gain ramp during start-up than
TPA2026D2.

In addition to these features, a fast start-up time and
small package size make the TPA2026D2 an ideal
choice for cellular handsets, PDAs, and other
portable applications.

APPLICATIONS

• Wireless or Cellular Handsets and PDAs

• Portable Navigation Devices

• Portable DVD Player

• Notebook PCs

• Portable Radio

• Portable Games

• Educational Toys

• USB Speakers

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SmartGain, Nano-Free are trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

SIMPLIFIED APPLICATION DIAGRAM

Copyright © 2010, Texas Instruments Incorporated

I2C Interface

& Control

INL+

INL-

SDA

OUTL+

OUTL-

SDZ

INR+

INR-

SCL

Class-D

Modulator

Volume
Control

Differential

Input Left

C

IN

1uF

Differential

Input Right

C

IN

1uF

I2C Interface

IC shutdown

Power

Stage

AGC

Reference

Volume
Control

Power

Stage

OUTR+

OUTR-

AGND PGND

Bias and

References

AVDD

PVDDR

PVDDL

AGC

Class-D

Modulator

PGND

OUTL–OUTR–OUTR+

INL–INR+ INL+INR–

AGNDSDASCLAVDD

PVDDLSDZPVDDR

OUTL+

D 1 D 2 D 3 D 4

C 1 C 2 C 3 C 4

B1 B3 B4B2

A1 A2 A3 A4

YZH(WCSP)PACKAGE

(TopView)

TPA2026D2

SLOS649 –MARCH 2010

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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FUNCTIONAL BLOCK DIAGRAM

DEVICE PINOUT

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TPA2026D2

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PIN FUNCTIONS

PIN

NAME WCSP

INR+ A2 I Right channel positive audio input
INR– A1 I Right channel negative audio input
INL+ A3 I Left channel positive audio input
INL– A4 I Left channel negative audio input
SDZ C2 I Shutdown terminal (active low)
SDA B3 I/O I2C data interface
SCL B2 I I2C clock interface
OUTR+ D1 O Right channel positive differential output
OUTR– D2 O Right channel negative differential output
OUTL+ D4 O Left channel positive differential output
OUTL– D3 O Left channel negative differential output
AVDD B1 P Analog supply (must be the same as PVDDR and PVDDL)
AGND B4 P Analog ground (all GND pins need to be connected)
PVDDR C1 P Right channel power supply (must be the same as AVDD and PVDDL)
PGND C3 P Power ground (all GND pins need to be connected)
PVDDL C4 P Left channel power supply (must be the same as AVDD and PVDDR)

I/O/P DESCRIPTION

SLOS649 –MARCH 2010

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted).

VALUE / UNIT

V

Supply voltage AVDD, PVDDR, PVDDL –0.3 V to 6 V

DD

Input voltage

Continuous total power dissipation

T

Operating free-air temperature range –40°C to 85°C

A

T

Operating junction temperature range –40°C to 150°C

J

T

Storage temperature range –65°C to 150°C

stg

ESD Electro-static discharge tolerance, all pins

R

Minimum load resistance 3.2 Ω

L

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS TABLE

PACKAGE TA≤ 25°C DERATING FACTOR TA= 70°C TA= 85°C

16-ball WCSP 1.25 W 10 mW/°C 0.8 W 0.65 W

(1) Dissipations ratings are for a 2-side, 2-plane PCB.

SDZ, INR+, INR–, INL+, INL– –0.3 V to VDD+0.3 V
SDA, SCL –0.3 V to 6 V

See Dissipation Ratings

Table

Human body model (HBM) 2 KV
Charged device model (CDM) 500 V

(1)

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): TPA2026D2

TPA2026D2

SLOS649 –MARCH 2010

T

A

–40°C to 85°C

AVAILABLE OPTIONS

PACKAGED DEVICE

16-ball, 2,2 mm × 2,2 mm WCSP (+0.01 mm/

-0.09 mm tolerance)

(2)

(1)

PART NUMBER SYMBOL

TPA2026D2 YZHR NSV
TPA2026D2 YZHT NSV

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(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com

(2) The YZH package is only available taped and reeled. The suffix R indicates a reel of 3000; the suffix T indicates a reel of 250.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

VDDSupply voltage AVDD, PVDDR, PVDDL 2.5 5.5 V
VIHHigh-level input voltage SDZ, SDA, SCL 1.3 V
VILLow-level input voltage SDZ, SDA, SCL 0.6 V
T

Operating free-air temperature –40 +85 °C

A

ELECTRICAL CHARACTERISTICS

at TA= 25°C, VDD= 3.6 V, SDZ = 1.3 V, and RL= 8 Ω + 33 mH (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

DD

I

SDZ

I

SWS

I

DD

f

SW

I

IH

I

IL

t

START

POR Power on reset ON threshold 2 2.3 V
POR Power on reset hysteresis 0.2 V

CMRR Input common mode rejection –70 dB

V

oo

Z

OUT

PSRR Power supply rejection ratio VDD= 2.5 V to 4.7 V -80 dB

Supply voltage range 2.5 3.6 5.5 V

SDZ = 0.35 V, VDD= 2.5 V 0.1 1

Shutdown quiescent current SDZ = 0.35 V, VDD= 3.6 V 0.2 1 µA

SDZ = 0.35 V, VDD= 5.5 V 0.3 1

SDZ = 1.3 V, VDD= 2.5 V 35 50
Software shutdown quiescent
current

SDZ = 1.3 V, VDD= 3.6 V 50 70 µA

SDZ = 1.3 V, VDD= 5.5 V 75 110

VDD= 2.5 V 3.5 4.5
Supply current VDD= 3.6 V 3.7 4.7 mA

VDD= 5.5 V 4.5 5.5
Class D switching frequency 275 300 325 kHz
High-level input current VDD= 5.5 V, SDZ = 5.8 V 1 µA
Low-level input current VDD= 5.5 V, SDZ = –0.3 V –1 µA
Start-up time 2.5 V ≤ VDD≤ 5.5 V no pop, CIN≤ 1 mF 5 ms

RL= 8 Ω, V

differential inputs shorted
Output offset voltage 2 10 mV
Output impedance in shutdown 2 kΩ

mode

VDD= 3.6 V, AV= 6 dB, RL= 8 Ω, inputs ac

grounded

SDZ = 0.35 V

= 0.5 V and V

icm

= VDD– 0.8 V,

icm

Gain accuracy Compression and limiter disabled, Gain = 0 to 30 dB –0.5 0.5 dB

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Product Folder Link(s): TPA2026D2

TPA2026D2

IN+

IN–

OUT+

OUT–

V

DD

V

DD

GND

C

I

C

I

Measurement

Output

+

+

–

–

Load

30kHz

Low-Pass

Filter

Measurement

Input

+

–

1 Fm

TPA2026D2

www.ti.com

SLOS649 –MARCH 2010

OPERATING CHARACTERISTICS

at TA= 25°C, VDD= 3.6V, SDZ = 1.3 V, RL= 8 Ω +33 mH, and AV= 6 dB (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

k

SVR

THD+N Total harmonic distortion + noise

Nfo
Nfo
FR Frequency response Av = 6 dB 20 20000 Hz

Po

h Efficiency

Power-supply ripple rejection ratio VDD= 3.6 Vdc with ac of 200 mVPPat 217 Hz –68 dB

f

= 1 kHz, PO= 550 mW, VDD= 3.6 V 0.1%

aud_in

f

= 1 kHz, PO= 1 W, VDD= 5 V 0.1%

aud_in

f

= 1 kHz, PO= 630 mW, VDD= 3.6 V 1%

aud_in

f

= 1 kHz, PO= 1.4 W, VDD= 5 V 1%

aud_in

Output integrated noise Av = 6 dB 44 mV

nF

Output integrated noise Av = 6 dB floor, A-weighted 33 mV

A

THD+N = 10%, VDD= 5 V, RL= 8 Ω 1.72 W

Maximum output power

max

THD+N = 10%, VDD= 3.6 V, RL= 8 Ω 750 mW
THD+N = 1%, VDD= 5 V, RL= 8 Ω 1.4 W
THD+N = 1% , VDD= 3.6 V, RL= 8 Ω 630 mW
THD+N = 1%, VDD= 3.6 V, RL= 8 Ω, PO= 0.63 W 90%
THD+N = 1%, VDD= 5 V, RL= 8 Ω, PO= 1.4 W 90%

TEST SET-UP FOR GRAPHS

(1) All measurements were taken with a 1-mF CI(unless otherwise noted).
(2) A 33-mH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (1 kΩ

4.7 nF) is used on each output for the data sheet graphs.

Product Folder Link(s): TPA2026D2

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5

SCL

SDA

t

w(H)

t

w(L)

t

su1

t

h1

SCL

SDA

t

h2

t

(buf)

t

su2

t

su3

StartCondition

StopCondition

TPA2026D2

SLOS649 –MARCH 2010

I2C TIMING CHARACTERISTICS

For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

SCL

t

W(H)

t

W(L)

t

SU(1)

t

h1

t

(buf)

t

SU2

t

h2

t

SU3

Frequency, SCL No wait states 400 kHz
Pulse duration, SCL high 0.6 ms
Pulse duration, SCL low 1.3 ms
Setup time, SDA to SCL 100 ns
Hold time, SCL to SDA 10 ns
Bus free time between stop and start 1.3 ms

condition
Setup time, SCL to start condition 0.6 ms
Hold time, start condition to SCL 0.6 ms
Setup time, SCL to stop condition 0.6 ms

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Figure 1. SCL and SDA Timing

Figure 2. Start and Stop Conditions Timing

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TPA2026D2

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SLOS649 –MARCH 2010

TYPICAL CHARACTERISTICS

with C

(DECOUPLE)

All THD + N graphs are taken with outputs out of phase (unless otherwise noted).

All data is taken on left channel.

= 1 mF, CI= 1 µF.

Table of Graphs

FIGURE

Quiescent supply current vs Supply voltage Figure 3
Supply current vs Supply voltage in shutdown Figure 4
Output level vs Input level Figure 5
Output level vs Input level Figure 6
Output level vs Input level Figure 7
Output level vs Input level Figure 8
Output level vs Input level Figure 9
Supply ripple rejection ratio vs Frequency, 8Ω Figure 10
Total harmonic distortion + noise vs Frequency Vsupply = 2.5V, 4Ω Figure 11
Total harmonic distortion + noise vs Frequency Vsupply = 2.5V, 8Ω Figure 12
Total harmonic distortion + noise vs Frequency Vsupply = 3.6V, 4Ω Figure 13
Total harmonic distortion + noise vs Frequency Vsupply = 3.6V, 8Ω Figure 14
Total harmonic distortion + noise vs Frequency Vsupply = 5.0V, 4Ω Figure 15
Total harmonic distortion + noise vs Frequency Vsupply = 5.0V, 8Ω Figure 16
Total harmonic distortion + noise vs Output power, 4Ω Figure 17
Total harmonic distortion + noise vs Output power, 8Ω Figure 18
Efficiency vs Output power (per channel), 4Ω Figure 19
Efficiency vs Output power (per channel), 8Ω Figure 20
Total power dissipation vs Total output power, 4Ω Figure 21
Total power dissipation vs Total output power, 8Ω Figure 22
Total supply current vs Total output power, 4Ω Figure 23
Total supply current vs Total output power, 8Ω Figure 24
Output power vs Supply voltage, 4Ω Figure 25
Output power vs Supply voltage, 8Ω Figure 26
TPA2026D2 vs TPA2016D2 Startup gain ramp Figure 27
TPA2026D2 vs TPA2016D2 Shutdown gain ramp Figure 28
Shutdown time Figure 29
Startup time Figure 30

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): TPA2026D2

VDD − Supply Voltage − V

0

2

4

6

8

10

2.5 3.5 4.5 5.5

I

DD

− Quiescent Supply Current − mA

G001

VDD − Supply Voltage − V

0

20

40

60

80

100

2.5 3.5 4.5 5.5

I

DD

− Supply Current − µA

G002

SDZ = 0 V

SDZ = VDD, SWS = 1

Input Level − dBV

−50

−40

−30

−20

−10

0

10

20

−40 −30 −20 −10 0 10

Output Level − dBV

G003

RL = 8 Ω + 33 µH
V

Supply

= 5 V
Fixed Gain = Max Gain = 30 dB
Compression Ratio = 1:1

Limiter Level = −6.5
Limiter Level = −4.5
Limiter Level = −2.5
Limiter Level = −0.5
Limiter Level = 1.5
Limiter Level = 3.5
Limiter Level = 5.5
Limiter Level = 7.5
Limiter Level = 9

Input Level − dBV

−50

−40

−30

−20

−10

0

10

20

−70 −50 −30 −10 10

Output Level − dBV

G004

Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
V

Supply

= 5 V
Fixed Gain (2:1)
Compression Ratio = 2:1
Max Gain = 30 dB

Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3
Fixed Gain = 6
Fixed Gain = 9
Fixed Gain = 12

TPA2026D2

SLOS649 –MARCH 2010

QUIESCENT SUPPLY CURRENT SUPPLY CURRENT

INPUT LEVEL WITH LIMITER ENABLED INPUT LEVEL WITH 2:1 COMPRESSION

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vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE IN SHUTDOWN

Figure 3. Figure 4.

OUTPUT LEVEL OUTPUT LEVEL

vs vs

Figure 5. Figure 6.

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Input Level − dBV

−50

−40

−30

−20

−10

0

10

20

−70 −50 −30 −10 10

Output Level − dBV

G005

Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
V

Supply

= 5 V
Compression Ratio = 4:1
Max Gain = 30 dB

Fixed Gain = −15
Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3
Fixed Gain = 6

Fixed Gain = −27
Fixed Gain = −24
Fixed Gain = −21
Fixed Gain = −18

Input Level − dBV

−50

−40

−30

−20

−10

0

10

20

−70 −50 −30 −10 10

Output Level − dBV

G006

Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
V

Supply

= 5 V
Compression Ratio = 8:1
Max Gain = 30 dB

Fixed Gain = −12
Fixed Gain = −9
Fixed Gain = −6
Fixed Gain = −3
Fixed Gain = 0
Fixed Gain = 3

Fixed Gain = −27
Fixed Gain = −24
Fixed Gain = −21
Fixed Gain = −18
Fixed Gain = −15

f − Frequency − Hz

K

SVR

− Supply Ripple Rejection Ratio − dB

20 100 1k 10k 20k

−100

−80

−60

−40

−20

0

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 8 Ω + 33 µH

Left Channel

Input Level − dBV

−50

−40

−30

−20

−10

0

10

20

−70 −50 −30 −10 10

Output Level − dBV

G007

Compression Ratio = 1:1
Compression Ratio = 2:1
Compression Ratio = 4:1
Compression Ratio = 8:1

Limiter Level = 9 dBV
RL = 8 Ω + 33 µH
V

Supply

= 5 V
Fixed Gain = 0 dB
Max Gain = 30 dB

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 25 mW
PO = 125 mW
PO = 300 mW

Gain = 6 dB
RL = 4 Ω + 33 µH
V

Supply

= 2.5 V

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 25 mW
PO = 125 mW
PO = 200 mW

Gain = 6 dB
RL = 8 Ω + 33 µH
V

Supply

= 2.5 V

TPA2026D2

www.ti.com

SLOS649 –MARCH 2010

OUTPUT LEVEL OUTPUT LEVEL

vs vs

INPUT LEVEL WITH 4:1 COMPRESSION INPUT LEVEL WITH 8:1 COMPRESSION

Figure 7. Figure 8.

OUTPUT LEVEL SUPPLY RIPPLE REJECTION RATIO

vs vs

INPUT LEVEL FREQUENCY, 8Ω

Figure 9. Figure 10.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY Vsupply = 2.5V, 4Ω FREQUENCY Vsupply = 2.5V, 8Ω

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 11. Figure 12.

vs vs

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f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 50 mW
PO = 250 mW
PO = 700 mW

Gain = 6 dB
RL = 4 Ω + 33 µH
V

Supply

= 3.6 V

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 50 mW
PO = 250 mW
PO = 500 mW

Gain = 6 dB
RL = 8 Ω + 33 µH
V

Supply

= 3.6 V

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 100 mW
PO = 500 mW
PO = 1.75 W

Gain = 6 dB
RL = 4 Ω + 33 µH
V

Supply

= 5.0 V

f − Frequency − Hz

THD+N − Total Harmonic Distortion + Noise − %

20 100 1k 10k 20k

0.001

0.01

0.1

1

10

PO = 100 mW
PO = 500 mW
PO = 1 W

Gain = 6 dB
RL = 8 Ω + 33 µH
V

Supply

= 5.0 V

PO − Output Power (Per Channel) − W

THD+N − Total Harmonic Distortion + Noise − %

10m 100m 1 4

0.01

0.1

1

10

100

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 4 Ω + 33 µH

f = 1 kHz

PO − Output Power (Per Channel) − W

THD+N − Total Harmonic Distortion + Noise − %

10m 100m 1 3

0.01

0.1

1

10

100

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 8 Ω + 33 µH

f = 1 kHz

TPA2026D2

SLOS649 –MARCH 2010

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY Vsupply = 3.6V, 4Ω FREQUENCY Vsupply = 3.6V, 8Ω

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY Vsupply = 5.0V, 4Ω FREQUENCY Vsupply = 5.0V, 8Ω

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vs vs

Figure 13. Figure 14.

vs vs

Figure 15. Figure 16.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

POWER, 4Ω POWER, 8Ω

Figure 17. Figure 18.

10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

vs vs

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PO − Output Power (Per Channel) − W

Efficiency − %

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

0

20

40

60

80

100

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 4 Ω + 33 µH

f = 1 kHz

PO − Output Power (Per Channel) − W

Efficiency − %

0.0 0.5 1.0 1.5 2.0

0

20

40

60

80

100

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 8 Ω + 33 µH

f = 1 kHz

PO − Total Output Power − W

P

D

− Total Power Dissipation − W

0 1 2 3 4 5 6 7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 4 Ω + 33 µH

f = 1 kHz

PO − Total Output Power − W

P

D

− Total Power Dissipation − W

0 1 2 3 4

0.0

0.1

0.2

0.3

0.4

V

Supply

= 2.5 V

V

Supply

= 3.6 V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 8 Ω + 33 µH

f = 1 kHz

PO − Total Output Power − W

I

DD

− Total Supply Current − A

0 1 2 3 4 5 6 7

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

V

Supply

= 2.5 V

V

Supply

= 3.6V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 4 Ω + 33 µH

f = 1 kHz

PO − Total Output Power − W

I

DD

− Total Supply Current − A

0 1 2 3 4

0.0

0.2

0.4

0.6

0.8

1.0

V

Supply

= 2.5 V

V

Supply

= 3.6V

V

Supply

= 5.0 V

Gain = 6 dB
RL = 8 Ω + 33 µH

f = 1 kHz

TPA2026D2

www.ti.com

SLOS649 –MARCH 2010

EFFICIENCY EFFICIENCY

vs vs

OUTPUT POWER (PER CHANNEL), 4Ω OUTPUT POWER (PER CHANNEL), 8Ω

Figure 19. Figure 20.

TOTAL POWER DISSIPATION TOTAL POWER DISSIPATION

vs vs

TOTAL OUTPUT POWER, 4Ω TOTAL OUTPUT POWER, 8Ω

Figure 21. Figure 22.

TOTAL SUPPLY CURRENT TOTAL SUPPLY CURRENT

TOTAL OUTPUT POWER, 4Ω TOTAL OUTPUT POWER, 8Ω

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Figure 23. Figure 24.

vs vs

Product Folder Link(s): TPA2026D2

Vsupply − Supply Voltage − V

P

O

− Output Power − W

2.5 3.0 3.5 4.0 4.5 5.0 5.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

THD = 1%
THD = 10%

f = 1 kHz
Gain = 6 dB
RL = 4 Ω + 33 µH
WCSP

Vsupply − Supply Voltage − V

P

O

− Output Power − W

2.5 3.0 3.5 4.0 4.5 5.0 5.5

0.0

0.5

1.0

1.5

2.0

2.5

THD = 1%
THD = 10%

f = 1 kHz
Gain = 6 dB
RL = 8 Ω + 33 µH
WCSP

TPA2026D2

SLOS649 –MARCH 2010

TPA2016D2 STARTUP GAIN RAMP TPA2016D2 SHUTDOWN GAIN RAMP

www.ti.com

OUTPUT POWER OUTPUT POWER

vs vs

SUPPLY VOLTAGE, 4Ω SUPPLY VOLTAGE, 8Ω

Figure 25. Figure 26.

TPA2026D2 TPA2026D2

vs vs

Figure 27. Figure 28.

12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TPA2026D2