Texas Instruments TP3057AN, TP3057ADWR, TP3054ADW, TP3054ADWR, TP3054AN Datasheet

TP3054A, TP3057A, TP13054A, TP13057A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass

Filtering

– Receive Low-Pass Filter With (sin x)/x

Correction

– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and

Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Autozero Circuitry

D

µ-Law . . . TP3054A and TP13054A

D

A-Law . . . TP3057A and TP13057A

D

±5-V Operation

D

Low Operating Power...50 mW Typ

D

Power-Down Standby Mode...3 mW Typ

D

Automatic Power Down

D

TTL- or CMOS-Compatible Digital Interface

D

Maximizes Line Interface Card Circuit
Density

D

Improved Versions of National
Semiconductor TP3054, TP3057, TP3054-X,
TP3057-X

description

The TP3054A, TP3057A, TP13054A, and
TP13057A are comprised of a single-chip PCM
codec (pulse code-modulated encoder and
decoder) and PCM line filter. These devices
provide all the functions required to interface a
full-duplex (2-wire) voice telephone circuit with a
TDM (time-division-multiplexed) system. These
devices are pin-for-pin compatible with the
National Semiconductor TP3054A and TP3057A,
respectively. Primary applications include:

• Line interface for digital transmission and

switching of T1 carrier, PABX, and central
office telephone systems

• Subscriber line concentrators

• Digital-encryption systems

• Digital voice-band data-storage systems

• Digital signal processing

These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3054A, TP3057A, TP13054A, and TP13057A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3057A and
TP13057A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below –55 dBm0.

The TP3054A and TP3057A are characterized for operation from 0°C to 70°C. The TP13054A and TP13057A
are characterized for operation from –40°C to 85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

BB

ANLG GND

VFRO

V

CC

FSR

DR

BCLKR/CLKSEL

MCLKR/PDN

VFXI+
VFXI–
GSX
TSX
FSX
DX
BCLKX
MCLKX

DW OR N PACKAGE

(TOP VIEW)

TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

R2

GSX

14

VBBANLG GNDV

CC

412

–5 V

FSX

5 V

9 8 10 7 125

MCLKX MCLKR/

PDN

BCLKX BCLKR/

CLKSEL

FSR

TSX

13

Power

Amplifier

Timing and Control

DR

6

CLK

Receive

Regulator

S/H

DAC

RC Active

Filter

11

DX

OE

Transmit

Regulator

A/D

Control

Logic

Comparator

Voltage

Reference

Autozero

Logic

S/H

DAC

Switched­Capacitor

Band-Pass Filter

RC

Active Filter

3

VFRO

+

–

VFXI+

16

R1

15

VFXI–

Analog

Input

Switched­Capacitor

Low-Pass Filter

TP3054A, TP3057A, TP13054A, TP13057A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

DESCRIPTION

ANLG GND 2 Analog ground. All signals are referenced to ANLG GND.
BCLKR/CLKSEL 7 The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,

BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in
the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1).

BCLKX 10 The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with

MCLKX.
DR 6 Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX 11 The 3-state PCM data output that is enabled by FSX.
FSR 5 Receive-frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
FSX 12 Transmit-frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
GSX 14 Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN 8 Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should

be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected

for all internal timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX 9 Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
TSX 13 Open-drain output that pulses low during the encoder time slot
V

BB

1 Negative power supply. VBB = –5 V ±5%

V

CC

4 Positive power supply. VCC = 5 V ±5%
VFRO 3 Analog output of the receive filter
VFXI+ 16 Noninverting input of the transmit input amplifier
VFXI– 15 Inverting input of the transmit input amplifier

TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, V

BB

(see Note 1) –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any analog input or output V

CC

+0.3 V to VBB –0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any digital input or output V

CC

+0.3 V to ANLG GND –0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: TP3054A, TP3057A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP13054A, TP13057A –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DW 1025 mW 8.2 mW/°C 656 mW 533 mW

N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

Supply voltage, V

BB

–4.75 –5 –5.25 V

High-level input voltage, V

IH

2.2 V

Low-level input voltage, V

IL

0.6 V

Common-mode input voltage range, V

ICR

‡

±2.5 V

Load resistance, GSX, R

L

10 kΩ

Load capacitance, GSX, C

L

50 pF

p

p

TP3054A, TP3057A 0 70

°

Operating free-air temperature, T

A

TP13054A, TP13057A –40 85

°C

‡

Measured with CMRR > 60 dB.

NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

power-up sequence paragraphs later in this document should be followed.

electrical characteristics over recommended ranges of supply voltage operating free-air
temperature range (unless otherwise noted)

supply current

TP305xA TP1305xA

PARAMETER

TEST CONDITIONS

MIN TYP‡MAX MIN TYP‡MAX

UNIT

pp

Power down

0.5 1 0.5 1.2

ICCSupply current from V

CC

Active

No load

6 9 6 10

mA

pp

Power down

0.5 1 0.5 1.2

IBBSupply current from V

BB

Active

No load

6 9 6 10

mA

TP3054A, TP3057A, TP13054A, TP13057A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at VCC = 5 V ±5%, V

BB

= – 5 V ± 5%, GND at 0 V, T

A

= 25°C (unless

otherwise noted)

digital interface

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

OH

High-level output voltage DX IH = -3.2 mA 2.4 V

p

DX IL = 3.2 mA 0.4

VOLLow-level output voltage

TSX IL = 3.2 mA, Drain open 0.4

V

I

IH

High-level input current VI = VIH to V

CC

±10 µA

I

IL

Low-level input current All digital inputs VI = GND to V

IL

±10 µA

I

OZ

Output current in high-impedance state DX VO = GND to V

CC

±10 µA

analog interface with transmit amplifier input

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

I

Input current VFXI+ or VFXI – VI = –2.5 V to 2.5 V ±200 nA

r

i

Input resistance VFXI+ or VFXI – VI = –2.5 V to 2.5 V 10 MΩ

r

o

Output resistance Closed loop, Unity gain 1 3 Ω
Output dynamic range GSX RL ≥ 10 kΩ ±2.8 V

A

V

Open-loop voltage amplification VFXI+ to GSX 5000

B

I

Unity-gain bandwidth GSX 1 2 MHz

V

IO

Input offset voltage VFXI+ or VFXI – ±20 mV
CMRR Common-mode rejection ratio 60 dB
K

SVR

Supply-voltage rejection ratio 60 dB

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25

°C.

analog interface with receive filter

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Output resistance VFRO 1 3 Ω
Load resistance VFRO = ±2.5 V 600 Ω
Load capacitance VFRO to GND 500 pF
Output dc offset voltage VFRO to GND ±200 mV

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS026C – SEPTEMBER 1992 – REVISED JUL Y 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

f

clock(M)

Frequency of master clock

MCLKX and
MCLKR

Depends on the device used and
BCLKX/CLKSEL

1.536

1.544

2.048

MHz

f

clock(B)

Frequency of bit clock, transmit BCLKX 64 2048 kHz

t

w1

Pulse duration, MCLKX and MCLKR high 160 ns

t

w2

Pulse duration, MCLKX and MCLKR low 160 ns

t

r1

Rise time of master clock

MCLKX and
MCLKR

50 ns

t

f1

Fall time of master clock

MCLKX and
MCLKR

Measured from 20% to 80%

50 ns

t

r2

Rise time of bit clock, transmit BCLKX

50 ns

t

f2

Fall time of bit clock, transmit BCLKX

Measured from 20% to 80%

50 ns

t

su1

Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKX↓

First bit clock after the leading
edge of FSX

100 ns

t

w3

Pulse duration, BCLKX and BCLKR high VIH = 2.2 V 160 ns

t

w4

Pulse duration, BCLKX and BCLKR low VIL = 0.6 V 160 ns

t

h1

Hold time, frame sync low after bit clock low
(long frame only)

0 ns

t

h2

Hold time, BCLKX high after frame sync↑
(short frame only)

0 ns

t

su2

Setup time, frame sync high before bit clock↓
(long frame only)

80 ns

t

d1

Delay time, BCLKX high to data valid

Load = 150 pF plus 2 LSTTL loads

‡

0 140 ns

t

d2

Delay time, BCLKX high to TSX low

Load = 150 pF plus 2 LSTTL loads

‡

140 ns

t

d3

Delay time, BCLKX (or 8 clock FSX in long frame only)
low to data output disabled

50 165 ns

t

d4

Delay time, FSX or BCLKX high to data valid (long
frame only)

CL = 0 pF to 150 pF 20 165 ns

t

su3

Setup time, DR valid before BCLKR↓ 50 ns

t

h3

Hold time, DR valid after BCLKR or BCLKX↓ 50 ns

t

su4

Setup time, FSR or FSX high before BCLKR or
BCLKR↓

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

50 ns

t

h4

Hold time, FSX or FSR high after BCLKX or BCLKR↓

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

100 ns

t

h5

Hold time, frame sync high after bit clock↓

Long-frame sync pulse
(from 3 to 8 bit clock periods long)

100 ns

t

w5

Minimum pulse duration of the frame sync pulse
(low level)

64 kbps operating mode 160 ns

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

‡

Nominal input value for an LSTTL load is 18 kΩ.

NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.