Texas Instruments TNETX3270 User Manual

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

D

Port Configurations:
Twenty-Four 10-Mbit/s Ports
– Ports Arranged in Three Groups of Eight

Ports in a Multiplexed Interface

– Direct Multiplexer Interface to

TNETE2008
– Full and Half Duplex
– Half-Duplex Collision-Based Flow

Control
– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE

Std 802.1Q VLAN
– Speed, Duplex, and Pause

Autonegotiation With Physical Layer

(PHY)
Three 10-/100-Mbit/s Ports
– Direct Interface to TNETE2101
– Full and Half Duplex
– Half-Duplex Collision-Based Flow

Control
– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE

Std 802.1Q VLAN
– Pretagging Support

D

Port Trunking and Load Sharing

D

LED Indication of Port Status

D

SDRAM Interface
– Direct Interface to 8-Bit/Word and

16-Bit/Word, 16-Mbit, and 64-Mbit

SDRAMs
– 32-Bit-Wide Data Bus

– Up to 32 Mbytes Supported
– 83.33-MHz SDRAM Clock
– 12-ns (–12) SDRAMs Required

D

Remote Monitoring (RMON) Support –
Groups 1, 2, 3, and 9

D

Direct I/O (DIO) Management Interface
– Eight Bits Wide
– CPU Access to Statistics, Registers, and

Management Information Bases (MIBs)
– Internal Network Management Port
– Forwards Spanning-Tree Packets to CPU
– Serial Media-Independent Interface (MII)

for PHY Control

D

EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)

D

Internal Address-Lookup/Frame-Routing
Engine
– Interoperable Support for IEEE

Std 802.1Q VLAN
– Supports IEEE Std 802.1D Spanning Tree
– Thirty-Two Assignable Virtual LANs

(VLANs)
– Multiple Forwarding Modes
– 2K Total Addresses Supported
– Port Mirroring

D

IEEE Std 1149.1 (JTAG) Interface (3.3-V
Signals)

D

2.5-V Process With 3.3-V-Drive I/O

D

Packaged in 240-Terminal Plastic Quad
Flatpack

TAP

(JTAG)

SDRAM

Controller

EEPROM
Interface

CPU

Interface

LED

Interface

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Manager

Address

Compare

Queue

Network

Statistics

Logic

Statistics

Storage

MIB

Data Path

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)

MUX

MUX

MUX

MII
MII
MII

Copyright  1999, Texas Instruments Incorporated

Eight Ports
(00–07)
10 Mbit/s

Eight Ports
(08–15)
10 Mbit/s

Eight Ports
(16–23)
10 Mbit/s

Three Ports
(24–26)
10/100 Mbit/s

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

description

The TNETX3270 provides highly integrated switching solutions that allow network designers to lower overall
system costs. Based on Texas Instruments (TI) ThunderSWITCH architecture, the TNETX3270 design
integrates 24 full-duplex 10-Mbit/s ports and 3 full-duplex 10-/100-Mbit/s ports, as well as an address-lookup
engine, all in a single 240-pin package. All ports on the TNETX3270 are designed to support multiple addresses,
cut-through or store-and-forward modes of operation, and VLAN. The 10-/100-Mbit/s ports have
media-independent interface (MII)-compatible interfaces and can be configured to work as MII uplinks to
high-speed switching fabrics. All three of the 10-/100-Mbit/s ports can be logically combined into a single
high-performance uplink channel that can be used to provide up to 600-Mbit/s switch-to-switch connections.

The TNETX3270 incorporates an internal content-addressable memory (CAM) capable of supporting 2,048 end
stations from a single switch. In addition, the device supports 32 user-configurable VLAN-broadcast domains
(IEEE Std 802.1Q), which allows IEEE Std 802.1P priority support interoperability , IEEE Std 802.3X full-duplex
flow control, and a collision-based flow-control scheme. The TNETX3270 also integrates an EEPROM interface
that allows the device to be initialized and configured without the added expense of a CPU. All of these features
on chip greatly reduce the number of external components required to build a switch.

The internal address-lookup engine (IALE) supports up to 2K unicast/multicast and broadcast addresses and
up to 32 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGV Package Terminal Layout 4. . . . . . . . . . . . . . . . . . . . . . . . . .

TNETX3270 Interface Block Diagram 5. . . . . . . . . . . . . . . . . . . .

Terminal Functions 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIO Register Groups 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Description 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIO Interface 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiving/Transmitting Management Frames 18. . . . . . . .

State of DIO Signals During Hardware Reset 18. . . . . . . .

Network Management Port 19. . . . . . . . . . . . . . . . . . . . . . . .

MII Serial Management Interface (PHY Management) 22. . .

10-Mbit/s and 10-/100-Mbit/s MAC Interface 22. . . . . . . . . . . .

Receive Control 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Giant (Long) Frames 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short Frames 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Filtering of Frames 23. . . . . . . . . . . . . . . . . . . . . . .

Data Transmission 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Control 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Adaptive Performance Optimization

(APO) (Transmit Pacing) 23. . . . . . . . . . . . . . . . . . . . . . . . .

Interframe Gap Enforcement 23. . . . . . . . . . . . . . . . . . . . . .

Backoff 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Versus Transmit Priority 24. . . . . . . . . . . . . . . . . .

Uplink Pretagging 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Interface 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interaction of EEPROM Load With the SIO Register 28. .

Summary of EEPROM Load Outcomes 28. . . . . . . . . . . . .

Compatibility With Future Device Revisions 28. . . . . . . . .

JTAG Interface 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HIGHZ instruction 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LED Interface 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lamp Test 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multi-LED Display 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Configurations 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-Mbit/s MAC Interfaces (Ports 00–23) 30. . . . . . . . . . . . . . .

10-/100-Mbit/s MAC Interfaces (Ports 24–26) 34. . . . . . . . . . .

10-/100-Mbit/s Port Configuration 34. . . . . . . . . . . . . . . . . .

10-/100-Mbit/s Port Configuration

in a Nonmanaged Switch 35. . . . . . . . . . . . . . . . . . . . . . . . .

10-/100-Mbit/s Port Configuration

in a Managed Switch 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Contents

SDRAM Interface 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDRAM-Type and Quantity Indication 38. . . . . . . . . . . . . . . . .

Initialization 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Refresh 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame Routing 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VLAN Support 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE Std 802.1Q Headers – Reception 40. . . . . . . . . . . . . . . .

IEEE Std 802.1Q Headers – Transmission 40. . . . . . . . . . . . .

Address Maintenance 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Spanning-Tree Support 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Aging Algorithms 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame-Routing Determination 41. . . . . . . . . . . . . . . . . . . . . . . .

Port Mirroring 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Trunking/Load Sharing 45. . . . . . . . . . . . . . . . . . . . . . . . . .

Flow Control 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision-Based Flow Control 46. . . . . . . . . . . . . . . . . . . . . . . . .

IEEE Std 802.3 Flow Control 46. . . . . . . . . . . . . . . . . . . . . . . . .

Internal Wrap Test 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duplex Wrap Test 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Mirroring 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Copy to Uplink 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 51. . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 52. . . . . . . . . . . . . . . . . . . . . .

Test Measurement 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-Mbit/s Interface (Ports 00–23) 53. . . . . . . . . . . . . . . . . . . . . . . . . .

10-/100-Mbit/s MAC Interface 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDRAM Interface 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIO/DMA Interface 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial MII Management Interface 60. . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Interface 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LED Interface 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power-Up OSCIN and RESET 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

PGV PACKAGE

(TOP VIEW)

DD26
DD27
DD28

V

DD(2.5V)

DD29
DD30
DD31

GND
DCAS
DRAS

DW

V

DD(3.3V)

DCLK

GND

DA00
DA01

V

DD(2.5V)

DA02
DA03
DA04

GND

DA05
DA06
DA07
DA08
DA09
DA10

GND

DA11

DA12

V

DD(2.5V)

DA13

TH0RENEG

GND

TH0TXD0
TH0TXD1
TH0TXD2
TH0TXD3
TH0TXEN

GND

TH0SYNC

TH0CLK
TH0COL

TH0CRS

V

DD(2.5V)

TH0RXDV
TH0RXD0
TH0RXD1

V

DD(3.3V)

TH0RXD2
TH0RXD3

TH0LINK

TH1RENEG

TH1TXD0

GND

TH1TXD1
TH1TXD2

V

DD(2.5V)

TH1TXD3

TH1TXEN

181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

DD25

180

1

DD(2.5V)

DD24VDD23

DD22

GND

DD21

DD20

175

179

178

177

176

174

173

5

2346789

DD15

DD14

167

DD(2.5V)

V

165

166

15

DD13

164

DD(3.3V)

V

DD12

163

162

DD11

161

20

GND

160

DD10

159

DD09

158

DD08

DD07

157

25

156

DD06

GND

155

154

DD05

153

DD04

V

152

DD(2.5V)

DD03

DD02

150

151

149

GND

148

DD01

147

DD00

SRXRDY

145

146

35

STXRDY

SAD1

SAD0

144

143

142

GND

141

40

SINT

140

SRDY

SCS

139

138

V

DD(3.3V)

DD19

DD18

DD17

DD16

V

170

172

171

169

168

10

1112131416171819212223242627282930313233343637383941424344464748495152535456575859

DD(2.5V)

SDATA7

SDATA6

135

137

136

45

GND

134

DD(3.3V)

V

SDATA5

133

132

SDATA4

131

50

SDATA3

130

SDATA2

129

GND

128

SDATA1

127

SDATA0

126

55

DD(2.5V)

SRNW

V

125

124

V

SDMA

123

122

DD(3.3V)

MDCLK

121
120
119
118
117
116
115
114
113
112

111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

60

MDIO
MRESET
V

DD(2.5V)

ECLK
EDIO
RESET
LEDDATA
LEDCLK
OSCIN
TRST
TDI
V

DD(3.3V)

TDO
TMS
TCLK
V

DD(2.5V)

M26FORCE10
M26FORCEHD
M26LINK
M26RXER
GND
M26RXDV
M26RXD3
M26RXD2
M26RXD1
M26RXD0
GND
M26RCLK
M26CRS
V

DD(2.5V)

M26COL
M26TXER
GND
M26TXEN
M26TXD3
M26TXD2
M26TXD1
M26TXD0
M26TCLK
GND
M25FORCE10
M25FORCEHD
M25LINK
V

DD(2.5V)

M25RXER
M25RXDV
GND
M25RXD3
V

DD(3.3V)

M25RXD2
M25RXD1
M25RXD0
GND
M25RCLK
M25CRS
M25COL
V

DD(2.5V)

M25TXER
M25TXEN
M25TXD3

DD(2.5V)

TH1CRS

V

GND

TH1RXD0

TH1RXD1

TH1RXDV

TH1CLK

TH1COL

TH1SYNC

4

DD(3.3V)

TH1RXD2

TH1RXD3

V

GND

TH1LINK

TH2RENEG

DD(2.5V)

TH2TXD0

TH2TXD1

V

TH2TXD2

TH2TXD3

TH2TXEN

TH2CLK

TH2COL

TH2SYNC

TH2CRS

TH2RXD0

TH2RXDV

TH2RXD1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DD(2.5V)

V

TH2RXD2

TH2RXD3

GND

TH2LINK

M24TCLK

M24TXD0

M24TXD1

M24TXD2

GND

M24TXD3

M24TXEN

M24COL

M24CRS

M24TXER

DD(2.5V)

V

M24RCLK

M24RXD0

M24RXD1

M24RXD2

M24RXD3

M24RXDV

M24LINK

M24RXER

24FORCEHD

GND

DD(2.5V)

V

M25TCLK

M25TXD0

M24FORCE10

M25TXD1

M25TXD2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 5

JTAG

Test Access

Port (TAP)

DRAM

Port

EEPROM

Port

SDATA7–SDATA0

CPU

Interface

LED

Activity

Port

Serial

MII

Interface

Miscellaneous

Functions

†

xx is the port number that is being monitored.

TRST

TMS

TCLK

TDI

TDO

DD31–DD0
DA12–DA0

DCLK
DRAS
DCAS

DW

ECLK

EDIO

SAD1–SAD0

SRNW

SCS

SRDY

SDMA

SINT

STXRDY

SRXRDY

LEDDATA

LEDCLK

MDCLK

MDIO

MRESET

OSCIN

RESET

SDRAM

Controller

EEPROM
Interface

CPU

Interface

LED

Interface

MII

TAP

Queue

Manager

Address

Compare

Network

Statistics

Logic

Statistics

Storage

MIB

Data Path

Controller (MAC)

Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)

Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

MII

MII

MII

MUX MUX MUX

TH0CLK
TH0TXD3–TH0TXD0
TH0TXEN
TH0COL
TH0CRS
TH0SYNC
TH0RXD3–TH0RXD0
TH0RXDV
TH0LINK
TH0RENEG

TH1CLK
TH1TXD3–TH1TXD0
TH1TXEN
TH1COL
TH1CRS
TH1SYNC
TH1RXD3–TH1RXD0
TH1RXDV
TH1LINK
TH1RENEG

TH2CLK
TH2TXD3–TH2TXD0
TH2TXEN
TH2COL
TH2CRS
TH2SYNC
TH2RXD3–TH2RXD0
TH2RXDV
TH2LINK
TH2RENEG

MxxTCLK
MxxTXD3–MxxTXD0
MxxTXEN
MxxTXER
MxxCOL
MxxCRS
MxxRCLK
MxxRXD3–MxxRXD0
MxxRXDV
MxxRXER
MxxFORCE10
MxxFORCEHD
MxxLINK

Eight Ports
(00–07)
10 Mbit/s

Eight Ports
(08–15)
10 Mbit/s

Eight Ports
(16–23)
10 Mbit/s

Three Ports

†

(24–26)
10/100 Mbit/s

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

ThunderSWITCH 24/3 ETHERNET SWITCH

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999



TNETX3270

Figure 1. TNETX3270 Interface Block Diagram

PRODUCT PREVIEW

TNETX3270

I/O

DESCRIPTION

ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions

10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, TH1, and

222

2

23

223

3

24

224

5

25

232

13
32

213
233

15

231
230
228
227

11
10

9
7

†

INTERNAL

RESISTOR

I Pullup

I Pulldown

I Pulldown

I Pulldown

O None

I Pullup

‡

Interface clock. Eight ports are supported on each interface and use this common 20-MHz
clock.

Interface collision sense. Assertion of THxCOL† during half-duplex operation indicates
network collision on the current port. Additionally, during full-duplex operation, transmission
of new frames does not start if this terminal is asserted.

Interface carrier sense. THxCRS† indicates a frame carrier signal is being received on a
current port.

Interface link presence. THxLINK† indicates the presence of the connection on a port.

– Low = no link
– High = link good

Interface renegotiate. A 1-0-1 sequence output on THxRENEG causes flow control and
half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.
These THxRENEG

Interface receive data. The receive data nibble from the current port is synchronous to
THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.
THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals
also are used to report the channel state to the MAC.

terminals connect to IFFORCEHD on TNETE2008.

TH2) of eight ports

TERMINAL

NAME NO.

TH0CLK
TH1CLK
TH2CLK

TH0COL
TH1COL
TH2COL

TH0CRS
TH1CRS
TH2CRS

TH0LINK
TH1LINK
TH2LINK

TH0RENEG
TH1RENEG
TH2RENEG

TH0RXD3
TH0RXD2
TH0RXD1
TH0RXD0

TH1RXD3
TH1RXD2
TH1RXD1
TH1RXD0

TH2RXD3
TH2RXD2
TH2RXD1
TH2RXD0

TH0TXEN
TH1TXEN
TH2TXEN

TH0SYNC
TH1SYNC
TH2SYNC

†

THx = TH0, TH1, and TH2

‡

Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required
in their system.

30
29
28
27

219
240

O None Interface transmit enable. THxTXEN indicates valid transmit data on THxTXD.

21

221

1

22

I Pullup

Interface synchronize. THxSYNC is used to synchronize the port traffic between the
media-access controller (MAC) and PHY. When THxSYNC is a 1, the current MAC-to-PHY
path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface
TH2. THxSYNC is sampled by the MAC on the falling edge of THxCLK.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

I/O

DESCRIPTION

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions (Continued)

10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, TH1, and

20
19
18
16

6

26

42
65
90

43
66
92

54
80

104

52
78

102

53
79

103

44
67
93

†

(continued)

INTERNAL
RESISTOR

Interface transmit data. The transmit data nibble for the current port is synchronous to

O None

I Pulldown

THxCLK. When THxTXEN is asserted, these signals carry data. THxTXD3–THxTXD0 are
used during renegotiation to convey flow-control and duplex configuration requests to the
PHY. THxTXD0 is the least significant bit and THxTXD3 is the most significant bit.

Interface receive data valid. When THxRXDV is a 1, it indicates that the THxRXD lines contain
valid data.

‡

INTERNAL
RESISTOR

Collision sense. Assertion of MxxCOL in half-duplex signal indicates a network collision

I Pulldown

I Pulldown Carrier sense. MxxCRS indicates a frame carrier signal is being received.

§

I/O

I/O

Pullup

I Pulldown

‡

Pullup

I Pullup Receive clock. Receive clock source from the attached PHY or PMI device.

on that port. In full-duplex operation, transmission of new frames does not start if this
terminal is asserted.

Speed selection (force 10 Mbit/s is active low)

– If pulled low by either the TNETX3270 or a PHY, the port operates at 10 Mbit/s.
– If not pulled low by either the TNETX3270 or a PHY , the internal pullup resistor holds
this signal high and the port operates at 100 Mbit/s. An external 4.7-kΩ pullup resistor
connected to V

Connection status. MxxLINK indicates the presence of a port connection.

– If MxxLINK = 0, there is no link.
– If MxxLINK = 1, the link is good.

Duplex selection (force half duplex is active low)

– If pulled low by either the TNETX3270 or the PHY, the port operates at half duplex.
– If not pulled low by either the TNETX3270 or the PHY , the internal pullup resistor holds
this signal high and the port operates at full duplex. An external 4.7-kΩ pullup resistor
connected to V

DD(3.3V)

DD(3.3V)

may be required, depending on the system layout.

may be required, depending on the system layout.

TH2) of eight ports

TERMINAL

NAME NO.

TH0TXD3
TH0TXD2
TH0TXD1
TH0TXD0

TH1TXD3
TH1TXD2
TH1TXD1
TH1TXD0

TH2TXD3
TH2TXD2
TH2TXD1
TH2TXD0

TH0RXDV
TH1RXDV
TH2RXDV

†

THx = TH0, TH1, and TH2

218
217
216
215

239
237
236
234

226

10-/100-Mbit/s MAC interface (ports 24–26)

TERMINAL

NAME NO.

M24COL
M25COL
M26COL

M24CRS
M25CRS
M26CRS

M24FORCE10
M25FORCE10
M26FORCE10

M24LINK
M25LINK
M26LINK

M24FORCEHD
M25FORCEHD
M26FORCEHD

M24RCLK
M25RCLK
M26RCLK

‡

xx = ports 24, 25, and 26

§

Not a true bidirectional terminal. It can only be actively pulled down (open drain).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TNETX3270

I/O

DESCRIPTION

ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (ports 24–26) (continued)

TERMINAL

NAME NO.

M24RXD3
M24RXD2
M24RXD1
M24RXD0

M25RXD3
M25RXD2
M25RXD1
M25RXD0

M26RXD3
M26RXD2
M26RXD1
M26RXD0

M24RXDV
M25RXDV
M26RXDV

M24RXER
M25RXER
M26RXER

M24TCLK
M25TCLK
M26TCLK

M24TXD3
M24TXD2
M24TXD1
M24TXD0

49
48
47
46

73
71
70
69

98
97
96
95

50
75
99

51
76

101

33
56
82

38
37
36
35

INTERNAL
RESISTOR

Receive data (nibble receive data from the attached PHY or PMI device). Data on these

I Pullup

I Pulldown

I Pulldown Receive error. MxxRXER indicates a coding error on received data.

I Pullup Transmit clock. Transmit clock source from the attached PHY or PMI device.

signals is synchronous to MxxRCLK. MxxRXD0 is the least significant bit and MxxRXD3
is the most significant bit.

Receive data valid. When high, MxxRXDV indicates valid data is present on the
MxxRXD3–MxxRXD0 lines.

†

M25TXD3
M25TXD2
M25TXD1
M25TXD0

M26TXD3
M26TXD2
M26TXD1
M26TXD0

M24TXEN
M25TXEN
M26TXEN

M24TXER
M25TXER
M26TXER

†

xx = ports 24, 25, and 26

61
60

O None

59
57

86
85
84
83

39
62

O None Transmit enable. MxxTXEN indicates valid transmit data on MxxTXD3–MxxTXD0.

87
41

63

O None

89

Transmit data (nibble transmit data). When MxxTXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to MxxTCLK. MxxTXD0 is the least
significant bit and MxxTXD3 is the most significant bit.

Transmit error . MxxTXER allows coding errors to be propagated across the MII. MxxTXER
is taken high when an under-run in the transmit FIFO for port xx occurs and causes fill data
to be transmitted (MxxTXER is low otherwise). MxxTXER is asserted at the end of an
under-running frame, enabling the device to force a coding error .

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

SDRAM interface

TERMINAL

NAME NO.

DA13
DA12
DA11
DA10
DA09
DA08
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00

DCAS

DCLK
DD31

DD30
DD29
DD28
DD27
DD26
DD25
DD24
DD23
DD22
DD21
DD20
DD19
DD18
DD17
DD16
DD15
DD14
DD13
DD12
DD11
DD10
DD09
DD08
DD07
DD06
DD05
DD04
DD03
DD02
DD01
DD00

DRAS
DW

212
210
209
207
206
205
204
203
202
200
199
198
196
195

189 O None

193 O None
187

186
185
183
182
181
180
179
177
176
174
173
172
171
170
168
167
166
164
162
161
159
158
157
156
155
153
152
150
149
147
146

190 O None SDRAM row address strobe. DRAS, with DCAS and DW, supplies the SDRAM commands.
191 O None SDRAM write select. DW, with DRAS and DCAS, supplies the SDRAM commands.

O None

I/O Pullup

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions (Continued)

INTERNAL
RESISTOR

SDRAM address bus (time-multiplexed bank, row, and column address). The address bus
DA13–DA00 also provides the SDRAM mode register initialization value. DA13 is the most significant
bit and DA00 is the least significant bit.

SDRAM column address strobe. DCAS, in conjunction with DRAS and DW, determines the SDRAM
commands.

SDRAM clock (83.33-MHz clock to the SDRAMs). SDRAM commands, addresses, and data are
sampled by the SDRAM on the rising edge of this clock.

SDRAM data bus (bidirectional bus used to carry SDRAM data). DD31–DD00 also output status
information to indicate buffer operation type and port number . Internal pullup resistors are provided.
DD31 is the most significant bit and the DD00 is the least significant bit.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TNETX3270

I/O

DESCRIPTION

ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions (Continued)

host DIO interface

TERMINAL

NAME NO.

SAD1
SAD0

SCS

SDMA

SDATA7
SDATA6
SDATA5
SDATA4
SDATA3
SDATA2
SDATA1
SDATA0

SINT

SRDY

SRNW

SRXRDY

STXRDY

143
142

138 I Pullup DIO chip select. When low, SCS indicates a DIO port access is valid.

123 I Pullup

136
135
133
131
130
129
127
126

140 O None

139 O Pullup

125 I Pullup

145 O None

144 O None

INTERNAL
RESISTOR

I Pullup DIO address bus. SAD1 and SAD0 select the internal host registers, when SDMA is high.

DIO DMA select. When low, SDMA modifies the behavior of the DIO interface to allow it to operate
with an external DMA controller. The SAD0 and SAD1 terminals are not used to select the internal
host register for the access. Instead, the DIO address to access is provided by the DMA address
register, and one of two host register addresses is selected according to DMAinc in the Syscontrol
register.

– If DMAinc = 1, accesses are the DIOdatainc register and DMAaddress increments after each
access.
– If DMAinc = 0, accesses are the DIOdata register, and DMAaddress does not increment after
each address.

I/O Pullup

DIO data interface bus (byte-wide bidirectional DIO port). SDATA7 is the most significant bit and
SDATA0 is the least significant bit.

DIO interrupt line (interrupt to the attached microprocessor). The interrupt originating event is
stored in the Int register.

DIO ready signal

– When low during reads, SRDY
– When low during writes, SRDY
high. SRDY

DIO read not write

– When high, read operation is selected.
– When low, write operation is selected.

Network management port, receive ready. When high, SRXRDY indicates that the network
management port’s RX buffers are empty and the network management port is able to receive
a frame.

Network management port, transmit ready. STXRDY indicates that at least one frame buffer is
available to be read by the management CPU.

– It outputs as a 1 if any of the end-of-frame (EOF) bits, start-of-frame (SOF) bits, or one of the
bits in NMTxcontrol is set to 1.
– Otherwise, it outputs 0.

is driven high for one clock cycle before placing the output in high impedance.

indicates to the host when data is valid to be read.

indicates when data has been received after SCS is taken

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

I/O

DESCRIPTION

I/O

DESCRIPTION

I/O

DESCRIPTION

Terminal Functions (Continued)

serial MII management PHY interface

TERMINAL

NAME NO.

MDCLK

MDIO

MRESET

121 O/High Z Pullup

120 I/O Pullup

119 O/High Z Pullup

EEPROM interface

TERMINAL

NAME NO.

ECLK

EDIO

117 O None EEPROM data clock.

116 I/O Pullup

INTERNAL
RESISTOR

INTERNAL
RESISTOR

EEPROM data I/O. An external pulldown resistor may be required for proper operation. Since this
terminal has an internal pullup, it can be left unconnected if no EEPROM is present. The EEPROM
is optional if a management CPU is present.

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Serial MII management data clock. MDCLK can be disabled (high impedance) through the
use of the SIO register.

Serial MII management data I/O. MDIO can be disabled, placed in high Z, through the SIO
register. An external 4.7-kΩ pullup resistor , conected to V
rise-time requirements.

Serial MII management reset. MRESET can be disabled (high impedance) through the use
of the SIO register. If connected to a PHY device, an external pullup resistor is
recommended.

DD(3.3V)

, is needed to meet the

LED interface

TERMINAL

NAME NO.

LEDCLK
LEDDATA

113 O None LED clock (serial shift clock for the LED status data)
114 O None

JTAG interface

TERMINAL

NAME NO.

TCLK

TDI

TDO

TRST

TMS

106 I Pullup

110 I Pullup

108 O None

111 I Pullup

107 I Pullup

INTERNAL
RESISTOR

LED data (serial LED status data). LEDDATA is active low . All LED information (port link, activity
status, software status, flow status, and fault status) is sent via this serial interface.

INTERNAL
RESISTOR

T est clock. TCLK is used to clock state information, test instructions, and test data into and out of the
device during operation of the test port.

Test data input. TDI is used to serially shift test data and test instructions into the device during
operation of the test port. An internal pullup resistor is provided on TDI to ensure JT AG compliance.

T est data output. TDO is used to serially shift test data and test instructions out of the device during
operation of the test port.

T est reset. TRST is used for asynchronous reset of the test-port controller . An internal pullup resistor
is provided to ensure JTAG compliance. If the test port is not used, an external pulldown resistor of
10 kΩ may be used to disable the test-port controller.

T est mode select. TMS is used to control the state of the test-port controller. An internal pullup resistor
is provided on TMS to ensure JTAG compliance.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TNETX3270

I/O

DESCRIPTION

DESCRIPTION

ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Terminal Functions (Continued)

miscellaneous

TERMINAL

NAME NO.

OSCIN
RESET

112 I None Master system clock input (83.33-MHz input clock)
115 I None Reset. RESET is synchronous and, therefore, the system clock must be operational during reset.

power interface

NAME NO.

8, 14, 34, 40, 55, 68, 74, 81, 88, 94, 100,

GND

V

DD(3.3V)

V

DD(2.5V)

128, 134, 141, 148, 154, 160, 175, 188,

12, 72, 109, 122, 132, 163, 169, 192, 229 None

105, 118, 124, 137, 151, 165, 178,

INTERNAL
RESISTOR

TERMINAL

194, 201, 208, 214, 220, 235

4, 17, 31, 45, 58, 64, 77, 91,

184, 197, 211, 225, 238

INTERNAL
RESISTOR

None

None 2.5-V supply voltage. Power for the core.

Ground. GND is the 0-V reference for the device. All GND
terminals must be connected.

3.3-V supply voltage. Power for the input, output, and I/O
terminals.

summary of signal terminals by signal group function

PORT DESCRIPTION

LED 2 1 2
10-Mbit/s port 16 3 48
10-/100-Mbit/s port 19 3 57
DIO 17 1 17
EEPROM interface 2 1 2
DRAM interface 50 1 50
Miscellaneous 2 1 2
JTAG 5 1 5
Serial MII management 3 1 3

Total signals 186

Assigned terminals 186
V

DD(3.3V)

V

DD(2.5V)

GND 25
Total terminals 240

NUMBER OF

SIGNALS

SUMMARY

MULTIPLIER TOTAL

9

20

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DIO register groups

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Table 1. Internal Register and Statistics Memory Map

LOADABLE

REGISTERS

Port configuration Yes Yes 0x0000:0x002F
Spanning tree Yes Yes 0x0030:0x007F
Trunking Yes Yes 0x0080:0x0088
VLAN No Yes 0x0089:0x03FF
Port status No No 0x0400:0x043F
Address configuration No No 0x0440:0x08FF
Port statistics No No 0x0900:0xFFFF

USING 24C02

EEPROM?

LOADABLE

USING 24C08

EEPROM?

DIO

ADDRESS

RANGE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Table 2. Detailed DIO Register Map

BYTE 3 BYTE 2 BYTE 1 BYTE 0

Port1control Port0control 0x0000
Port3control Port2control 0x0004
Port5control Port4control 0x0008
Port7control Port6control 0x000C

Port9control Port8control 0x0010
Port11control Port10control 0x0014
Port13control Port12control 0x0018
Port15control Port14control 0x001C
Port17control Port16control 0x0020
Port19control Port18control 0x0024
Port21control Port20control 0x0028
Port23control Port22control 0x002C
Port25control Port24control 0x0030

Reserved Port26control 0x0034
Reserved Reserved 0x0038:0x003F

Reserved UnkVLANport Mirrorport Uplinkport 0x0040

Reserved Aging threshold 0x0044

Reserved 0x0048:0x004F

Nlearnports 0x0050

Txblockports 0x0054

Rxuniblockports 0x0058

Rxmultiblockports 0x005C

Unkuniports 0x0060

Unkmultiports 0x0064

Unksrcports 0x0068

UnkVLANintports 0x006C

Reserved 0x0070:0x007F
Trunkmap3 T runkmap2 Trunkmap1 Trunkmap0 0x0080
Trunkmap7 Trunkmap6 Trunkmap5 Trunkmap4 0x0084

Reserved Trunkports 0x0088

Reserved 0x008C:0x009F

Devcode Reserved SIO Revision 0x00A0

Reserved 0x00A4:0x00DF

RAMsize Reserved IOBcontrol 0x00E0

Reserved 0x00E4

Pausetime100 Pausetime10 0x00E8

Reserved 0x00EC

Reserved Flowthreshold 0x00F0

Reserved LEDcontrol 0x00F4

Syscontrol Statcontrol 0x00F8

DIO

ADDRESS

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Table 2. Detailed DIO Register Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

Reserved (for EEPROM CRC) 0x00FC

VLAN0ports 0x0100
VLAN1ports 0x0104
VLAN2ports 0x0108
VLAN3ports 0x010C
VLAN4ports 0x0110
VLAN5ports 0x0114
VLAN6ports 0x0118
VLAN7ports 0x011C
VLAN8ports 0x0120

VLAN9ports 0x0124
VLAN10ports 0x0128
VLAN11ports 0x012C
VLAN12ports 0x0130
VLAN13ports 0x0134
VLAN14ports 0x0138
VLAN15ports 0x013C
VLAN16ports 0x0140
VLAN17ports 0x0144
VLAN18ports 0x0148
VLAN19ports 0x014C
VLAN20ports 0x0150
VLAN21ports 0x0154
VLAN22ports 0x0158
VLAN23ports 0x015C
VLAN24ports 0x0160
VLAN25ports 0x0164
VLAN26ports 0x0168
VLAN27ports 0x016C
VLAN28ports 0x0170
VLAN29ports 0x0174
VLAN30ports 0x0178
VLAN31ports 0x017C

Reserved 0x0180:0x02FF
VLAN1QID VLAN0QID 0x0300
VLAN3QID VLAN2QID 0x0304
VLAN5QID VLAN4QID 0x0308
VLAN7QID VLAN6QID 0x030C
VLAN9QID VLAN8QID 0x0310

VLAN11QID VLAN10QID 0x0314
VLAN13QID VLAN12QID 0x0318
VLAN15QID VLAN14QID 0x031C

DIO

ADDRESS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Table 2. Detailed DIO Register Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

VLAN17QID VLAN16QID 0x0320
VLAN19QID VLAN18QID 0x0324
VLAN21QID VLAN20QID 0x0328
VLAN23QID VLAN22QID 0x032C
VLAN25QID VLAN24QID 0x0330
VLAN27QID VLAN26QID 0x0334
VLAN29QID VLAN28QID 0x0338
VLAN31QID VLAN30QID 0x033C

Reserved 0x0340:0x037F
Port1Qtag Port0Qtag 0x0380
Port3Qtag Port2Qtag 0x0384
Port5Qtag Port4Qtag 0x0388
Port7Qtag Port6Qtag 0x038C
Port9Qtag Port8Qtag 0x0390

Port11Qtag Port10Qtag 0x0394
Port13Qtag Port12Qtag 0x0398
Port15Qtag Port14Qtag 0x039C
Port17Qtag Port16Qtag 0x03A0
Port19Qtag Port18Qtag 0x03A4
Port21Qtag Port20Qtag 0x03A8
Port23Qtag Port22Qtag 0x03AC
Port25Qtag Port24Qtag 0x03B0

Reserved Port26Qtag 0x03B4

Reserved 0x03B8:0x03FF

Port1status Port0status 0x0400
Port3status Port2status 0x0404
Port5status Port4status 0x0408
Port7status Port6status 0x040C

Port9status Port8status 0x0410
Port11status Port10status 0x0414
Port13status Port12status 0x0418
Port15status Port14status 0x041C
Port17status Port16status 0x0420
Port19status Port18status 0x0424
Port21status Port20status 0x0428
Port23status Port22status 0x042C
Port25status Port24status 0x0430

Reserved Port26status 0x0434

Reserved 0x0438:0x043F

DIO

ADDRESS

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

Table 2. Detailed DIO Register Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

Findnode<23–16> Findnode<31–24> Findnode<39–32> Findnode<47–40> 0x0440

FindVLAN Findcontrol Findnode<7–0> Findnode<15–8> 0x0444

Findport 0x0448

Newnode<23–16> Newnode<31–24> Newnode<39–32> Newnode<47–40> 0x044C

Reserved Newnode<7–0> Newnode<15–8> 0x0450

NewVLAN Newport 0x0454

Addnode<23–16> Addnode<31–24> Addnode<39–32> Addnode<47–40> 0x0458

AddVLAN Adddelcontrol Addnode<7–0> Addnode<15–8> 0x045C

Addport 0x0460

Agednode<23–16> Agednode<31–24> Agednode<39–32> Agednode<47–40> 0x0464

AgedVLAN Agedport Agednode<7–0> Agednode<15–8> 0x0468

Delnode<23–16> Delnode<31–24> Delnode<39–32> Delnode<47–40> 0x046C

DelVLAN Delport Delnode<7–0> Delnode<15–8> 0x0470

Agingcounter Numnodes 0x0474

Reserved 0x0478:0x07FF

Reserved DMAaddress 0x0800
Reserved Int 0x0804
Reserved Intenable 0x0808

Systest Freestacklength 0x080C

RAMaddress 0x0810

Reserved RAMdata 0x0814

Reserved NMRxcontrol 0x0818
Reserved NMTxcontrol 0x081C

Reserved NMdata 0x0820

Reserved 0x0824:0x3FFF

TNETX3270 reset: reinitializes the TNETX3270 0x4000:0x5FFF

Reserved 0x6000:0x7FFF

Port and network management port statistics 0x8000:8DFF

Reserved 0x8E00:8FFF

TX pause, RX pause, and security-violation counters 0x9000:0x91BF

Reserved 0x91C0:0x9FFF

Unknown unicast destination addresses 0xA000

Unknown multicast destination addresses 0xA004

Unknown source address 0XA008

Reserved 0xA00C:0xFFFF

DIO

ADDRESS

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17

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

interface description

DIO interface

The DIO interface is a general-purpose interface that can be used with a wide range of microprocessor or
computer systems. The interface supports external DMA controllers.

This interface can be used to configure the TNETX3270 using an optional attached CPU (or EEPROM), and
to access statistics registers. In addition, this allows access to an internal network management (NM) port that
can be transferred between the CPU and the TNETX3270 to support spanning tree, SNMP, and RMON. Either
the CPU can read and write packets directly under software control or an external DMA controller can be used
to improve performance.

When accessing the statistics values from the DIO port, it is necessary to perform four 1-byte DIO reads to obtain
the full 32-bit counter. Counters always should be read in ascending byte-address order (0, 1, 2, 3). To prevent
the counter being updated while reading the four bytes, the entire 32-bit counter value is transferred to a holding
register when byte 0 is read.

receiving/transmitting management frames

Frames originating within the host are written to the NM port via the NMRxcontrol and NMdata registers. Once
a frame has been fully written, it is then received by the switch and routed to the destination port(s).

Frames that were routed to this port from any of the switch ports are placed in a queue until the host is ready
to read them via the NMTxcontrol and NMdata registers. They then are effectively transmitted out of the switch.

SDMA

can be used to transmit or receive management frames (the SAD1–SAD0 pins are ignored when SDMA
is asserted) (see Table 3). When SDMA is asserted, the switch uses the value in the DMAaddress register
instead of the DIO address registers to access frame data (this also can be used to access the switch statistics).
STXRDY and SRXRDY, the interrupts, freebuffs, eof, sof, and iof mechanisms can be used, as desired, to
prevent unwanted stalls on the DIO bus during busy periods.

Table 3. DMA Interface Signals

SIGNAL DESCRIPTION

SDMA Automatically sets up DIO address using the DMAaddress register
STXRDY Indicates that at least one data frame buffer can be read by the management CPU
SRXRDY Indicates that the management CPU can write a frame of any size up to 1535 bytes

state of DIO signals during hardware reset

The CPU can perform a hardware reset by writing to an address in the range 0x4000–0x5FFF (writes to a DMA
address in this range have no effect on reset). This is equivalent to asserting the hardware RESET
hardware reset, the output and bidirectional DIO pins behave as shown in Table 4.

Table 4. DIO Interface During Hardware Reset

DIO INTERFACE

SIGNAL

SDATA7–SDATA0 High impedance. Resistively pulled up.
SRDY High impedance. Resistively pulled up.
SRXRDY Driven high
STXRDY Driven low

STATE DURING HARDWARE RESET

pin. During

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

network management port

Frames can be received or transmitted via the DIO interface using a built-in port, the network management (NM)
port.

Frames originating within the host are written to this port via the NMRxcontrol and NMdata registers. Once a
frame has been fully written, it is then received by the switch and routed to the destination port(s).

Frames that were routed to this port from any of the switch’s ports queue until the host is ready to read them
via the NMTxcontrol and NMdata registers. They are then effectively transmitted out of the switch.

IEEE Std 802.1Q VLAN headers on the NM port

Frames received from the host via the NM port are required to contain a valid IEEE Std 802.1Q header. Frames
that do not contain a valid header are incorrectly routed. They may be corrupted at the transmission port(s), as
the header-stripping process does not verify that the four bytes after the source address are actually a valid
header because they always are a valid header under all other circumstances.

When a frame is transmitted to the NM port, no header-stripping occurs, so the frame contains one, or possibly
two headers, depending on how the frame was originally received.

full-duplex NM port

The NM port can intermix reception and transmission as desired. The direction of the NMdata access (i.e., read
or write) determines whether a byte is removed from the transmit queue or added to the receive queue. The
DIO interface is half duplex since it can do only a read or write at one time.

NM bandwidth and priority

The NM port is capable of transferring a byte to or from NMdata once every five cycles, so the burst rate of this
port approximates eight bits per 60 ns (or ≈133 Mbit/s). This can be sustained between the DIO port and the
NM port’s dedicated transmit or receive buffers.

However, the NM port is prioritized lower than the other ports between its receive and transmit buf fers and the
external memory system so that at periods of high activity , the NM port does not cause frames to be dropped
on the other ports. STXRDY and SRXRDY, the interrupts and freebuffs, EOF , SOF, and interior-of-frame (IOF)
mechanisms can be used as desired to prevent unwanted stalls on the DIO bus during busy periods.

The burst rate is unaffected by traffic on other ports.

interrupt processing

There are two interrupts available on the NM port.
The interrupt process uses RXRDY and the nmrx interrupts to indicate when the receive FIFO is empty. This

indicates that the NM port is ready to accept a frame of any length (up to 1536 bytes).
If the host needs to download a sequence of frames, it can use the freebuffs field to indicate space availability .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

frame format on the NM port

The frame format on the NM port differs slightly from a standard Ethernet frame format. The key differences are:
the frame always contains an IEEE Std 802.1Q header in the four bytes following the source address (see
Figure 2). The TPID (tag protocol identifier or ethertype) field, however , is used in the switch for other purposes,
so a frame transmitted out of the switch on the NM port does not have the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) value in these two bytes.

The first TPID byte output contains:

D

The frame source port number in the least significant bits. This allows the frame source port number to be
carried within the frame, which is useful for processing BPDUs, for example.

D

A cyclic redundancy check (CRC) type indicator (crctype) in the most significant bit (bit 7).

• If crctype = 1, then the CRC word in the frame excludes the IEEE Std 802.1Q header.

• If crctype = 0, then the CRC word in the frame includes the IEEE Std 802.1Q header. This CRC word is

for a regular IEEE Std 802.1Q frame format with the value in the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) in the TPID field. Because the internal frame format uses the TPID field for other
purposes in the manner being described, it is necessary to insert the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) value into the TPID field if the frame needs to be restored to a normal
IEEE Std 802.1Q frame format, which passes a CRC check.

T o provide a CRC word, which includes the header , the NM port generates a new CRC word as the frame is
being read out. It simultaneously checks the existing CRC in the frame and, if an error is found, ensures that
the final byte of the newly generated CRC is corrupted to contain an error, too. The CRC word is deliberately
corrupted if the header parity protection (described in the following) indicates an error in the header. In either
case, the pfe bit also is set to 1 after the final byte of the frame has been read from NMdata.

If the frame was received on a port other than the NM port, then the crctype bit is set if an IEEE Std 802.1Q
tag header was inserted into the frame during ingress.

• If crctype = 1, a header was inserted.

• If crctype = 0, a header was not inserted (crctype also is 0 if the frame VLAN ID was 0x000 and was

replaced by the port VLANID (PVID) from the PortxQtag register).

In an IEEE Std 802.1D-compliant application, the header simply can be removed from the frame to produce
a headerless frame with a correct CRC word.

• All other bits in the byte are reserved and are 0.

The second TPID byte output contains:

D

Odd-parity protection bits for the other three bytes in the tag header

D

Bit 5 protects the first byte of the TPID field (i.e., the one containing crctype and source port number).

D

Bit 6 protects the first byte of the VLAN ID field.

D

Bit 7 protects the second byte of the VLAN ID field.

D

All other bits in the byte are reserved and are 0.

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