Texas Instruments TNETE2201BPJD, TNETE2201BPHD Datasheet

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

D

1.25 Gigabits Per Second (Gbps) Gigabit
Ethernet Transceiver

D

Based on the P802.3Z Specification

D

Transmits Serial Data up to 1.25 Gbps

D

Operates With 3.3-V Supply Voltage

D

5-V Tolerant on TTL Inputs

description

The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data
transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by
the P802.3z Gigabit Task Force.

PHD OR PJD PACKAGE

(TOP VIEW)

D

Interfaces to Electrical Cables/Backplane or
Optical Modules

D

PECL Voltage Differential Signaling Load,
1 V Typ With 50 Ω – 75 Ω

D

Receiver Differential Input Voltage
200 mV Minimum

D

Low Power Consumption

D

64-Pin Quad Flat Pack With Thermally
Enhanced Package

GND_CMOS

TD0
TD1
TD2

V

_CMOS

CC

TD3
TD4
TD5
TD6

V

_CMOS

CC

TD7
TD8
TD9

GND_CMOS

GND_TX

TC1

_A

CC

GND_A

DOUT_TXP

V

63 62 61 60 5964 58

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1718 19

TC0

20

_TX

CC

V

LOOPEN

_A

_A

CC

CC

DOUT_TXN

21 22 23 24

V

V

GND_CMOS

_A

CC

V

GND_A

_CMOS

REFCLK

CC

V

_A

_A

CC

CC

V

56 55 5457

25 26 27 28 29

SYNCEN

DIN_RXP

GND_A

V

53 52

LCKREFN

RESERVED

GND_CMOS

_A

CC

DIN_RXN

V

51 50 49

30 31 32

_A

_A

CC

CC

V

V

_RX

CC

V

GND_RX

RC1

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RBC1

RBC0

GND_A

RC0
SYNC
GND_TTL
RD0
RD1
RD2
V

_TTL

CC

RD3
RD4
RD5
RD6
V

_TTL

CC

RD7
RD8
RD9
GND_TTL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  1999, Texas Instruments Incorporated

1

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

description (continued)

The intended application of this device is to provide building blocks for developing point-to-point baseband data
transmission over controlled-impedance media of approximately 50 Ω to 75 Ω. The transmission media can be
printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.

The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit
ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps
of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero
(NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input
serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output
with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in
RBC clock rising edges.

The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver
can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.

The TNETE2201B provides an internal loopback capability for self-test purposes. Serial data from the serializer
is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TNETE2201B is characterized for operation from 0°C to 70°C.

2

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functional block diagram

LOOPEN

10

TD0 – TD9

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

TX+
TX–

/

10-Bit

Register

10

/

Shift

Register

REFCLK

SYNCEN

SYNC

RD0 – RD9

RBC0

RBC1

10

/

62.5 MHz

62.5 MHz

125 MHz

÷ 2

10-Bit

Register

125 MHz

10

/

Clock

Multiplier

Synchronous

Detect

Shift

Register

PLL Clock

Recovery and

Data Retiming

2:1

MUX

RX+
RX–

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3

TNETE2201B

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

I/O structures

PECL inputs (DIN_RXP, DIN_RXN) PECL outputs (DIN_TXP, DIN_TXN)

V

DD

DIN_RXP

V

DD

100 Ω

4 kΩ

+
_

DIN_RXN

V

V

DD

CM

4 kΩ

CMOS inputs (TD0 – TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)

V

DD

P

N

TERMINALS
REFCLK, TD0 – TD9
LOOPEN
SYNCEN, LCKREFN

Input

120 Ω

V

DD

R1

R2

CMOS outputs (RD0 – RD9, RBC0, RBC1, SYNC)

V

DD

V

DD

Open Circuit
Open Circuit

R1 R2

Open Circuit

400 kΩ

Open Circuit

DOUT_TXP

DOUT_TXN

400 kΩ

P

Output

N

4

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TNETE2201B

DESCRIPTION

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

Terminal Functions

TERMINAL

NAME NO. TYPE

I/O and DATA

DOUT_TXP
DOUT_TXN

DIN_RXP
DIN_RXN

LCKREFN 27 Input Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied

LOOPEN 19 Input Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The

RBC0
RBC1

RC1,
RC0

RD0 – RD9 45,44,43,41

REFCLK 22 Input Reference clock. REFCLK is an external 125 MHz input clock that synchronizes the receiver and

SYNC 47 Output Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data

SYNCEN 24 Input Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function

TC1
TC0

TD0 – TD9 2,3,4,6

NOTE 1: A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due

to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage
supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power
supply noise.

62
61

54
52

31
30

49
48

40,39,38,36

35,34

16
17

7,8,9,1 1

12,13

Output Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface

to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.25 Gbps.
DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is
low.

Input Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface

from a copper or an optical I/F module. These terminals receive NRZ data at a rate of 1.25 Gbps and
are active when LOOPEN is held low.

REFCLK signal. LCKREFN prelocks or resets the receive PLL.

transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held
static during the loop-back test. LOOPEN is held low during standard operational state with external
serial outputs and inputs active.

Output Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for synchronizing the

10-bit output data on RD0 – RD9. The 10-bit output data words are valid on the rising edges of RBC0
and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.

Analog Receive capacitor. RC0 and RC1 are external capacitor connections used for the receiver internal

PLL filter. The recommend value for this external capacitor is 2 nF (a value of 0.1 µF can also be used,
see Note 1).

Output Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol

layer. The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the
K28.5 character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.

transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for
serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.

path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is
activated (asserted high). Note: SYNC is active on byte0 and, therefore, active on rising edge of
RCB1.

is activated. When this function is enabled, the transceiver detects the K28.5 character (0011 1 1 1010
negative beginning disparity) in the serial data stream and realigns data on byte boundaries if
required. When SYNCEN is low, serial input data is unframed in RD0 – RD9.

Analog T ransmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal

PLL filter. The recommended value of this external capacitor is 2 nF (a value of 0.1 µF can also be
used, see Note 1).

Input Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver

for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising
edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

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5

TNETE2201B

DESCRIPTION

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS367A – JUNE 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME NO. TYPE

POWER

VCC_A 20,28,29,53

55,57,59,60

63

VCC_CMOS 5,10,23, Supply Digital PECL logic power. VCC_CMOS provides an isolated low-noise power supply for the logic

VCC_RX 50 Supply Receiver power . VCC_RX provides a low-noise supply reference voltage for the receiver high-speed

VCC_TTL 42,37 Supply TTL power. VCC_TTL provides a supply reference voltage for the receiver TTL circuits.
VCC_TX 18 Supply Transmitter power. VCC_TX provides a low-noise supply reference voltage for the transmitter

GND_A 21,32,56,64 Ground Analog ground. GND_A provides a ground reference for the high-speed analog circuits.
GND_CMOS 1,14,

25,58
GND_RX 51 Ground Receiver ground. GND_RX provides a ground reference for the receiver circuits.
GND_TTL 33,46 Ground TTL circuit ground. GND_TTL provides a ground for TTL interface circuits.
GND_TX 15 Ground Transmitter ground. GND_TX provides a ground reference for the transmitter circuits.

RESERVED 26 Reserved. Internally pulled to GND, leave open or assert low.

Supply Analog power. VCC_A provides a supply reference voltage for the high-speed analog circuits.

circuits.

analog circuits.

high-speed analog circuits.

GROUND

Ground Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits.

MISCELLANEOUS

detailed description

data transmission

The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0...TD9) on the rising edge
of REFCLK (125 MHz). The reference clock is also used by the serializer, which multiplies the clock by a factor
of 10 providing a 1.25 Gbaud signal that is fed to the shift register. The data is then transmitted dif ferentially at
PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9.

transmission latency

The data transmission latency of the TNETE2201B is defined as the delay from the initial 10-bit word load to
the serial transmission of bit 9. The typical transmission latency is 9 ns.

data reception

The receiver of the TNETE2201B deserializes 1.25 Gbps differential serial data. The 8b/10b data (or equivalent)
is retimed based on an extracted clock from the serial data. The serial data is then aligned to the 10-bit word
boundaries and presented to the protocol controller along with two receive byte clocks (RBC0, RBC1). RBC0
and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered 1.25 Gbps
(625 MHz) clock by 10 providing for two 62.5-MHz signals. The receiver presents the protocol device byte 0 of
the received data valid on the rising edge of RBC1.

NOTE:

This allows the option of byte alignment without the use of the synchronous detection

(SYNC) function by the protocol device.

The receiver PLL can lock to the incoming 1.25 GHz data without the need for a lock-to-reference preset. The
received serial data rate (RX+ and RX–) should be 1.25 Gbps ±0.01% (100 ppm) for proper operation.

6

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