Texas Instruments TNETE2201 User Manual
Application Report
SLLA032
TNETE2201 EVM Kit Setup and Usage
Boyd Barrie MSDS Applications Group
Abstract
The Texas Instruments (TIä) TNETE2201 EVM (evaluation module) k it is a tool used to
evaluate and design high-speed prototypes using the TNETE2201 Ethernet Transceiver
IC (10 mm x 10 mm TQFP plastic package). The EVM kit is used to evaluate device
parameters while acting as a guide for high-speed board layout. The high-speed
interface is selectable between a 50-W SMA connector and a GBIC standard interface.
The GBIC standard also provides a 75-W copper interface module and various fiber optic
options. Overall, the designer can use the EVM kit as a tool for successful evaluation
and design of an end product.
Contents
Introduction......................................................................................................................................................2
Board Layout and Configuration......................................................................................................................3
Test Configuration and Results........................................................................................................................4
Board Layouts, Schematics, and Bill of Materials............................................................................................6
Digital Signal Processing Solutions March 1999
Application Report
SLLA032
Figures
Figure 1. GBIC Setup Modifications................................................................................................................4
Figure 2. Bit Error-Rate Ratio Test Configuration ...........................................................................................5
Figure 3. Eye Diagrams of High-Speed Serial Outputs...................................................................................5
Figure 4. TNETE2201 EVM Board Schematic................................................................................................7
Figure 5. TNETE2201 EVM Board Top Layer.................................................................................................9
Figure 6. TNETE2201 EVM Board GND Layer.............................................................................................10
Figure 7. TNETE2201 EVM Board VCC Layer.............................................................................................11
Figure 8. TNETE2201 EVM Board Bottom Layer..........................................................................................12
Tables
Table 1. Default Setup as Shipped..................................................................................................................3
Table 2. TNETE2201 EVM Board Bill of Materials..........................................................................................8
Introduction
The TNETE2201 EVM kit can act as a daughter board that plugs into new or existing
designs. By providing the appropriate cabling, the EVM kit can interface with just about
any test equipment or other reference designs. The EVM kit's high-speed serial interface
can use either the GBIC (Gigabit Interface Converter) standard interface or a 50-ohm
SMA connection. In addition, the GBIC specification allows the designer to choose either
a 75-ohm copper module or a selection of fiber-optics modules.
As the frequency of operation increases, the board designer must take special care to
ensure that the highest signal integrity is maintained. To achieve this, the board’s
impedance is controlled for both 50-ohm and 75-ohm high-speed transmission lines. In
addition, the 50-ohm impedance mismatches are reduced by designing the component
pad size to be as close as possible to the width of the connecting transmission line. Vias
are minimized and, when necessary, placed as close as possible to the device drivers.
Overall, the board layout is designed and optimized to support high-speed operation.
Thus, understanding impedance control and transmission line effects are crucial when
designing high-speed boards.
Some of the advanced features offered by the EVM kit include:
r
PCB (printed circuit board) designed for speeds in excess of 1.25 Gbps
r
Flexible—The EVM can be configured to operate with multiple device types and with
copper or fiber interfaces.
r
Integrated GBIC Interface eliminates the need for two boards.
r
All input/output signals are accessible for rapid prototyping.
r
Clock input is selectable for either 8/14 pin crystal or external clock input.
r
Power can be supplied either by banana jacks or a 20-pin connector.
r
Series terminated parallel outputs
TNETE2201 EVM Kit Setup and Usage 2
Application Report
SLLA032
Board Layout and Configurat ion
The TNETE2201 EVM kit is designed to give the developer many options for operation.
Many of these options are selectable by DIP switch and others may require board
component removal or additions. The following sections provide guidelines to config ure
the EVM kit for different modes of operation.
The EVM kit is normally delivered in a default configuration that requires external clock
and data inputs. The high-speed serial input and output are routed through the 50-ohm
transmission line path. The GBIC interface is not connected and would require some
resistor modifications to be functional. The default setup is useful for testing the board
and interface IC. The designer might consider testing the bit error rate, jitter, and eyediagram characteristics of the system. The TNETE2201 EVM is shipped with certain
components installed for default operation. Table 1 lists the default configuration.
Table 1. Default Setup as Shipped
Designator Function Condition (TNETE2201)
P5 CLK SEL Jumper installed between Pins 2 and 3
R1 TX Termination 200 ohm installed
R2 TX Termination 200 ohm installed
R5 Bias Net 365 ohm installed
R6 Bias Net 562 ohm installed
R8 WIZ OPTIO N Not installed
R9 WIZ OPTIO N Not installed
R16 CAP OPTION Zero ohm installed
R17 Bias Net Not installed
R21 WIZ OPTIO N Not installed
R22 WIZ OPTIO N Not installed
C13 Vcc Decouple 0.01 µF installed
C23 GBIC OPTION Not installed
C24 SMA OPTION 0.01 µF installed
C25 GBIC OPTION Not installed
C26 SMA OPTION 0.01 µF installed
C27 SMA OPTION 0.01 µF installed
C28 GBIC OPTION Not installed
C29 GBIC OPTION Not installed
C30 SMA OPTION 0.01 µF installed
C31 RX Termination 0.01 µF installed
C32 TX PLL Cap 0.0022 µF installed
C33 REF CLK Bias Net Zero 0hm installed
C34 TX PLL Cap 0.0022 µF installed
L1 Filter/Bias Ferrite installed
X1 OSC Not installed (not provided)
DIP1-1 PRBSEN X (OFF)
DIP1-2 TXRRAMP X (OFF)
DIP1-3 TXDIR X (OFF)
TNETE2201 EVM Kit Setup and Usage 3
Application Report
SLLA032
Designator Function Condition (TNETE2201)
DIP1-4 LCKREFN X (OFF)
DIP1-5 TESTEN ON
DIP1-6 SYNCEN X (OFF)
DIP1-7 LOOPEN ON
DIP1-8 CLKEN X (OFF)
Note: X is a don't care state (default posi ti on).
The GBIC Configuration requires a modification of the steering capacitors C23 through
C30. This requires removing C24, C26, C27, and C30 and soldering these capacitors in
locations C23, C25, C28, and C29 (see Figure 1).
Figure 1. GBIC Setup Modifications
GBIC
INSTALLED
CAPACITORS
Test Configuration and Results
The serial Bit Error-rate Ratio Test (BERT) is useful for evaluating device and board
characteristics. Using this test, we can determine the eye diagram characteristics of the
system, as shown in Figure 3. The test setup is illustrated in Figure 2.
The HP71603B 3-Gbps Serial BERT outputs a high-speed serial stream to the test board
where the data is converted by the TNETE part to a 10-bit parallel format. The parallel
data is then looped back from the receiver to the transmitter. The pulse generator
provides a clock input to the transmitter. The external clock source is necessary because
the receiver's recovered clock is half the frequency necessary for transmission.
TNETE2201 EVM Kit Setup and Usage 4
Application Report
SLLA032
Both the pulse generator and the BERT are synchronized with an external clock source.
The operator adjusts the variable phase delay to ensure that the clock meets the setup
and hold time of the data. The parallel data along with the clock is routed to the
transmitter where the data is serialized and captured by the oscilloscope. Figure 3 shows
an example eye diagram taken using this technique.
Figure 2. Bit Error-Rate Ratio Test Configuration
Wizard
(With parallel
ports looped)
RX-
RX+
External Clock
For Sync
Data In
Sync
HP71603B
BERT
Data Out
Data Out
Sync
(Variable Delay)
36”
36”
HP8133A
Pulse Generator
Clk Out
Figure 3. Eye Diagrams of High-Speed Serial Outputs
TX+
TX-
36”
REFCLK
HP54750A
Digital O’Scope
36”
Channel 1
TNETE2201 EVM Kit Setup and Usage 5
Loading...