Texas Instruments TNETE211, TNETE110A, TNETE100A User Manual
ThunderLAN
TNETE100A, TNETE110A, TNETE211
Programmer’s
Guide
October 1996 Network Business Products
Printed in U.S.A., October 1996
L411001–9761 revisionA
SPWU013A
ThunderLAN
t
Programmer’s Guide
TNETE100A, TNETE1 10A, TNETE211
Manufacturing Part Number: L411001-9761 revision A
Literature Number: SPWU013A
October 1996
Running Title—Attribute Reference
T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify , before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI’s standard warranty . T esting and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury , or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
IMPORTANT NOTICE
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer .
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright 1996, Texas Instruments Incorporated
ii
About This Manual
The
implementations of ThunderLAN networking hardware:
-
-
-
How to Use This Manual
The goal of this book is to assist you in the development of drivers for the
ThunderLAN controllers. This document contains the following chapters:
-
Preface
Read This First
ThunderLAN Programmer’s Guide
TNETE100A Ethernett controller
TNETE110A Ethernet controller
TNETE211 100 VG-AnyLAN physical media interface (PMI)
Chapter 1, ThunderLAN Overview, describes some Texas
Instruments-specific hardware features. These include the enhanced
media independent interface (MII), which passes interrupts from an
attached physical interface (PHY) to the host.
assists you in using the following
-
Chapter 2, ThunderLAN Registers, shows how to access the various
ThunderLAN registers and how to use these registers to access external
devices attached to ThunderLAN.
-
Chapter 3, Initializing and Resetting, discusses how to initialize and reset
the controller and the attached PHYs.
-
Chapter 4, Interrupt Handling, describes what happens when interrupts
occur and how to correct failure conditions.
-
Chapter 5, List Structures, describes how to pass data to ThunderLAN
using a system of linked list structures.
-
Chapter 6, Transmitting and Receiving Frames, explains the format and
procedure for transmitting and receiving, as well as the linked list structure
required.
-
Chapter 7, Physical Interface, discusses the features of ThunderLAN
which support IEEE 802.3- and 802.12-compliant devices.
iii
Notational Conventions
Notational Conventions
This document uses the following conventions:
-
-
Related Documentation
Information Technology Local and Metropolitan Area Networks–Part 12:
MAC Parameters, Physical Layer, Medium Attachment Units and
PCI Local Bus Specification, Revision 2.0
ThunderLAN Adaptive Performance Optimization Technical Brief
XL24C02 Data Sheet,
Program listings, program examples, and interactive displays are shown
in a special font. Examples use a bold version of the special font for
emphasis. Here is a sample program listing:
11 0005 0001 .field 1, 2
12 0005 0003 .field 3, 4
13 0005 0006 .field 6, 3
14 0006 .even
A lower case ‘x’ in a number indicates that position can be anything (don’t
care). Here are some examples:
J
0x00
J
0x0004
J
0x4000501
Demand-Priority Access Method, Physical Layer and Repeater
Specifications for 100-Mb/s Operation,
Draft 8.0 of the Revision
Marked for Technical changes of IEEE Standard 802.12.
Repeater for 100-Mb/s Operation,
Draft 5.0 of the Supplement to 1993
version of ANSI/IEEE Std. 802.3: Carrier Sense Multiple Access with
Collision Detection (CSMA/CD) Access Method & Physical Layer
Specifications.
is the specification which
ThunderLAN is designed to meet. T o obtain copies, contact PCI Special
Interest Group, P .O. Box 14070, Portland, OR 97214, 1–800–433–5177.
(Texas
Instruments literature number SPWT089) discusses specific buffering
and pacing techniques for improving adapter performance by adjusting
the resources and transmit procedures to achieve optimal transmission
rate and minimal CPU use.
EXEL Microelectronics, 1993, which contains the
device specifications for the XL24C02 2M-bit electrically erasable
EPROM.
iv
If Y ou Need Assistance / Trademarks
If You Need Assistance. . .
-
World-Wide Web Sites
TI Online http://www.ti.com
Semiconductor PIC http://www.ti.com/sc/docs/pic/home.htm
Networking Home Page http://www.ti.com/sc/docs/network/nbuhomex.htm
-
North America, South America, Central America
Product Information Center (PIC) (972) 644-5580
TI Literature Response Center U.S.A. (800) 477-8924
Software Registration/Upgrades (214) 638-0333 Fax: (214) 638-7742
U.S.A. Factory Repair/Hardware Upgrades (713) 274-2285
U.S. Technical Training Organization (972) 644-5580
Networking Hotline Fax: (713) 274-4027
-
Europe, Middle East, Africa
European Product Information Center (EPIC) Hotlines:
Multi-Language Support +33 1 30 70 11 69 Fax: +33 1 30 70 10 32 Email: epic@ti.com
Deutsch +49 8161 80 33 11 or +33 1 30 70 11 68
English +33 1 30 70 11 65
Francais +33 1 30 70 11 64
Italiano +33 1 30 70 11 67
EPIC Modem BBS +33 1 30 70 11 99
European Factory Repair +33 1 93 22 25 40
Europe Customer Training Helpline Fax: +49 81 61 80 40 10
-
Asia-Pacific
Literature Response Center +852 2 956 7288 Fax: +852 2 956 2200
-
Japan
Product Information Center +0120-81-0026 (in Japan) Fax: +0120-81-0036 (in Japan)
+03-3457-0972 or (INTL) 813-3457-0972 Fax: +03-3457-1259 or (INTL) 813-3457-1259
-
Documentation
When making suggestions or reporting errors in documentation, please include the following information that is on the title
page: the full title of the book, the publication date, and the literature number.
Mail: Texas Instruments Incorporated Email: comments@books.sc.ti.com
Technical Documentation Services, MS 702
P.O. Box 1443
Houston, Texas 77251-1443
Note: When ordering documentation from a Literature Response Center, please specify the literature number of the
book.
Email:TLANHOT@micro.ti.com
Read This First
v
Trademarks
Trademarks
Ethernet is a trademark of Xerox Corporation.
ThunderLAN and Adaptive Performance Optimization are trademarks of Texas Instruments
Incorporated.
vi
Contents
Contents
1 ThunderLAN Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 ThunderLAN Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Networking Protocols 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 PCI Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 PCI Cycles 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Byte Ordering 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ThunderLAN Registers 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Register Addresses 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 PCI Configuration Space 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Host Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Internal Registers 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 MII PHY Registers 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 External Devices 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 BIOS ROM 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 LEDs 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 EEPROM 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4 ThunderLAN EEPROM Map 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Initializing and Resetting 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Initializing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Finding the Network Interface Card (NIC) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Finding the Controller in Memory and I/O Space 3-4. . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Finding Which Interrupt was Assigned 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Turning on the I/O Port and Memory Address Decode 3-6. . . . . . . . . . . . . . . . . . . .
3.1.5 Recovering the Silicon Revision Value 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6 Setting the PCI Bus Latency Timer 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Resetting 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Hardware Reset 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Software Reset 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Interrupt Handling 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Loading and Unloading an Interrupt Service Routine (ISR) 4-2. . . . . . . . . . . . . . . . . . . . . . .
4.2 Prioritizing Adapter Interrupts 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Acknowledging Interrupts (Acking) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Interrupt Type Codes 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
Contents
4.4.1 No Interrupt (Invalid Code). Int_type = 000b 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Tx EOF Interrupt. Int_type = 001b 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Statistics Overflow Interrupt. Int_type = 010b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Rx EOF Interrupt. Int_type = 011b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Dummy Interrupt. Int_type = 100b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Tx EOC Interrupt. Int_type = 101b 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.7 Network Status Interrupt. Int_type = 110b and Int_Vec = 00h 4-9. . . . . . . . . . . . . .
4.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec
≠ 00h 4-10. . . . . . . . . . . . .
4.4.9 Rx EOC Interrupt. Int_type = 111b 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 List Structures 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 List Management 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 CSTAT Field Bit Requirements 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 One-Fragment Mode 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Receive List Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Transmit List Format 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Transmitting and Receiving Frames 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Frame Format 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Receive (Rx) Frame Format 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Transmit (Tx) Frame Format 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 GO Command 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Starting Frame Reception (Rx GO Command) 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Starting Frame Transmission (Tx GO Command) 6-6. . . . . . . . . . . . . . . . . . . . . . . .
7 Physical Interface (PHY) 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 MII-Enhanced Interrupt Event Feature 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Nonmanaged MII Devices 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Bit-Rate Devices 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PHY Initialization 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Register Definitions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 PCI Configuration Registers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.1 PCI Autoconfiguration from External 24C02 Serial EEPROM A-3. . . . . . . . . . . . . .
A.1.2 PCI Vendor ID Register (@ 00h) Default = 104Ch A-4. . . . . . . . . . . . . . . . . . . . . . .
A.1.3 PCI Device ID Register (@ 02h) Default = 0500h A-4. . . . . . . . . . . . . . . . . . . . . . . .
A.1.4 PCI Command Register (@ 04h) A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.5 PCI Status Register (@ 06h) A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.6 PCI Base Class Register (@ 0Bh) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.7 PCI Subclass Register (@ 0Ah) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.8 PCI Program Interface Register (@ 09h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.9 PCI Revision Register (@ 08h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.10 PCI Cache Line Size Register (@ 0Ch) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.11 PCI Latency Timer Register (@ 0Dh) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.12 PCI I/O Base Address Register (@ 10h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Contents
A.1.13 PCI Memory Base Address Register (@ 14h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.14 PCI BIOS ROM Base Address Register (@ 30h) A-8. . . . . . . . . . . . . . . . . . . . . . . .
A.1.15 PCI NVRAM Register (@ 34h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.16 PCI Interrupt Line Register (@ 3Ch) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.17 PCI Interrupt Pin Register (@ 3Dh) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers A-10. . . . . . . . . . . . . . . . . .
A.1.19 PCI Reset Control Register (@ 40h) A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.20 CardBus CIS Pointer (@ 28h) A-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Adapter Host Registers A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.1 Host Command Register–HOST_CMD @ Base_Address + 0 (Host) A-12. . . . . .
A.2.2 Channel Parameter Register–CH_PARM @ Base_Address + 4 (Host) A-17. . . .
A.2.3 Host Interrupt Register–HOST_INT @ Base_Address + 10 (Host) A-18. . . . . . . .
A.2.4 DIO Address Register–DIO_ADR @ Base_Address + 8 (Host) A-19. . . . . . . . . . .
RAM Addressing A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.5 DIO Data Register–DIO_DATA @ Base_Address + 12 (Host) A-20. . . . . . . . . . . .
A.3 Adapter Internal Registers A-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3.1 Network Command Register–NetCmd @ 0x00 (DIO) A-23. . . . . . . . . . . . . . . . . . .
A.3.2 Network Serial I/O Register–NetSio @ 0x00 (DIO) A-24. . . . . . . . . . . . . . . . . . . . .
A.3.3 Network Status Register–NetSts @ 0x00 (DIO) A-25. . . . . . . . . . . . . . . . . . . . . . . .
A.3.4 Network Status Mask Register–NetMask @ 0x00 (DIO) A-26. . . . . . . . . . . . . . . . .
A.3.5 Network Configuration Register–NetConfig @ 0x04 (DIO) A-27. . . . . . . . . . . . . . .
A.3.6 Manufacturing Test Register–ManTest @ 0x04 (DIO) A-29. . . . . . . . . . . . . . . . . . .
A.3.7 Default PCI Parameter Registers–@ 0x08–0x0C (DIO) A-29. . . . . . . . . . . . . . . . .
A.3.8 General Address Registers–Areg_0-3 @ 0x10–0x24 (DIO) A-30. . . . . . . . . . . . . .
A.3.9 Hash Address Registers–HASH1/HASH2 @ 0x28–0x2C (DIO) A-31. . . . . . . . . .
A.3.10 Network Statistics Registers–@ 0x30–0x40 (DIO) A-32. . . . . . . . . . . . . . . . . . . . . .
A.3.11 Adapter Commit Register–Acommit @ 0x40 (DIO) (Byte 3) A-34. . . . . . . . . . . . . .
A.3.12 LED Register–LEDreg @ 0x44 (DIO) (Byte 0) A-35. . . . . . . . . . . . . . . . . . . . . . . . .
A.3.13 Burst Size Register–BSIZEreg @ 0x44 (DIO) (Byte 1) A-36. . . . . . . . . . . . . . . . . .
A.3.14 Maximum Rx Frame Size Register–MaxRx @ 0x44 (DIO) (Bytes 2+3) A-37. . .
A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) A-38. . . . . . . . . . . . .
A.4 10Base-T PHY Registers A-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4.1 PHY Generic Control Register–GEN_ctl @ 0x0 A-40. . . . . . . . . . . . . . . . . . . . . . . .
A.4.2 PHY Generic Status Register–GEN_sts @ 0x1 A-42. . . . . . . . . . . . . . . . . . . . . . . .
A.4.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 A-44. . . . . . . . . . . . . . .
A.4.4 Autonegotiation Advertisement Register–AN_adv @ 0x4 A-45. . . . . . . . . . . . . . . .
A.4.5 Autonegotiation Link Partner Ability Register–AN_lpa @ 0x5 A-46. . . . . . . . . . . . .
A.4.6 Autonegotiation Expansion Register–AN_exp @ 0x6 A-47. . . . . . . . . . . . . . . . . . .
A.4.7 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 A-48. . . . . . . . . . . . . . .
A.4.8 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11 A-49. . . . . . . . . . . . . . . . .
A.4.9 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 A-50. . . . . . . . . . . . . . . . .
Contents
ix
Contents
B TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B-1
B.1 100VG-AnyLAN Training B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 TNETE211 Register Descriptions B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2.1 PHY Generic Control Register–GEN_ctl @ 0x0 B-7. . . . . . . . . . . . . . . . . . . . . . . . .
B.2.2 PHY Generic Status Register –GEN_sts @ 0x1 B-8. . . . . . . . . . . . . . . . . . . . . . . . .
B.2.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 B-9. . . . . . . . . . . . . . . .
B.2.4 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 B-9. . . . . . . . . . . . . . . .
B.2.5 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11 B-9. . . . . . . . . . . . . . . . . .
B.2.6 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 B-11. . . . . . . . . . . . . . . . .
C TNETE100PM/TNETE1 10PM C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
Figures
Figures
1–1 The ThunderLAN Controller 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 PCI Bus Byte Assignment 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 How ThunderLAN Registers are Addressed 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 The PCI Configuration Space Registers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Configuration EEPROM Data Format 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Host Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Internal Registers 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 MII PHY Registers 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Adapter Check Interrupt Fields 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 List Pointers and Buffers 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Linked List Management Technique 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Receive List Format – One_Frag = 0 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Receive List Format – One_Frag = 1 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Receive CSTAT Request Fields 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Receive CSTAT Complete Fields 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Transmit List Format 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Transmit CSTAT Request Fields 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Transmit CSTAT Complete Fields 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Token Ring Logical Frame Format (Rx) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Ethernet Logical Frame Format (Rx) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Token Ring Logical Frame Format (Tx) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Ethernet Logical Frame Format (Tx) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 100VG-AnyLAN Support Through ThunderLAN’s Enhanced 802.3u MII 7-2. . . . . . . . . . . . . .
7–2 MII Frame Format: Read 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 MII Frame Format: Write 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Assertion of Interrupt Waveform on the MDIO Line 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 Waveform Showing Interrupt Between MII Frames 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 PCI Configuration Register Address Map A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Configuration EEPROM Data Format A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Host Interface Address Map A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 ADAPTER Internal Register Map A-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Default PCI Parameter Register A-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 Ethernet Error Counters A-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 Demand Priority Error Counters A-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 10Base-T PHY Registers A-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 802.12 Training Frame Format B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 Training Flowchart B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–3 TNETE211 Registers B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
xi
Tables
Tables
2–1 ThunderLAN EEPROM Map 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Adapter Check Bit Definitions 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Adapter Check Failure Codes 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Relevance of Error Status Bits for Adapter Check Failure Codes 4-13. . . . . . . . . . . . . . . . . . .
5–1 Receive Parameter List Fields 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Receive CSTAT Request Bits 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Receive CSTAT Complete Bits 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Transmit Parameter List Fields 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Transmit CSTAT Request Bits 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Transmit CSTAT Complete Bits 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 ThunderLAN MII Pins (100M-bps CSMA/CD) 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Possible Sources of MII Event Interrupts 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 PCI Command Register Bits A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 PCI Status Register Bits A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 PCI NVRAM Register Bits A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 PCI Reset Control Register Bits A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Host_CMD Register Bits A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 HOST_INT Register Bits A-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 DIO_ADR Register Bits A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 Network Command Register Bits A-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 Network Serial I/O Register Bits A-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–10 Network Status Register Bits A-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–11 Network Status Mask Register Bits A-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–12 Network Configuration Register Bits A-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13 MAC Protocol Selection Codes A-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14 Ethernet Error Counters A-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–15 Demand Priority Error Counters A-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–16 Adapter Commit Register Bits A-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–17 Burst Size Register Bits A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–18 Demand Priority Error Counters A-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–19 PHY Generic Control Register Bits A-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–20 PHY Generic Status Register Bits A-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–21 Autonegotiation Advertisement Register Bits A-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–22 Autonegotiation Link Partner Ability Register Bits A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–23 Autonegotiation Expansion Register Bits A-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–24 ThunderLAN PHY Control Register Bits A-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Tables
A–25 ThunderLAN PHY Status Register Bits A-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 PHY Generic Control Register Bits B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 PHY Generic Status Register Bits B-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–3 ThunderLAN PHY Control Register Bits B-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–4 ThunderLAN PHY Status Register Bits B-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
xiii
xiv
Running Title—Attribute Reference
Chapter 1
ThunderLAN Overview
The ThunderLAN family consists of highly integrated, single-chip networking
hardware. It uses a high-speed architecture that provides a complete peripheral component interconnect (PCI)- to-10Base-T/AUI (adapter unit interface)
Ethernet solution. It allows the flexibility to handle 100M-bps Ethernet protocols as the user’s networking requirements change.
The TNETE100A, one implementation of the ThunderLAN architecture, is an
intelligent protocol network interface. Modular support for the 100 Base-T
(IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) is provided via a media
independent interface (MII). The TNETE110A is the same device without the
MII and is 10M bps only . ThunderLAN uses a single driver suite to support multiple networking protocols.
ThunderLAN architecture was designed to achieve the following goals:
-
High performance with low use of host CPU
-
Simplicity of design
-
Ease of upgrade to higher speed networks
-
Freedom of choice of network protocol
ThunderLAN allows a simple system design by integrating a PCI controller, an
internal first in, first out (FIFO) buffer , a LAN controller, and a 10Base-T physical interface (PHY).
Topic Page
1.1 ThunderLAN Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Networking Protocols 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 PCI Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter Title—Attribute Reference
1-1
ThunderLAN Architecture
1.1 ThunderLAN Architecture
Figure 1–1.The ThunderLAN Controller
PCI Bus
PCI
controller
An integrated PHY provides interface functions for 10Base-T carrier sense
multiple access/collision detect (CSMA/CD) (Ethernet). A MII is used to communicate with the integrated PHY. The PHY is an independent module from
the rest of the ThunderLAN controller. This allows the PHY to be reset and
placed in a power-down mode.
FIFO
registers
Multiplexed
SRAM
LAN
controller
PHY
LAN
802.3
100M-bps
MII
The PCI controller is responsible for direct memory accesses (DMAs) to and
from the host memory . It is designed to relieve the host from time-consuming
data movements, thereby reducing use of the host CPU. The PCI interface
supports a 32-bit data path.
ThunderLAN supports two transmit and one receive channels. The demand
priority protocol supports two frame priorities: normal and priority. The two
transmit channels provide independent host channels for these two priority
types. CSMA/CD protocols only support a single frame priority, but the two
channels can be used to prioritize network access, if needed. All received
frames pass through the single receive channel.
ThunderLAN’s multiplexed SRAM is 3.375K bytes in size. This allows it to support one 1.5K byte FIFO for receive, two 0.75K byte FIFOs for the two transmit
(Tx) channels, and three 128-byte lists (see section 5.1, List Management). In
one-channel mode, the two Tx channels are combined, giving a single 1.5Kbyte FIFO for a single Tx channel. Supporting 1.5K byte of FIFO per channel
allows full frame buffering of Ethernet frames. PCI latency is such that a minimum of 500 bytes of storage is required to support 100M-bps LANs. (Refer to
PCI Local Bus Specification,
the
revision 2.0, section 3.5, Latency).
ThunderLAN’s industry-standard MII permits ease of upgrade. External devices can be connected to the MII and managed, if they support the two-wire
management interface. PHY layer functions for 100M-bps CSMA/CD and demand priority are connected to the MII.
1-2
1.2 Networking Protocols
The MII also allows freedom in choosing a networking protocol. It allows the
use of standard 100M bps CSMA/CD PHY chips. ThunderLAN uses these signal lines to interface to an external 100M bps demand priority PHY . This gives
ThunderLAN the flexibility necessary to handle 10Base-T, 10Base-2,
10Base-5 AUI, 100Base-TX, 100Base-T4, 100Base-FX, and 100VG-AnyLAN
today, while supporting emerging technologies.
ThunderLAN is designed to simplify the software used to transmit frames, receive frames, and service the PHY events. It accomplishes this by integrating
time-consuming tasks into the controller. These tasks include:
-
The DMA of data into and out of the controller
-
A simplified, interrupt-driven frame buffer management technique
-
The elimination of PHY register polling through MII interrupts
DMA of data is handled through list structures. ThunderLAN’s method of handling data through list structures has parallels with the method used in Texas
Instruments TI380 COMMprocessors. There are some differences, such as
the use of a 0 forward pointer.
Networking Protocols
ThunderLAN is designed to meet
its PCI interface standards.
PCI Local Bus Specification
, revision 2.0 for
ThunderLAN Overview
1-3
PCI Interface
1.3 PCI Interface
1.3.1 PCI Cycles
The PCI local bus is a high-performance, 32- or 64-bit bus with multiplexed address and data lines. The bus is designed to be a medium between highly integrated peripheral controller components such as ThunderLAN, add-in boards,
and processor/memory systems.
ThunderLAN executes the following cycles when it acts as the PCI bus master.
The hexadecimal number shown is the bus command encoded in the PC/
BE[3::0]# signals.
-
0x7h–memory write
-
0xCh–memory read multiple
-
0xEh–memory read line
ThunderLAN responds to the following PCI cycles when acting in slave mode
on the PCI bus:
-
0x2h–I/O read
-
0x3h–I/O write
-
0x6h–memory read
-
0x7h–memory write
-
0xAh–configuration read
-
0xBh–configuration write
-
0xCh–memory read multiple
-
0xEh–memory read line
-
0xFh–memory write and invalidate
1-4
Future versions of ThunderLAN may not be limited to these PCI cycles. T exas
Instruments reserves the right to add or delete any cycles to the ThunderLAN
PCI controller. When designing a system, ensure that the attached interface
to ThunderLAN is fully compliant with the
PCI Local Bus Specification
.
1.3.2 Byte Ordering
PCI Interface
ThunderLAN follows the
ferring data on the PCI bus. The PCI bus data is transferred on the P AD[31::0]
lines. PAD31 is the most significant bit, and PAD0 is the least significant bit.
The 32 data lines are enough to transfer four bytes per data cycle. Byte 0 is
the LSbyte and byte 3 is the MSbyte. Byte 0 uses bits 0–7, byte 1 uses bits
8–15, byte 2 uses bits 16–23, byte 3 uses bits 24–31.
Figure 1–2. PCI Bus Byte Assignment
31
ThunderLAN uses the full four bytes per data cycle. The only exception is when
the data to be transferred is not octet aligned. In this case, the PCI controller
might not transfer the full four bytes on the first cycle. ThunderLAN deasserts
the IRDY signal only once, if needed, to synchronize the PCI bus to the internal
64-bit architecture. The deassertion of IRDY occurs on the third cycle of the
PCI bus. ThunderLAN does not deassert IRDY for the rest of the transfer unless the PCI bus asserts the TRDY signal.
PCI Local Bus Specification
convention when trans-
07815162324
Byte 0Byte 1Byte 2Byte 3
ThunderLAN Overview
1-5
1-6
Chapter 2
ThunderLAN Registers
ThunderLAN uses a variety of registers to perform its networking functions.
These include peripheral component interface (PCI) registers, host registers,
internal direct input/output (DIO) registers, media independent interface (MII)
registers, and physical interface (PHY) registers. Access to these is a requirement for setting up the ThunderLAN controller and any of the PHY devices attached to the MII. They must be accessed as well for transmission, initiation,
and reception of data. Other activities which require the user to understand
ThunderLAN’s register spaces include determining the cause of event-driven
interrupts and how to clear them and diagnostic functions. This chapter explains register configurations and discusses control of these spaces through
code examples.
Topic Page
2.1 Register Addresses 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 PCI Configuration Space 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Host Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Internal Registers 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 MII PHY Registers 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 External Devices 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
Register Addresses
2.1 Register Addresses
The following figure shows the various register spaces provided by ThunderLAN. It also shows how a driver uses ThunderLAN’s registers to interface to
external devices such as PHYs, BIOS ROMs, and EEPROMs.
Figure 2–1. How ThunderLAN Registers are Addressed
ThunderLAN
Host registers
SRAM
Internal/DIO registers
NetCmd
NetSts
NetSio
AREG0–3
HASH
Statistics
registers
LEDreg
PCI
HOST CMD
CH PARM
HOST INT
DIO ADR
DIO DATA
PCI registers
I/O base
address
Memory
base address
BIOS ROM
base address
PCI NVRAM
MDIO/MDCLK
EDIO/EDCLK
MII/PHY registers
Generic
Autonegotiation
Reserved
PHY specific
Serial EEPROM
BIOS ROM
2-2
LED IF
LED
One block of registers, the host registers, appear at a programmable place in
memory or port address space, directly on the PCI bus. The beginning address
is determined by the value written into the PCI configuration space base address registers. Once the base register’s address is determined, ThunderLAN
reads and writes to these registers like ordinary memory or I/O ports. Since the
ThunderLAN devices are directly connected to the PCI, there is no external
decode logic that generates a chip select—all the decode is done internally.
ThunderLAN’s internal/DIO registers are accessed via the DIO_ADR and
DIO_DA TA registers in the host register group. An address is placed in the host
DIO_ADR register , and the data to be read or written to the DIO register is read
or written to the DIO_DA TA register. The internal/DIO register space is referenced indirectly via the host registers to minimize the amount of host address
space required to support the ThunderLAN controller. External devices and
their data are also reached via indirect reference through the host registers
Register Addresses
and PCI configuration registers to make control of the system possible through
the one PCI interface.
An EEPROM, required by the PCI, can be written to at manufacture time
through the PCI_NVRAM register, which is located in the host register space.
The EEPROM can also be accessed through the NetSio register which is located in the internal/DIO register space. Control registers on the PHY side of
the MII management interface can be similarly written and read through the
NetSio register.
A BIOS ROM can be enabled via the BRE bit in the PCI BIOS ROM base address register, and its chip selected address dynamically assigned via a base
register in the configuration space. The BRE bit points to a valid address in the
ROM address space which causes two byte-address strobe cycles (EALE,
EXLE) and a read before the PCI cycle is completed.
ThunderLAN Registers
2-3
PCI Configuration Space
2.2 PCI Configuration Space
Figure 2–2.The PCI Configuration Space Registers
Base class
(02h)
Reserved
Vendor IDDevice ID
Status Command
Subclass
Reserved
(00h)(00h)
I/O base address
Memory base address
Reserved (00h)
Cardbus CIS Pointer
Reserved (00h)
BIOS ROM base address
Reserved (00h)
Reserved (00h)
Reserved (00h)
Reserved (00h)
Reserved (00h)
Reserved (00h)
Program interface
(00h)
Latency
timer
Int pin(01h)Min_GntMax_Lat
Byte 0Byte 1Byte 2Byte 3
Revision
Cache line
size
Interrupt line
Reset control
IntDis
031
read only
00h
read/write
04h
read only
08h
read/write
0Ch
read/write
10h
read/write
14h
18h
28h
2Ch
read/write
30h
34h
38h
read/write
3Ch
read/write
40h
44h
48h
read only
2-4
Reserved (00h)
Reserved (00h)
PCI NVRAM
B4h
read only
FFh
Register configuration space information fields are needed to identify a board
in a slot to a driver. The functional purpose of the board, the manufacturer , the
revision, and several bus requirements can be obtained by inspecting these
parameters. The PCI configuration space uses these registers which are
called out in the
-
Identify the ThunderLAN controller. This includes setting the interrupt as-
PCI Local Bus Specification.
These enable the PCI system to:
signed to ThunderLAN.
-
Map the host registers using either the I/O base address register or the
memory base address register. The driver uses the address contained in
these registers to access ThunderLAN’s internal registers.
PCI Configuration Space
-
Set up the PCI bus. Several PCI bus options can be selected through
these registers, including latency and grant. (Refer to
ification,
-
Map a BIOS ROM using the BIOS ROM base address register
subsection 3.5)
PCI Local Bus Spec-
Many of the registers in the PCI configuration space are accessed with PCI
BIOS calls. Refer to the
PCI Local Bus Specification,
chapter 6, for the commands supported by your specific PCI BIOS. Some operating systems (O/Ss)
provide BIOS call support. Your operating system’s user’s guide contains
these specific BIOS support routines.
The PCI specification requires that a bus-resident device respond to bus cycle
codes reserved for reading and writing to configuration space. See the
Local Bus Specification
document for more information on how these short,
PCI
slot-dependent address spaces appear to the host processor. The shaded
registers in Figure 2–3 can be autoloaded from an external serial EEPROM.
Check the following before accessing the PCI configuration space:
-
Ensure that there is a PCI BIOS present or other support for BIOS calls.
-
Ensure that the BIOS is the right revision.
-
Use a PCI BIOS call to find all attached devices on the PCI bus. Make sure
that you are talking to the right device on the PCI bus.
Attaching a pullup resistor to the EDIO pin allows the board designer to automatically read an EEPROM after reset to determine the contents of the first
eight bytes, shown shaded below. If the host attempts to read any of the configuration space during the time the adapter is reading the EEPROM, ThunderLAN rejects the request by signaling target-retry.
Figure 2–3. Configuration EEPROM Data Format
Vendor ID LSByte
Vendor ID MSByte
Device ID LSByte
Device ID MSByte
Revision
Subclass
Min_Gnt
Max_Lat
Checksum
Address
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
ThunderLAN Registers
2-5
PCI Configuration Space
Normally , access to the configuration space is limited to the operating system.
On power-up, the vendor ID, device ID, revision, subclass, Min_Gnt, and
Max_Lat registers are loaded with default values. Vendor-specific data is
loaded into these registers by placing the data into the EEPROM, which is read
at the end of reset if autoload is enabled with a pullup resistor on the EDIO pin.
If the data read from the EEPROM has a checksum error, values are fetched
from the default PCI parameter registers, which are located at addresses
0x08h to 0x0Fh in the internal/DIO registers space.
Some fields in the configuration space like the bits in the memory base address
register and the I/O base address register, which indicate the space size allocation required to access the host registers, are hardwired in the ThunderLAN controllers. Some of the allowed PCI configuration space values like base
registers beyond the basic I/O and memory base registers are not implemented because no other entities are supported by this PCI interface other than the
network function.
To find register information, you must first identify the PCI function ID:
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
// PCIFindDevice – Find PCI device
//
// Parameters:
// DeviceID WORD The device ID
// VendorID WORD The vendor ID
// Index WORD index (normally 0, use when more than
1 device)
// pDev WORD* Where to put the device id
//
// Return val:
// int 0 if successful. see std return codes in
header
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
WORD PciFindDevice(
WORD deviceID,
WORD vendorID,
WORD Index,
WORD *pDev)
{
union REGS r;
2-6
PCI Configuration Space
r.h.ah = PCI_FUNCTION_ID;
r.h.al = FIND_PCI_DEVICE;
r.x.cx = DeviceID;
r.x.dx = VendorID;
r.x.si = Index;
int86(PCI_INT, &r, &r);
*pDev = (WORD)r.x.bx;
return (int)r.h.ah;
}
This code returns the function ID that is used to request reads and writes to
the ThunderLAN PCI configuration space; this varies from installation to installation, based on hardware implementation and slot. This ID is necessary to determine where ThunderLAN is. The device ID indicates a networking card, and
the vendor ID is the manufacturer code. These values can be overlaid in the
configuration space with values from the EEPROM during the autoconfiguration. These should be available to the driver software either in the BIOS ROM
or on machine-readable media supplied with the network board(s).
The following example reads a byte of a PCI register:
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
// PciRdByte() – Read a byte from PCI configuration space
//
// Parameters:
// devid WORD pci device identifier
// addr WORD config address
//
// Return val:
// BYTE value read
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
BYTE PciRdByte(WORD devid, WORD addr)
{
union REGS r;
r.h.ah = PCI_FUNCTION_ID; /* PCI_FUNCTION_ID
0xB1 */
r.h.al = READ_CONFIG_BYTE; /* READ_CONFIG_WORD
0x09 */
r.x.bx = devid;
ThunderLAN Registers
2-7
Loading...