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TMX 320 DM 6446
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Texas Instruments TMX 320 DM 6446 INSTALLATION INSTRUCTIONS

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Digital Media System on-Chip
SPRS283 – DECEMBER 2005

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

• High-Performance Digital Media SoC • ARM926EJ-S (MPU) Core
– 594-MHz C64x+™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb® – 297-MHz ARM926EJ-S™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 4752 C64x+ MIPS – Fully Software-Compatible With C64x /
ARM9™
• Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional – Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions – Additional Instructions to Support Complex
Multiplies
• C64x+ L1/L2 Memory Architecture
– 32K-Byte L1P Program RAM/Cache (Direct
Mapped) – 80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative) – 64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
Mode) Instruction Sets
– DSP Instruction Extensions and Single
Cycle MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache – 8K-Byte Data Cache – 16K-Byte RAM – 16K-Byte ROM
• Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Video Processing Subsystem
– Front End Provides:
• CCD and CMOS Imager Interface
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
• Preview Engine for Real-Time Image
Processing
• Glueless Interface to Common Video
Decoders
• Histogram Module
• Auto-Exposure, Auto-White Balance and
Auto-Focus Module
• Resize Engine
• Resize Images From 1/4x to 4x
• Separate Horizontal/Vertical Control
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Four 54-MHz DACs for a Combination of
• Composite NTSC/PAL Video
• Luma/Chroma Separate Video
(S-video)
• Component (YPbPr or RGB) Video
(Progressive)
• Digital Output
• 8-/16-bit YUV or up to 24-Bit RGB
• HD Resolution
• Up to 2 Video Windows
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C6000, I2C bus, I2C-bus are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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• External Memory Interfaces (EMIFs) • 10/100 Mb/s Ethernet MAC (EMAC)
– 32-Bit DDR2 SDRAM Memory Controller – IEEE 802.3 Compliant
With 256M-Byte Address Space (1.8-V I/O)
– Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
• Flash Memory Interfaces
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)
• Flash Card Interfaces
– Multimedia Card (MMC)/Secure Digital (SD) – CompactFlash Controller With True IDE
Mode
– SmartMedia
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Three UARTs (One with RTS and CTS Flow
Control)
• One Serial Port Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• Audio Serial Port (ASP)
– I2S – AC97 Audio Codec Interface – Standard Voice Codec Interface (AIC12)
– Media Independent Interface (MII)
• VLYNQ™ Interface (FPGA Interface)
• USB Port With Integrated 2.0 PHY
– USB 2.0 High-/Full-Speed (480-Mbps) Client – USB 2.0 High-/Full-/Low-Speed Host
(Mini-Host, Supporting One External
Device)
• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash or UART
• ATA/ATAPI I/F (ATA/ATAPI-5 Specification)
• Individual Power-Saving Modes for ARM/DSP
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
• Up to 71 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• 361-Pin Pb-Free BGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
• 0.09-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal
• Applications:
– Digital Media – Networked Media Encode/Decode – Video Imaging

1.2 Description

The TMS320DM6446 (also referenced as DM6446) leverages TI’s Davinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.
The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core incorporates:
• A coprocessor 15 (CP15) and protection module
• Data and program Memory Management Units (MMUs) with table look-aside buffers.
• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the
2 Digital Media System-on-Chip (DMSoC)
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Digital Media System on-Chip
SPRS283 – DECEMBER 2005
TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).
The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.
The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.
The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.
The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
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The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.
The I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors.
The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
Digital Media System-on-Chip (DMSoC)4
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1.3 Functional Block Diagram

JTAG Interface
System Control
PLLs/Clock
Generator
Input
Clock(s)
Power/Sleep
Controller
Pin
Multiplexing
ARM Subsystem
ARM926EJ-S CPU
16 KB
I-Cache
16 KB RAM
8 KB
D-Cache
16 KB ROM
DSP Subsystem
C64x+ DSP CPU
32 KB
L1 Pgm
64 KB L2 RAM
80 KB
L1 Data
Video-Imaging
Coprocessor (VICP)
BT.656, Y/C, Raw (Bayer)
Video Processing Subsystem (VPSS)
CCD
Controller
Video
Interface
Front End
Resizer
Histogram/
3A
Preview
10b DAC
On-Screen
Display
(OSD)
Video
Encoder
(VENC)
10b DAC
10b DAC 10b DAC
Back End 8b BT.656,
Y/C, 24b RGB
NTSC/ PAL, S-Video, RGB, YPbPr
Switched Central Resource (SCR)
Peripherals
EDMA
Audio Serial
Port
I2C SPI
UART
Serial Interfaces
DDR2
Mem Ctlr
(16b/32b)
Async EMIF/
NAND/
SmartMedia
ATA/
Compact
Flash
MMC/
SD
Program/Data Storage
Watchdog
Timer
PWM
System
General­Purpose
Timer
USB 2.0
PHY
VLYNQ
EMAC
With
MDIO
Connectivity
Figure 1-1 shows the functional block diagram of the device.
Digital Media System on-Chip
SPRS283 – DECEMBER 2005
Figure 1-1. TMS320DM6446 Functional Block Diagram
Digital Media System-on-Chip (DMSoC) 5
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PRODUCT PREVIEW
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Contents
1 Digital Media System-on-Chip (DMSoC) ............ 1 5.1 Parameter Information .............................. 85
1.1 Features .............................................. 1
1.2 Description ............................................ 2
1.3 Functional Block Diagram ............................ 5
2 Device Overview ......................................... 6
2.1 Device Characteristics ................................ 6
2.2 Device Compatibility .................................. 8
2.3 ARM Subsystem ...................................... 8
2.4 DSP Subsystem ..................................... 13
2.5 Memory Map Summary ............................. 20
2.6 Pin Assignments .................................... 23
2.7 Terminal Functions .................................. 29
2.8 Device Support ...................................... 54
3 Device Configuration .................................. 57
3.1 System Module Registers ........................... 57
3.2 Power Considerations ............................... 57
3.3 Clocks Considerations .............................. 58
3.4 Bootmode ........................................... 61
3.5 Configurations at Reset ............................. 64
3.6 Configurations After Reset .......................... 68
3.7 Emulation Control ................................... 79
3.8 Debugging Considerations .......................... 81
3.9 Configuration Examples ............................ 81
4 Device Operating Conditions ........................ 82
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) .......................... 82
4.2 Recommended Operating Conditions ............... 83
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 84
5 Peripheral and Electrical Specifications ........... 85
5.2 Recommended Clock and Control Signal Transition
Behavior ............................................. 86
5.3 Power Supplies ...................................... 86
5.4 Reset ................................................ 95
5.5 Oscillators ........................................... 98
5.6 Clock PLLs ......................................... 101
5.7 Interrupts ........................................... 105
5.8 General-Purpose Input/Output (GPIO) ............. 111
5.9 Enhanced Direct Memory Access (EDMA)
Controller ........................................... 114
5.10 External Memory Interface (EMIF) ................ 126
5.11 ATA/CF ........................................... 132
5.12 MMC/SD ........................................... 149
5.13 Video Processing Sub-System (VPSS) Overview . 151
5.14 USB 2.0 ........................................... 170
5.15 Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 179
5.16 Serial Port Interface (SPI) ......................... 181
5.17 Inter-Integrated Circuit (I2C) ....................... 184
5.18 Audio Serial Port (ASP) ............................ 189
5.19 Ethernet Media Access Controller (EMAC) ........ 193
5.20 Management Data Input/Output (MDIO) .......... 200
5.21 Timer ............................................... 202
5.22 Pulse Width Modulator (PWM) .................... 203
5.23 VLYNQ ............................................ 205
5.24 IEEE 1149.1 JTAG ................................ 209
6 Mechanical Packaging and Orderable
Information ............................................. 211
6.1 Thermal Data for ZWT ............................. 211
6.1.1 Packaging Information ............................ 211

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320DM6446 SoC. The table shows significant features of the
device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count.
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Table 2-1. Characteristics of the Processor
Digital Media System on-Chip
SPRS283 – DECEMBER 2005
HARDWARE FEATURES
DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous EMIF (EMIFA) (speed PLL1/6)
Flash Cards (speed PLL1/6) MMC/SD
EDMA (speed PLL1/3)
Timers (speed PLL1/17 [Normal Mode]) configurable as 2 separate 32-bit (speed PLL1/22 [Turbo Mode]) timers)
Peripherals Not all peripherals pins are
available at the same time (For more detail, see the Device Configuration section).
On-Chip Memory
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) TBD JTAG BSDL_ID 0x0B70 002F
CPU Frequency MHz DM6446 - 594
Cycle Time ns DM6446 - 594
Voltage
PLL Options x1 (Bypass), x22 (-594) BGA Package 16 x 16 mm 357-Pin BGA (ZWT)
Process Technology µm 0.09 µm
UART (speed PLL1/17 [Normal Mode]) 3 (one with RTS and CTS flow (speed PLL1/22 [Turbo Mode]) control)
SPI (speed PLL1/6) 1 (supports 2 slave devices) I2C (speed PLL1/17 [Normal Mode])
(speed PLL1/22 [Turbo Mode]) Audio Serial Port [ASP] (speed PLL1/6) 1 10/100 Ethernet MAC with Management Data Input/Output (speed
PLL1/6) VLYNQ (speed PLL1/6) 1 General-Purpose Input/Output Port (speed PLL1/6) Up to 71 PWM (speed PLL1/17 [Normal Mode])
(speed PLL1/22 [Turbo Mode]) ATA/CF (speed PLL1/6) 1 (ATA/ATAPI-5)
Configurable Video Ports (speed PLL1/6)
USB 2.0 (speed PLL1/6) Size (Bytes) 160KB RAM, 16KB ROM
Organization
JTAGID register (address location: 0x01C4 0028)
Core (V) 1.2 V (-594) I/O (V) 1.8 V, 3.3 V CLKIN frequency multiplier
(27 MHz reference)
(1)
Asynchronous (8/16-bit bus width)
RAM, Flash (NOR, NAND)
2 64-Bit General Purpose (each
DSP [32KB L1 Program (L1P)/Cache (up to 32KB), 80KB L1 Data (L1D)/Cache (up to 32KB), 64KB Unified Mapped RAM/Cache (L2), MPU [16KB I-cache, 8KB D-cache, 16KB RAM, 16KB ROM]
DM6446
SmartMedia/xD
64 independent channels
8 QDMA channels
1 64-Bit Watch Dog
1 (Master/Slave)
3 outputs
1 Input (VPFE)
1 Output (VPBE)
High Speed Device
High Speed Host
DSP 594 MHz
MPU 297 MHz
DSP 1.68 ns MPU 3.37 ns
CF
1
(1) Speeds noted may not indicate peripheral operating speed, but rather peripheral state machine clocking speed.
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Table 2-1. Characteristics of the Processor (continued)
HARDWARE FEATURES
Product Status
(2) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice .
(2)
Product Preview (PP), Advance Information (AI), PP or Production Data (PD)

2.2 Device Compatibility

The ARM926EJ-S RISC MPU is compatible with other ARM9 MPUs from ARM Holdings plc. The C64X+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the
C64X DSP family.

2.3 ARM Subsystem

The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem, the VPSS Subsystem, and a majority of the peripherals and external memories.
The ARM Subsystem includes the following features:
• ARM926EJ-S RISC processor
• ARMv5TEJ (32/16-bit) instruction set
• Little endian
• Co-Processor 15 (CP15)
• MMU
• 16KB Instruction cache
• 8KB Data cache
• Write Buffer
• 16KB Internal RAM (32-bit wide access)
• 16KB Internal ROM (ARM bootloader for non-EMIFA boot options)
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• ARM Interrupt controller
• PLL Controller
• Power and Sleep Controller (PSC)
• System Module
(1)
DM6446

2.3.1 ARM926EJ-S RISC MPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:
• ARM926EJ -S integer core
• CP15 system control coprocessor
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2.3.2 CP15

2.3.3 MMU

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• Memory Management Unit (MMU)
• Separate instruction and data Caches
• Write buffer
• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
• Separate instruction and data AHB bus interfaces
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux, WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
• Mapping sizes are:
– 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10

2.3.4 Caches and Write Buffer

The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features:
• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables.
• Critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.
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• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.5 Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. Placing the instruction region at 0x0000 is necesssary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks.

2.3.6 Advanced High-performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM644X also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:
• Trace Port provides real-time trace capability for the ARM9.
• Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The DM644X trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

2.3.8 ARM Memory Mapping

The ARM memory map is shown in the Memory Map section of this document. The ARM has access to memories shown in the following sections.
2.3.8.1 ARM Internal Memories
The ARM has access to the following ARM internal memories:
• 16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow simulatenous access on any given cycle if there are separate acecsses for code (I-TCM bus) and data (D-TCM) to the different memory regions.
• 16KB ARM Internal ROM
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2.3.8.2 External Memories
The ARM has access to the following External memories:
• DDR2 Synchronous DRAM
• Asynchronous EMIF / NOR Flash / NAND Flash
• ATA/CF
• Flash card devices:
– MMC/SD – xD – SmartMedia
2.3.8.3 DSP Memories
The ARM has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
2.3.8.4 VICP Registers and Memories
The ARM has access to the registers and memories of the Video/Imaging Co-Processor (VICP) Subsystem. The VICP Subsystem consists of the Sequencer, IMX, and VLCD, and the memories associated with these modules. For complete details on the VICP Subsystem, refer to the Documentation Support Section of this document for the VICP Subsystem Guide.
2.3.8.5 ARM-DSP Integration
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DM6446 ARM and DSP integration features are as follows:
• DSP visibility from ARM’s memory map, see the Memory Map section for details
• Boot Modes for DSP - see the Device Configurations section for details
• ARM control of DSP boot / reset - see the Device Configurations section for details
• ARM control of DSP isolation and powerdown / powerup - see the Device Configurations section
• ARM & DSP Interrupts - see the Interrupts section

2.3.9 Peripherals

The ARM9 has access to all of the peripherals on the DM6446 device with the exception of the VICP.

2.3.10 PLL Controller (PLLC)

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for configuring DM6446’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following configuration and control:
• PLL Bypass Mode
• Set PLL multiplier parameters
• Set PLL divider parameters
• PLL power down
• Oscillator power down
The PLLs are briefly described in this document in the Clocking section. For more detailed information on the PLLs and PLL Controller register descriptions, see the Documentation Support section of this document for the ARM Subsystem Guide .
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2.3.11 Power and Sleep Controller (PSC)

The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power domain shut-off. Brief details on the PSC are given in the Power Supply section. For more detailed information and complete register descriptions for the PSC, see the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.12 ARM Interrupt Controller (AINTC)

The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ (interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.13 System Module

The ARM Subsystem includes the System module. The System module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the System module, see the Device Configurations section and the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.14 Power Management

DM6446 has several means of managing power consumption. There is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. The DSP and VICP power can be disabled through register settings. Voltage/Frequency scaling can be used to allow the user to lower the core power supply voltage if the frequency needs for a particular application are lower. Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For more details on power management techniques, see the Device Configurations and Peripheral sections of this document and the Documentation Support section of this document for the ARM Subsystem Guide.
DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. Several typical power management scenarios are described in the following sections.
2.3.14.1 Standby Power Mode
This mode consumes the lowest power, with the minimum set of modules kept alive that are required to wake up the chip to a higher power mode. DSP and coprocessor subsystems are not powered. The rest of the chip is powered and clocks are suspended, except for GPIO (interrupts), UARTs, I2C (in slave mode), and the PWM peripheral. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. DDR2 clock is suspended and the DDR2 Memory Controller is put into self-refresh mode.
2.3.14.2 Low-Power Mode
This mode is for the ARM to sustain some basic control functions. DSP and coprocessor subsystems are not powered. The rest of the chip is powered, but most clocks are suspended, except for ARM, GPIO, UARTs, SPI, I2C, PWMs, and Timers. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. ARM runs at 13.5 MHz, and handles all peripherals by direct access. DDR2 clock is suspended and DDR2 Memory Controller is put into self-refresh mode. ARM will not have access to DDR2 and its caches are either frozen or inaccessible.
2.3.14.3 Active Power Mode
The entire chip is powered. All modules operate at nominal clock frequency. Unused peripherals have their clocks suspended. Active peripherals have their clocks suspended when unneeded.
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2.4 DSP Subsystem

The DSP Subsystem includes the following features:
• C64X+ DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 80KB L1 Data (L1D)/Cache (up to 32KB)
• 64KB Unified Mapped RAM/Cache (L2)
• Little endian

2.4.1 C64X+ DSP CPU Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1 . The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.
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The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilites (including a complex multiply). There is also support for Galois field mutiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.
Other new features include:
• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Futhermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
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• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:
• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
• TMS320C64x Technical Overview (literature number SPRU395)
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src2
src2
.D1
.M1
.S1
.L1
long src
odd dst
src2
src1
src1
src1
src1
even dst
even dst
odd dst
dst1
dst
src2
src2
src2
long src
DA1
ST1b
LD1b LD1a
ST1a
Data path A
Odd
register
file A
(A1, A3,
A5...A31)
Odd
register
file B
(B1, B3,
B5...B31)
.D2
src1
dst
src2
DA2
LD2a LD2b
src2
.M2
src1
dst1
.S2
src1
even dst
long src
odd dst
ST2a ST2b
long src
.L2
even dst
odd dst
src1
Data path B
Control Register
32 MSB 32 LSB
dst2
(A)
32 MSB 32 LSB
2x
1x
32 LSB
32 MSB
32 LSB
32 MSB
dst2
(B)
(B) (A)
8
8
8
8
32
32
32
32
(C)
(C)
Even
register
file A
(A0, A2,
A4...A30)
Even
register
file B
(B0, B2,
B4...B30)
(D)
(D)
(D)
(D)
A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
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Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
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2.4.1.1 C64X+ CPU Cache Registers
Table 2-2 shows a memory map of the C64x+ CPU cache Registers for the device.
HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION
0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register
0x0184 0048 - 0x0184 0FFC - Reserved
0x0184 1000 EDMAWEIGHT L2 EDMA access control register
0x0184 1004 - 0x0184 1FFC - Reserved
0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2
0x0184 200C L2ALLOC3 L2 allocation register 3
0x0184 2010 - 0x0184 3FFF - Reserved
0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register
0x0184 401C L2IWC L2 invalidate word count register
0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register
0x0184 404C L1DIWC L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF - Reserved
0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027 - Reserved
0x0184 5028 L1PINV L1P Global Invalidate
0x0184 502C - 0x0184 5039 - Reserved
0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate
0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF
0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF
0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF
Table 2-2. C64x+ Cache Registers
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Table 2-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION
0x0184 8108 - 0x0184 813C MAR66 - MAR79
0x0184 8140 MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF
0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF

2.4.2 DSP Memory Mapping

The DSP memory map is shown in Section 2.5 . Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections.
2.4.2.1 ARM Internal Memories
The DSP has access to the 16KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).
2.4.2.2 External Memories
The DSP has access to the following External memories:
• DDR2 Synchronous DRAM
• Asynchronous EMIF / NOR Flash
2.4.2.3 DSP Internal Memories
Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 ­0x4FFF FFFF
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The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
2.4.2.4 VICP Registers and Memories
The DSP has access to the registers and memories of the VICP Subsystem. The VICP Subsystem consists of the Sequencer, IMX, and VLCD, and the memories associated with these modules.
The VICP register descriptions are shown in the Table 2-3 - Table 2-6 . For complete details on the VICP Subsystem, refer to the VICP Subsystem Guide.
Table 2-3. Imaging Coprocessors (VICP) Register Descriptions
Address Register Description
0x01CC 0400 CLKC Clock Controller 0x01CC 0404 RSV Reserved 0x01CC 0998 BUFSW Buffer Switch 0x01CC 0A08 RSV Reserved 0x01CC 1698 INTC_GEN Interrupt Generation 0x01CC 1702 INTC_CFG Sequencer Interrupt Controller Configuration 0x01CC 1712 INTC_STAT Sequencer Interrupt or Sync State 0x01CC 1716 INTC_MSK Sequencer SyncIinterrupt Mask 0x01CC 1720 INTC_ARMCFG ARM-to-Sequencer Interrupt Configuration 0x01CC 1730 INTC_DSPCFG DSP-to-Sequencer Interrupt Configuration 0x01CC 1734 INTC_SDMACFG System DMA-to-Sequencer Interrupt Configuration 0x01CC 1744 INTC_LDMACFG Local DMA-to-Sequencer Interrupt Configuration 0x01CC 1748 INTC_IMXCFG iMX-to-Sequencer Interrupt Configuration 0x01CC 1752 INTC_VLCDCFG VLCD-to-Sequencer Interrupt Configuration
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Table 2-3. Imaging Coprocessors (VICP) Register Descriptions (continued)
Address Register Description
0x01CC 1762 RSV Reserved 0x01CC 1766 RSV Reserved 0x01CC 1776 INTC_DBGC Sequencer Debug Control 0x01CC 1780 INTC_HWBPA Sequencer Hardware Breakpoint Address 0x01CC 1784 INTC_BPST Sequencer Breakpoint Status 0x01CC 1794 INTC_TMR Sequencer Performance Timer 0x01CC 1798 INTC_AERR Memory Access Error Status 0x01CC 1808 RSV Reserved 0x01CC 1C96 LDMA_ADR Local DMA Address 0x01CC 1D06 LDMA_CTRL Local DMA Control 0x01CC 1D10 RSV Reserved 0x01CC 4532 CFG_DMA System CFG Bus DMA Setup 0x01CC 4536 CFG_RADDR System CFG Bus Read Address 0x01CC 4546 CFG_WADDR Systen CFG Bus Write Address 0x01CC 4550 CFG_RDATA CFG bus Request Read Data 0x01CC 4560 CFG_WDATA CFG bus Request Write Data
Table 2-4. Imaging Accelerator (IMX) Register Descriptions
Address Acronym Register Description
0x01CC 0900 EMU IMX EMU Register 0x01CC 0904 START IMX Start Register 0x01CC 0908 INTR_EN IMX INTR Enable Register 0x01CC 0918 BUSY IMX Busy Register 0x01CC 0922 CMDPTR IMX Command Pointer 0x01CC 0932 ABORT IMX Abort Register
0x01CC 0933 - Reserved Reserved
0x01CC 09FF
Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)
Address Register Description
0x01CC 0A00 START VLCD Start Register 0x01CC 0A02 MODE VLCD Mode Register 0x01CC 0A04 QIN_ADDR Quantization Input Address Register 0x01CC 0A06 QOUT_ADDR Quantization Output Address Register 0x01CC 0A08 IQIN_ADDR Inverse Quantization Input Address Register 0x01CC 0A16 IQOUT_ADDR Inverse Quantization Output Address Register 0x01CC 0A18 VLCDIN_ADDR VLCD Input Address 0x01CC 0A20 VLCDOUT_ADDR VLCD Output Address 0x01CC 0A22 DC_PRED0 Quantization DC Predictor 0 Register 0x01CC 0A24 DC_PRED1 Quantization DC Predictor 1 Register 0x01CC 0A32 DC_PRED2 Quantization DC Predictor 2 Register 0x01CC 0A34 DC_PRED3 Quantization DC Predictor 3 Register 0x01CC 0A36 DC_PRED4 Quantization DC Predictor 4 Register 0x01CC 0A38 DC_PRED5 Quantization DC Predictor 5 Register 0x01CC 0A40 IDC_PRED0 Inverse Quantization DC Predictor 0 Register 0x01CC 0A48 IDC_PRED1 Inverse Quantization DC Predictor 1 Register
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Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)
(continued)
Address Register Description
0x01CC 0A50 IDC_PRED2 Inverse Quantization DC Predictor 2 Register 0x01CC 0A52 IDC_PRED3 Inverse Quantization DC Predictor 3 Register 0x01CC 0A54 IDC_PRED4 Inverse Quantization DC Predictor 4 Register 0x01CC 0A56 IDC_PRED5 Inverse Quantization DC Predictor 5 Register 0x01CC 0A64 MPEG_INVQ MPEG Inverse Quantization Scale Register 0x01CC 0A66 MPEG_Q MPEG Quantization Scale Register 0x01CC 0A68 MPEG_DELTA_Q MPEG Quantization Delta Register 0x01CC 0A70 MPEG_DELTA_IQ MPEG Inverse Quantization Delta Register 0x01CC 0A72 MPEG_THRED MPEG Thred Register 0x01CC 0A80 MPEG_CBP MPEG Coded Block Pattern Register 0x01CC 0A82 LUMA_VECTOR LUMA Bit Vector Register 0x01CC 0A84 HUFFTAB_DCY Huffman DC Y Table Base Address Register 0x01CC 0A86 HUFFTAB_DCUV Huffman DC UV Table Base Address Register 0x01CC 0A88 HUFFTAB_AC0 Huffman AC0 Table Base Address Register 0x01CC 0A96 HUFFTAB_AC1 Huffman AC1 Table Base Address Register 0x01CC 0A98 OFLEV_MAXOTAB MPEG Max 0 Level Table Base Address Register 0x01CC 0A00 OFLEV_MAX1TAB MPEG Max 1 Level Table Base Address Register 0x01CC 0A02 CTLTAB_DCY DC Y Control Lookup Table Base Address Register 0x01CC 0B04 CTLTAB_DCUV DC UV Control Lookup Table Base Address Register 0x01CC 0B12 CTLTAB_AC0 AC0 Control Lookup Table Base Address Register 0x01CC 0B14 CTLTAB_AC1 AC1 Control Lookup Table Base Address Register 0x01CC 0B16 OFFSET_DCY DC Y Symbol Lookup Table Address Offset Register 0x01CC 0B18 OFFSET_DCUV DC UV Symbol Lookup Table Address Offset Register 0x01CC 0B20 OFFSET_AC0 AC0 Symbol Lookup Table Address Offset Register 0x01CC 0B28 OFFSET_AC1 AC1 Symbol Lookup Table Address Offset Register 0x01CC 0B30 SYMTAB_DCY DC Y Symbol Lookup Table Base Address Register 0x01CC 0B32 SYMTAB_DCUV DC UV Symbol Lookup Table Base Address Register 0x01CC 0B34 SYMTAB_AC0 AC0 Symbol Lookup Table Base Address Register 0x01CC 0B36 SYMTAB_AC1 AC1 Symbol Lookup Table Base Address Register 0x01CC 0B44 CTL VLD Control Register 0x01CC 0B46 VLD_NRBIT_DC DC Number of Bits Register 0x01CC 0B48 VLD_NRBIT_AC AC Number of Bits Register 0x01CC 0B50 BITS_BPTR Bits Pointer Register 0x01CC 0B52 BITS_WORD Bits Word Register 0x01CC 0C56 BYTE_ALIGN Byte Align Register 0x01CC 0C58 HEAD_ADDR Header Address Register 0x01CC 0C60 HEAD_NUM Number of Header Data Register 0x01CC 0C62 QIQ_CONFIG0 QIQ Configuration Register #0 0x01CC 0C64 QIQ_CONFIG1 QIQ Configuration Register #1 0x01CC 0C72 QIQ_CONFIG2 QIQ Configuration Register #2 0x01CC 0C74 QIQ_CONFIG3 QIQ Configuration Register #3 0x01CC 0C76 QIQ_CONFIG4 QIQ Configuration Register #4 0x01CC 0C78 QIQ_CONFIG5 QIQ Configuration Register #5 0x01CC 0C80 VLD_ERRCTL VLD Error Control Register 0x01CC 0C88 VLD_ERRSTAT VLD Error Status Register 0x01CC 0C90 RING_START Ring Buffer Start Address Register
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Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)
(continued)
Address Register Description
0x01CC 0C92 RING_END Ring Buffer End Address Register 0x01CC 0C94 CLKCTRL VLD Prefix Register - DC 0x01CC 0C96 VLD_PREFIX_DC VLD Prefix Register - DC 0x01CC 0D04 VLD_PREFIX_AC VLD Prefix Register - AC 0x01CC 0D06 WMV9_CFG WMV9 Configuration 0x01CC 0D08 FIRST_FRAME First Frame 0x01CC 0D10 H264_MODE H.264 Mode 0x01CC 0D12 NRBITS_THRED First Frame
Table 2-6. Imaging Coprocessor Sequencer Register Descriptions (SEQ)
Address Acronym Description
0x01CC 0B00 Reserved Reserved 0x01CC 0B04 CTRL Sequencer Control Register 0x01CC 0B08 BOOT Sequencer Boot Address Register 0x01CC 0B18 AREG A Register of Sequencer (debug) 0x01CC 0B22 BREG B Register of Sequencer (debug) 0x01CC 0B36 CREG C Register of Sequencer (debug) 0x01CC 0B40 PREG P1 Register of Sequencer (debug) 0x01CC 0B40 P2REG P2 Register of Sequencer (debug) 0x01CC 0B50 PCREG PC Register of Sequencer (debug) 0x01CC 0B54 STATUS Status Register of Sequencer (debug)
0x01CC 0B58 - Reserved Reserved
0x01CC 0BFF

2.4.3 Peripherals

The DSP has controllability for the following peripherals:
• VICP
• EDMA
• ASP
• 2 Timers (Timer 0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers

2.4.4 DSP Interrupt Controller

The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts section. For more detailed on the DSP Interrupt Controller, see the Documentation Support section of this document for the C64x+ CPU User's Guide.

2.5 Memory Map Summary

Table 2-7 shows the memory map address ranges of the device. Table 2-8 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.
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Table 2-7. Memory Map Summary
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START END SIZE EDMA/
ADDRESS ADDRESS (Bytes) PERIPHERAL
0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) Reserved Reserved Reserved 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) Reserved Reserved Reserved 0x0000 4000 0x0000 7FFF 16K ARM ROM (Instruction) Reserved Reserved Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) Reserved ARM RAM0 Reserved 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) Reserved ARM RAM1 Reserved 0x0000 C000 0x0000 FFFF 16K ARM ROM (Data) Reserved ARM ROM Reserved 0x0001 0000 0x000F FFFF 960K Reserved Reserved Reserved Reserved 0x0010 0000 0x001F FFFF 1M Reserved VICP Reserved Reserved 0x0020 0000 0x007F FFFF 6M Reserved Reserved Reserved Reserved 0x0080 0000 0x0080 FFFF 64K Reserved L2 RAM/Cache Reserved Reserved 0x0081 0000 0x00DF FFFF 6080K Reserved Reserved Reserved Reserved 0x00E0 0000 0x00E0 3FFF 16K Reserved Reserved Reserved Reserved 0x00E0 4000 0x00E0 7FFF 16K Reserved Reserved Reserved Reserved 0x00E0 8000 0x00E0 FFFF 32K Reserved L1P Cache Reserved Reserved 0x00E1 0000 0x00F0 3FFF 976K Reserved Reserved Reserved Reserved 0x00F0 4000 0x00F0 FFFF 48K Reserved L1D RAM Reserved Reserved 0x00F1 0000 0x00F1 7FFF 32K Reserved L1D Cache Reserved Reserved 0x00F1 8000 0x017F FFFF 9120K Reserved Reserved Reserved Reserved 0x0180 0000 0x01BB FFFF 3840K Reserved CFG Space Reserved Reserved 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory CFG Space Reserved Reserved 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space Reserved Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher CFG Space Reserved Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved CFG Space Reserved Reserved 0x01BD 0000 0x01BF FFFF 192K Reserved CFG Space Reserved Reserved 0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus CFG Bus Reserved
0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data) Reserved 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved VLYNQ (Remote) Reserved 0x1000 0000 0x1000 7FFF 32K Reserved Reserved Reserved Reserved 0x1000 8000 0x1000 9FFF 8K Reserved ARM RAM0 ARM RAM0 Reserved 0x1000 A000 0x1000 BFFF 8K Reserved ARM RAM1 ARM RAM1 Reserved 0x1000 C000 0x1000 FFFF 16K Reserved ARM ROM ARM ROM Reserved 0x1001 0000 0x110F FFFF 17344K Reserved Reserved Reserved Reserved 0x1110 0000 0x111F FFFF 1M VICP VICP VICP Reserved 0x1120 0000 0x117F FFFF 6M Reserved Reserved Reserved Reserved 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache Reserved 0x1181 0000 0x11DF FFFF 6080K Reserved Reserved Reserved Reserved 0x11E0 0000 0x11E0 3FFF 16K Reserved Reserved Reserved Reserved 0x11E0 4000 0x11E0 7FFF 16K Reserved Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache Reserved 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM Reserved 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache Reserved 0x11F1 8000 0x1FFF FFFF 241M-32K Reserved Reserved Reserved Reserved
ARM C64x+ VPSS
Peripherals Peripherals
Device Overview 21
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PRODUCT PREVIEW
SPRS283 – DECEMBER 2005
START END SIZE EDMA/
ADDRESS ADDRESS (Bytes) PERIPHERAL
0x2000 0000 0x2000 7FFF 32K DDR2 Control Regs DDR2 Control DDR2 Control Regs Reserved
0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved Reserved 0x4200 0x4FFF FFFF 224M Reserved EMIFA/VLYNQ EMIFA/VLYNQ Reserved
(1)
0000 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved
(1) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000
through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be used by C64x+ for both code execution and data accesses.
START END SIZE ARM/EDMA/SEQUENCER C64x+ ADDRESS ADDRESS (Bytes)
0x0180 0000 0x0180 FFFF 64K Reserved C64x+ Interrupt Controller 0x0181 0000 0x0181 0FFF 4K Reserved C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K Reserved C64x+ Security ID 0x0181 2000 0x0181 2FFF 4K Reserved C64x+ Revision ID 0x0182 0000 0x0182 FFFF 64K Reserved C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved Reserved 0x0184 0000 0x0184 FFFF 64K Reserved C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved Reserved 0x0188 0000 0x01BB FFFF 3328K Reserved Reserved 0x01BC 0000 0x01BC 00FF 256 Reserved AET Registers 0x01BC 0100 0x01BC 01FF 256 Reserved Pin Manager and Trace 0x01BC 0400 0x01BC 042F 48 Reserved Reserved 0x01BC 0430 0x01BC 044F 208 Reserved Reserved 0x01BC 0500 0x01BC FFFF 64255 Reserved Reserved 0x01BD 0000 0x01BF FFFF 192K Reserved Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA CC EDMA CC 0x01C1 0000 0x01C1 03FF 1K EDMA TC0 EDMA TC0 0x01C1 0400 0x01C1 07FF 1K EDMA TC1 EDMA TC1 0x01C1 8800 0x01C1 9FFF 6K Reserved Reserved 0x01C1 A000 0x01C1 FFFF 24K Reserved Reserved 0x01C2 0000 0x01C2 03FF 1K UART0 Reserved 0x01C2 0400 0x01C2 07FF 1K UART1 Reserved 0x01C2 0800 0x01C2 0BFF 1K UART2 Reserved 0x01C2 0C00 0x01C2 0FFF 1K Reserved Reserved 0x01C2 1000 0x01C2 13FF 1K I2C Reserved 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (WatchDog) Reserved 0x01C2 2000 0x01C2 23FF 1K PWM0 Reserved 0x01C2 2400 0x01C2 27FF 1K PWM1 Reserved 0x01C2 2800 0x01C2 2BFF 1K PWM2 Reserved 0x01C2 2C00 0x01C3 FFFF 117K Reserved Reserved
Memory Map Summary (continued)
ARM C64x+ VPSS
Regs
Shadow Shadow
Table 2-8. Configuration Memory Map Summary
22 Device Overview
www.ti.com
Configuration Memory Map Summary (continued)
START END SIZE ARM/EDMA/SEQUENCER C64x+ ADDRESS ADDRESS (Bytes)
0x01C4 0000 0x01C4 07FF 2K System Module System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 Reserved 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 Reserved 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and Sleep Controller 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP Reg 0x01C4 2034 0x01C4 23FF 1K - 52 Reserved Reserved 0x01C4 2400 0x01C4 7FFF 23K Reserved Reserved 0x01C4 8000 0x01C4 83FF 1K ARM Interrupt Controller Reserved 0x01C4 8400 0x01C5 FFFF 95K Reserved Reserved 0x01C6 0000 0x01C6 3FFF 16K Reserved Reserved 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Regs / RAM Reserved 0x01C6 6000 0x01C6 67FF 2K ATA/CF Reserved 0x01C6 6800 0x01C6 6FFF 2K SPI Reserved 0x01C6 7000 0x01C6 77FF 2K GPIO Reserved 0x01C6 7800 0x01C6 7FFF 2K Reserved Reserved 0x01C6 8000 0x01C6 FFFF 32K Reserved Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Regs Reserved 0x01C7 4000 0x01C7 FFFF 48K Reserved Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Regs Reserved 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Regs Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC Contol Module RAM Reserved 0x01C8 4000 0x01C8 47FF 2K MDIO Control Regs Reserved 0x01C8 4800 0x01C8 4FFF 2K Reserved Reserved 0x01C8 5000 0x01CB FFFF 236K Reserved Reserved 0x01CC 0000 0x01CD FFFF 128K Image Coprocessor Image Coprocessor 0x01CE 0000 0x01CF FFFF 128K Reserved Reserved 0x01D0 0000 0x01DF FFFF 1M Reserved Reserved 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control Reserved 0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Regs Reserved 0x01E0 2000 0x01E0 3FFF 8K ASP ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved Reserved 0x01E1 0000 0x01E1 FFFF 64K MMC/SD Reserved 0x01E2 0000 0x01E3 FFFF 128K Reserved Reserved 0x01E4 0000 0x01FF FFFF 1792K Reserved Reserved 0x0200 0000 0x03FF FFFF 32M EMIFA Data (CE0) EMIFA Data (CE0) 0x0400 0000 0x05FF FFFF 32M EMIFA Data (CE1) EMIFA Data (CE1) 0x0600 0000 0x07FF FFFF 32M EMIFA Data (CE2) EMIFA Data (CE2) 0x0800 0000 0x09FF FFFF 32M EMIFA Data (CE3) EMIFA Data (CE3) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved
Digital Media System on-Chip
SPRS283 – DECEMBER 2005

2.6 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.
Device Overview 23
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PRODUCT PREVIEW
W
V
U
T
R
P
N
M
L
K
10987654321
10987654321
DDR_D[1]
DV
DDR
EM_A[4]/
GPIO27
CLK_OUT0/
GPIO48
MXI/CLKIN
EM_A[5]/
GPIO26
MXV
SS
PLLV
DD18
APLLREFV
EM_A[6]/
GPIO25
EM_A[8]/
GPIO23
EM_A[7]/
GPIO24
EM_A[13]/
GPIO18
EM_A[10]/
GPIO21
EM_A[15]/
GPIO16/
VLYNQ_TXD3
EM_A[11]/
GPIO20
EM_A[17]/
GPIO14/
VLYNQ_TXD2
EM_A[19]/
GPIO12/
VLYNQ_TXD1
EM_A[20]/
GPIO11/
VLYNQ_RXD0
EM_CS4/
GPIO9/
VLYNQ_
SCRUN
DDR_
DQM[0]
DDR_D[0]
EM_A[21]/
GPIO10/
VLYNQ_TXD0
EM_A[14]/
GPIO17/
VLYNQ_RXD3
EM_A[9]/
GPIO22
MXV
DD
RESET
V
SS
RSV3
V
SS
CV
DD
DV
DDR
DV
DDR
V
SS
V
SS
DDR_A[11]DDR_A[12]DDR_CLK0DDR_CLK0DDR_D[14]
DV
DDR
V
SS
V
SS
DDR_D[5]
DDR_D[6]
DDR_D[9]
DV
DD18
EM_A[16]/
GPIO15/
VLYNQ_RXD2
DV
DDR2
DDR_BS[2]
CV
DD
DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8]
V
SS
DV
DDR
V
SS
V
SS
DV
DDR
DDR_
DQM[1]
DDR_CAS DDR_WE DDR_VDDDLL
CV
DDDSP
CV
DD
DDR_DQS[1] DDR_RAS DDR_A[10]
CV
DD
CV
DD
DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1]
DDR_D[4] DDR_D[12]
V
SS
EM_A[3]/
GPIO28
DV
DD18
CV
DD
DV
DD18
RSV7
MXO V
SS
DV
DD18
V
SS
EM_A[18]/
GPIO13/
VLYNQ_RXD1
V
SS
EM_A[12]/
GPIO19
V
SS
DDR_CS
CV
DDDSP
DDR_DQS[0] DDR_D[10] DDR_BS[0]
EM_CS5/
GPIO8/
VLYNQ_CLK
RSV6
DDR_D[7]
W
V
U
T
R
P
N
M
L
K
SPRS283 – DECEMBER 2005

2.6.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A,
B, C, and D).
24 Device Overview
Figure 2-2. Pin Map [Quadrant A]
www.ti.com
W
V
U
T
R
P
N
M
L
K
191817161514131211
191817161514131211
DDR_A[9]
V
SS
V
SS
CV
DD
CV
DD
V
SS
CV
DD
V
SS
DV
DDR2
DV
DDR2
DV
DDR2
V
SS
DV
DDR2
DV
DDR2
V
SS
DDR_
VSSDLL
DDR_ZPDDR_ZN
V
SS
V
SS
V
SS
DV
DD18
DV
DD18
HD PCLK
V
DDA_1P8V
CI6/CCD14/
UART_TXD2
CI7/CCD15/
UART_RXD2
DAC_IOUT_B
RSV4DDR_D[29]DDR_D[27]DDR_D[21]DDR_D[18]
DAC_IOUT_A
YI4/CCD4
DAC_RBIAS
DDR_A[3]
DDR_A[4]
DDR_A[0]
V
SS
V
SS
DDR_DQM[2]
DDR_D[26]
YI7/CCD7
DDR_D[17] DDR_D[22] DDR_D[24] DDR_D[30]
YI0/CCD0
V
SSA_1P8V
CI5/CCD13/
UART_CTS2
CI1/CCD9
CI4/CCD12/
UART_RTS2
DDR_REF DDR_DQM[3] DDR_D[23] DAC_IOUT_D
YI1/CCD1 YI3/CCD3
DDR_D[20] DDR_DQS[3] DDR_D[31]
YI6/CCD6 VD
DDR_A[7] DDR_A[2] DDR_D[19] DDR_D[28]
DDR_A[6] DDR_D[16]
DAC_IOUT_C
CV
DDDSP
V
SS
CI2/CCD10
YI5/CCD5
DAC_V
REF
DV
DD18
CI0/CCD8
CI3/CCD11
DV
DDR2
V
DDA_1P1V
DV
DDR2
V
SSA_1P1V
YI2/CCD2
DDR_A[1] DDR_DQS[2] DDR_D[25]
V
SS
DDR_A[5]
W
V
U
T
R
P
N
M
L
K
Digital Media System on-Chip
SPRS283 – DECEMBER 2005
Figure 2-3. Pin Map [Quadrant B]
Device Overview 25
www.ti.com
PRODUCT PREVIEW
H
G
F
E
D
C
B
A
191817161514131211
191817161514131211
CV
DDDSP
YOUT4/R4/
AEAW4
GPIOV33_1/
TXCLK
GPIOV33_2/
COL
GPIOV33_9/
RXD2
GPIOV33_8/
RXD1
GPIOV33_6/
TXD3
GPIOV33_4/
TXD1
GPIOV33_12/
RXDV
GPIO2/G0
GPIOV33_7/
RXD0
GPIOV33_10/
RXD3
DV
DD33
DV
DD33
DV
DD33
V
SS
V
SS
V
SS
GPIO1/
C_WE
GPIO0/
LCD_OE
GPIO4/R0/
C_FIELD
GPIOV33_0/
TXEN
GPIO6/B1
VSYNC VPBECLK
M24XI
YOUT3/G8/
AEAW3
VCLK
YOUT7/R7
CLK_OUT1/
TIM_IN/ GPIO49
PWM1/R2/
GPIO46
M24V
DD
CV
DDDSP
GPIO38/R1
DV
DD18
V
SS
USB_R1
COUT5/G2
COUT0/B3/
BTSEL0
YOUT6/R6
YOUT2/G7/
AEAW2
COUT7/G4
YOUT1/G6/
AEAW1
DV
DD18
USB_
V
SSREF
USB_
V
SSA1P2LD0
USB_DP
COUT2/B5/
EM_WIDTH
RSV2
V
SS
USB_V
SS1P8
USB_DM
COUT3/B6/
DSP_BT
COUT6/G3
M24XO
GPIOV33_5/
TXD2
PWM2/
B2/GPIO47
HSYNC
COUT1/B4/
BTSEL1
M24V
SS
GPIO3/B0/
LCD_FIELD
PWM0/
GPIO45
YOUT0/G5/
AEAW0
GPIO5/G1 YOUT5/R5
CV
DD
USB_
V
DDA1P2LD0
COUT4/B7
V
SS
DV
DD18
USB_V
DD1P8
GPIOV33_3/
TXD0
H
G
F
E
D
C
B
A
J
CV
DDDSP
V
SS
USB_
V
SSA3P3
DV
DD18
USB_ID
USB_
V
DDA3P3
CV
DDDSP
V
SS
USB_VBUS
J
BOLD text denotes a DaVinci device pin function
SPRS283 – DECEMBER 2005
Figure 2-4. Pin Map [Quadrant C]
26 Device Overview
www.ti.com
J
H
G
F
E
D
C
B
A
10987654321
10987654321
EM_BA[1]/
DA1/
GPIO52
TMS
SPI_EN0/
GPIO37
RSV1
EM_CS3
SPI_CLK/
GPIO39
SPI_EN1/
HDDIR/ GPIO42
EM_CS2
GPIO7
EM_D12/
DD12
EM_D1/
DD1
EM_D5/
DD5
RSV5
EM_D15/
DD15
EM_D3/
DD3
EM_D9/
DD9
EM_D13/
DD13
EM_D6/
DD6
EM_D8/
DD8
EM_WE/(WE)/
(IOWR)/DIOW
EM_D11/
DD11
ATA_CS1/
GPIO51
EM_R/W/
INTRQ
EM_D4/
DD4
SCL/
GPIO43
TDOSDA/GPIO44
TDI
SD_DATA3
GPIOV33_14/
CRS
V
SS
SD_DATA2
GPIOV33_13/
RXER
SD_DATA1
GPIOV33_15/
MDIO
RTCK
V
SS
DMACK/
UART_TXD1
EM_BA[0]/
DA0
UART_RXD0/
GPIO35
EM_D2/
DD2
EM_D10/
DD10
V
SS
SD_CMD
ATA_CS0/
GPIO50
DV
DD18
V
SS
CV
DDDSP
DR/
GPIO34
V
SS
SD_DATA0
FSR/
GPIO32
TRST
V
SS
DV
DD18
V
SS
V
SS
CLKR/
GPIO30
GPIOV33_11/
RXCLK
DV
DD18
V
SS
CV
DDDSP
CLKX/
GPIO29
GPIOV33_16/
MDCLK
EM_A[2]/
(CLE)
EM_A[1]/
(ALE)
EM_A[0]/
DA2/
GPIO53
V
SS
CV
DDDSP
DV
DD33
SPI_DO/
GPIO41
TCK
FSX/
GPIO31
DX/
GPIO33
DV
DD18
EM_D7/
DD7
UART_TXD0/
GPIO36
EMU1
EMU0
EM_D0/
DD0
DV
DD18
EM_WAIT/
(RDY/BSY)/
IORDY
DV
DD18
DV
DD18
SD_CLK
EM_OE
/(RE)/
(IORD)/DIOR
EM_D14/
DD14
CV
DDDSP
DMARQ/
UART_RXD1
SPI_DI/ GPIO40
J
H
G
F
E
D
C
B
A
Digital Media System on-Chip
SPRS283 – DECEMBER 2005
Figure 2-5. Pin Map [Quadrant D]
Device Overview 27
www.ti.com
PRODUCT PREVIEW
DDR_CLK0
DDR_D[31:0]
DDR_CS
DDR_A[12:0]
Data
Memory Map
Space Select
Address
Byte Enables
32
13
External
Memory I/F
Control
DDR2 Memory Controller (32-bit)
DDR_CAS
DDR_CKE
DDR_CLK0_#
DDR_DQS[3:0]
DDR_RAS DDR_WE
DDR_REF
Bank Address
DDR_BA[2:0]
DDR_DQM[3] DDR_DQM[2]
DDR_DQM[1] DDR_DQM[0]
DDR_VSSDLL
DDR_VDDDLL
200
200
V
SS
DDR_ZN
DDR_ZP
DV
DDR2
(1.8 V)
SPRS283 – DECEMBER 2005

2.6.2 Signal Groups Description

28 Device Overview
Figure 2-6. DDR2 Memory Controller Signals
www.ti.com

2.7 Terminal Functions

Digital Media System on-Chip
SPRS283 – DECEMBER 2005
The terminal functions tables (Table 2-9 through Table 2-33 ) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see the Device Configurations section of this data sheet.
Table 2-9. BOOT Terminal Functions
SIGNAL
NAME NO.
COUT0/
B3/ A16 I/O/Z IPD
BTSEL0
COUT1/
B4/ B16 I/O/Z IPD 0 1 ARM EMIFA Boot (NOR)
BTSEL1
COUT2/
B5/ A17 I/O/Z IPD
EM_WIDTH
COUT3/
B6/ B17 I/O/Z IPD
DSP_BT
YOUT0/
G5/ D15 I/O/Z IPD
AEAW0
YOUT1/
G6/ D16 I/O/Z IPD
AEAW1
YOUT2/ input states of AEAW[4:0] are sampled to set the EMIFA address bus
G7/ D17 I/O/Z IPD width. See the Peripheral Selection at Device Reset section for details.
AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 YOUT3/
R3/ D18 I/O/Z IPD
AEAW3
YOUT4/
R4/ E15 I/O/Z IPD
AEAW4
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
(1)
TYPE
IPD/
(2)
IPU
BOOT
These pins are multiplexed between ARM boot mode and the VPBE. At
reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to
determine the ARM boot configuration. See below for the boot modes set
by these inputs. See the Bootmode section for more details.
After reset, these are video encoder outputs COUT0 and COUT1, or
BTSEL1 BTSEL0 ARM Boot Mode
This pin is multiplexed between EMIFA and the VPBE. At reset, the input
state is sampled to set the EMIFA data bus width (EM_WIDTH). For an
8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
This pin is multiplexed between DSP boot and the VPBE. At reset, the
input state is sampled to set the DSP boot source DSP_BT. The DSP is
booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when
After reset, it is video encoder output COUT3 or RGB666/888 Blue data
These pins are multiplexed between EMIFA and the VPBE. At reset, the
RGB666/888 Blue output data bits 3 and 4 B3/B4.
0 0 ARM ROM Boot (NAND) [default]
1 0 Reserved 1 1 ARM ROM Boot (UART)
Red and Green data bit outputs G5, G6, G7, R3, and R4.
DESCRIPTION
bus, EM_WIDTH = 1.
data bit 5 B5.
DSP_BT=1.
bit 6 output B6.
Device Overview 29
www.ti.com
PRODUCT PREVIEW
SPRS283 – DECEMBER 2005
Table 2-10. Oscillator/PLL Terminal Functions
SIGNAL
NAME NO.
MXI/ Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz).
CLKIN If the internal oscillator is bypassed, this is the external oscillator clock input.
MXO M1 O Crystal output for MX oscillator
MXV
DD
MXV
SS
M24XI F18 I Crystal input for M24 oscillator (24 MHz for USB)
M24XO F19 O Crystal output for M24 oscillator
M24V
DD
M24V
SS
PLLV
DD18
APLLREFV M3 S Core voltage reference for PLL logic and bandgap backup
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
F16 S 1.8V power supply for M24 oscillator F17 GND Ground for M24 oscillator
TYPE
L1 I
L5 S 1.8V power supply for MX oscillator L2 GND Ground for MX oscillator
M2 S 1.8 Volt power supply for PLLs (system and USB)
IPD/
(1)
(2)
IPU
OSCILLATOR, PLL
DESCRIPTION
Table 2-11. Clock Generator Terminal Functions
SIGNAL
NAME NO.
CLK_OUT0/ clock generator, it is clock output CLK_OUT0. This is configurable for 13.5 MHz or
GPIO48 27 MHz clock outputs.
CLK_OUT1/ the USB clock generator, it is clock output CLK_OUT1. This is configurable for 12
TIM_IN/ E19 I/O/Z IPD MHz or 24 MHz clock outputs. GPIO49 For Timer0, it is the timer event capture input TIM_IN.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
TYPE
K1 I/O/Z IPD
IPD/
(1)
(2)
IPU
CLOCK GENERATOR
This pin is multiplexed between the PLL1 clock generator and GPIO. For the PLL1
This pin is multiplexed between the USB clock generator, timer, and GPIO. For
DESCRIPTION
For GPIO, it is GPIO48 [default].
For GPIO, it is GPIO49 [default].
SIGNAL
NAME NO.
RESET L4 I IPU This is the active low Global reset input.
TMS E6 I IPU JTAG test-port mode select input
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
TDO B5 O/Z JTAG test-port data output
TDI A5 I IPU JTAG test-port data input
TCK A6 I IPU JTAG test-port clock input
RTCK B6 O/Z JTAG test-port return clock output TRST D7 I IPD EMU1 C6 I/O/Z IPU Emulation pin 1
EMU0 D6 I/O/Z IPU Emulation pin 0
Device Overview30
Table 2-12. RESET and JTAG Terminal Functions
IPD/
(1)
TYPE
(2)
IPU
RESET
JTAG
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
DESCRIPTION
JTAG compatibility statement portion of this data sheet.
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