Texas Instruments TMX 320 DM 6446 INSTALLATION INSTRUCTIONS

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

• High-Performance Digital Media SoC • ARM926EJ-S (MPU) Core

– 594-MHz C64x+™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb® – 297-MHz ARM926EJ-S™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 4752 C64x+ MIPS – Fully Software-Compatible With C64x /

ARM9™

• Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+™ DSP Core – Eight Highly Independent Functional Units

• Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

• Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle

– Load-Store Architecture With Non-Aligned

Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional – Additional C64x+™ Enhancements

• Protected Mode Operation

• Exceptions Support for Error Detection

and Program Redirection

• Hardware Support for Modulo Loop

Operation

• C64x+ Instruction Set Features

– Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions – Additional Instructions to Support Complex

Multiplies

• C64x+ L1/L2 Memory Architecture

– 32K-Byte L1P Program RAM/Cache (Direct

Mapped) – 80K-Byte L1D Data RAM/Cache (2-Way

Set-Associative) – 64K-Byte L2 Unified Mapped RAM/Cache

(Flexible RAM/Cache Allocation)

Mode) Instruction Sets

– DSP Instruction Extensions and Single

Cycle MAC – ARM® Jazelle® Technology – EmbeddedICE-RT™ Logic for Real-Time

Debug

• ARM9 Memory Architecture

– 16K-Byte Instruction Cache – 8K-Byte Data Cache – 16K-Byte RAM – 16K-Byte ROM

• Embedded Trace Buffer™ (ETB11™) With 4KB

Memory for ARM9 Debug

• Endianness: Little Endian for ARM and DSP

• Video Processing Subsystem

– Front End Provides:

• CCD and CMOS Imager Interface

• BT.601/BT.656 Digital YCbCr 4:2:2

(8-/16-Bit) Interface

• Preview Engine for Real-Time Image

Processing

• Glueless Interface to Common Video

Decoders

• Histogram Module

• Auto-Exposure, Auto-White Balance and

Auto-Focus Module

• Resize Engine

• Resize Images From 1/4x to 4x

• Separate Horizontal/Vertical Control

– Back End Provides:

• Hardware On-Screen Display (OSD)

• Four 54-MHz DACs for a Combination of

• Composite NTSC/PAL Video

• Luma/Chroma Separate Video

(S-video)

• Component (YPbPr or RGB) Video

(Progressive)

• Digital Output

• 8-/16-bit YUV or up to 24-Bit RGB

• HD Resolution

• Up to 2 Video Windows

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

C6000, I2C bus, I2C-bus are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

• External Memory Interfaces (EMIFs) • 10/100 Mb/s Ethernet MAC (EMAC)

– 32-Bit DDR2 SDRAM Memory Controller – IEEE 802.3 Compliant

With 256M-Byte Address Space (1.8-V I/O)

– Asynchronous16-Bit Wide EMIF (EMIFA)

With 128M-Byte Address Reach

• Flash Memory Interfaces

• NOR (8-/16-Bit-Wide Data)

• NAND (8-/16-Bit-Wide Data)

• Flash Card Interfaces

– Multimedia Card (MMC)/Secure Digital (SD) – CompactFlash Controller With True IDE

Mode

– SmartMedia

• Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

• Two 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

• One 64-Bit Watch Dog Timer

• Three UARTs (One with RTS and CTS Flow

Control)

• One Serial Port Interface (SPI) With Two

Chip-Selects

• Master/Slave Inter-Integrated Circuit (I2C

Bus™)

• Audio Serial Port (ASP)

– I2S – AC97 Audio Codec Interface – Standard Voice Codec Interface (AIC12)

– Media Independent Interface (MII)

• VLYNQ™ Interface (FPGA Interface)

• USB Port With Integrated 2.0 PHY

– USB 2.0 High-/Full-Speed (480-Mbps) Client – USB 2.0 High-/Full-/Low-Speed Host

(Mini-Host, Supporting One External

Device)

• Three Pulse Width Modulator (PWM) Outputs

• On-Chip ARM ROM Bootloader (RBL) to Boot

From NAND Flash or UART

• ATA/ATAPI I/F (ATA/ATAPI-5 Specification)

• Individual Power-Saving Modes for ARM/DSP

• Flexible PLL Clock Generators

• IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

• Up to 71 General-Purpose I/O (GPIO) Pins

(Multiplexed With Other Device Functions)

• 361-Pin Pb-Free BGA Package

(ZWT Suffix), 0.8-mm Ball Pitch

• 0.09-µm/6-Level Cu Metal Process (CMOS)

• 3.3-V and 1.8-V I/O, 1.2-V Internal

• Applications:

– Digital Media – Networked Media Encode/Decode – Video Imaging

1.2 Description

The TMS320DM6446 (also referenced as DM6446) leverages TI’s Davinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program Memory Management Units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual

index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the

2 Digital Media System-on-Chip (DMSoC)

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

Digital Media System-on-Chip (DMSoC) 3

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Digital Media System-on-Chip (DMSoC)4

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1.3 Functional Block Diagram

JTAG Interface

System Control

PLLs/Clock

Generator

Input

Clock(s)

Power/Sleep

Controller

Multiplexing

ARM Subsystem

ARM926EJ-S CPU

16 KB

I-Cache

16 KB RAM

8 KB

D-Cache

16 KB ROM

DSP Subsystem

C64x+ DSP CPU

32 KB

L1 Pgm

64 KB L2 RAM

80 KB

L1 Data

Video-Imaging

Coprocessor (VICP)

BT.656, Y/C, Raw (Bayer)

Video Processing Subsystem (VPSS)

CCD

Controller

Video

Interface

Front End

Resizer

Histogram/

Preview

10b DAC

On-Screen

Display

(OSD)

Video

Encoder

(VENC)

10b DAC

10b DAC 10b DAC

Back End 8b BT.656,

Y/C, 24b RGB

NTSC/ PAL, S-Video, RGB, YPbPr

Switched Central Resource (SCR)

Peripherals

EDMA

Audio Serial

Port

I2C SPI

UART

Serial Interfaces

DDR2

Mem Ctlr

(16b/32b)

Async EMIF/

NAND/

SmartMedia

ATA/

Compact

Flash

MMC/

Program/Data Storage

Watchdog

Timer

PWM

System

GeneralPurpose

Timer

USB 2.0

PHY

VLYNQ

EMAC

With

MDIO

Connectivity

Figure 1-1 shows the functional block diagram of the device.

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Figure 1-1. TMS320DM6446 Functional Block Diagram

Digital Media System-on-Chip (DMSoC) 5

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Contents

1 Digital Media System-on-Chip (DMSoC) ............ 1 5.1 Parameter Information .............................. 85

1.1 Features .............................................. 1

1.2 Description ............................................ 2

1.3 Functional Block Diagram ............................ 5

2 Device Overview ......................................... 6

2.1 Device Characteristics ................................ 6

2.2 Device Compatibility .................................. 8

2.3 ARM Subsystem ...................................... 8

2.4 DSP Subsystem ..................................... 13

2.5 Memory Map Summary ............................. 20

2.6 Pin Assignments .................................... 23

2.7 Terminal Functions .................................. 29

2.8 Device Support ...................................... 54

3 Device Configuration .................................. 57

3.1 System Module Registers ........................... 57

3.2 Power Considerations ............................... 57

3.3 Clocks Considerations .............................. 58

3.4 Bootmode ........................................... 61

3.5 Configurations at Reset ............................. 64

3.6 Configurations After Reset .......................... 68

3.7 Emulation Control ................................... 79

3.8 Debugging Considerations .......................... 81

3.9 Configuration Examples ............................ 81

4 Device Operating Conditions ........................ 82

4.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(Unless Otherwise Noted) .......................... 82

4.2 Recommended Operating Conditions ............... 83

4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 84

5 Peripheral and Electrical Specifications ........... 85

5.2 Recommended Clock and Control Signal Transition

Behavior ............................................. 86

5.3 Power Supplies ...................................... 86

5.4 Reset ................................................ 95

5.5 Oscillators ........................................... 98

5.6 Clock PLLs ......................................... 101

5.7 Interrupts ........................................... 105

5.8 General-Purpose Input/Output (GPIO) ............. 111

5.9 Enhanced Direct Memory Access (EDMA)

Controller ........................................... 114

5.10 External Memory Interface (EMIF) ................ 126

5.11 ATA/CF ........................................... 132

5.12 MMC/SD ........................................... 149

5.13 Video Processing Sub-System (VPSS) Overview . 151

5.14 USB 2.0 ........................................... 170

5.15 Universal Asynchronous Receiver/Transmitter

(UART) ............................................. 179

5.16 Serial Port Interface (SPI) ......................... 181

5.17 Inter-Integrated Circuit (I2C) ....................... 184

5.18 Audio Serial Port (ASP) ............................ 189

5.19 Ethernet Media Access Controller (EMAC) ........ 193

5.20 Management Data Input/Output (MDIO) .......... 200

5.21 Timer ............................................... 202

5.22 Pulse Width Modulator (PWM) .................... 203

5.23 VLYNQ ............................................ 205

5.24 IEEE 1149.1 JTAG ................................ 209

6 Mechanical Packaging and Orderable

Information ............................................. 211

6.1 Thermal Data for ZWT ............................. 211

6.1.1 Packaging Information ............................ 211

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320DM6446 SoC. The table shows significant features of the

device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count.

Contents 6

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Table 2-1. Characteristics of the Processor

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

HARDWARE FEATURES

DDR2 Memory Controller DDR2 (16/32-bit bus width) Asynchronous EMIF (EMIFA) (speed PLL1/6)

Flash Cards (speed PLL1/6) MMC/SD

EDMA (speed PLL1/3)

Timers (speed PLL1/17 [Normal Mode]) configurable as 2 separate 32-bit (speed PLL1/22 [Turbo Mode]) timers)

Peripherals Not all peripherals pins are

available at the same time (For more detail, see the Device Configuration section).

On-Chip Memory

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) TBD JTAG BSDL_ID 0x0B70 002F

CPU Frequency MHz DM6446 - 594

Cycle Time ns DM6446 - 594

Voltage

PLL Options x1 (Bypass), x22 (-594) BGA Package 16 x 16 mm 357-Pin BGA (ZWT)

Process Technology µm 0.09 µm

UART (speed PLL1/17 [Normal Mode]) 3 (one with RTS and CTS flow (speed PLL1/22 [Turbo Mode]) control)

SPI (speed PLL1/6) 1 (supports 2 slave devices) I2C (speed PLL1/17 [Normal Mode])

(speed PLL1/22 [Turbo Mode]) Audio Serial Port [ASP] (speed PLL1/6) 1 10/100 Ethernet MAC with Management Data Input/Output (speed

PLL1/6) VLYNQ (speed PLL1/6) 1 General-Purpose Input/Output Port (speed PLL1/6) Up to 71 PWM (speed PLL1/17 [Normal Mode])

(speed PLL1/22 [Turbo Mode]) ATA/CF (speed PLL1/6) 1 (ATA/ATAPI-5)

Configurable Video Ports (speed PLL1/6)

USB 2.0 (speed PLL1/6) Size (Bytes) 160KB RAM, 16KB ROM

Organization

JTAGID register (address location: 0x01C4 0028)

Core (V) 1.2 V (-594) I/O (V) 1.8 V, 3.3 V CLKIN frequency multiplier

(27 MHz reference)

(1)

Asynchronous (8/16-bit bus width)

RAM, Flash (NOR, NAND)

2 64-Bit General Purpose (each

DSP [32KB L1 Program (L1P)/Cache (up to 32KB), 80KB L1 Data (L1D)/Cache (up to 32KB), 64KB Unified Mapped RAM/Cache (L2), MPU [16KB I-cache, 8KB D-cache, 16KB RAM, 16KB ROM]

DM6446

SmartMedia/xD

64 independent channels

8 QDMA channels

1 64-Bit Watch Dog

1 (Master/Slave)

3 outputs

1 Input (VPFE)

1 Output (VPBE)

High Speed Device

High Speed Host

DSP 594 MHz

MPU 297 MHz

DSP 1.68 ns MPU 3.37 ns

(1) Speeds noted may not indicate peripheral operating speed, but rather peripheral state machine clocking speed.

Device Overview 7

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-1. Characteristics of the Processor (continued)

HARDWARE FEATURES

Product Status

(2) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice .

(2)

Product Preview (PP), Advance Information (AI), PP or Production Data (PD)

2.2 Device Compatibility

The ARM926EJ-S RISC MPU is compatible with other ARM9 MPUs from ARM Holdings plc. The C64X+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the

C64X DSP family.

2.3 ARM Subsystem

The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem, the VPSS Subsystem, and a majority of the peripherals and external memories.

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 8KB Data cache

• Write Buffer

• 16KB Internal RAM (32-bit wide access)

• 16KB Internal ROM (ARM bootloader for non-EMIFA boot options)

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

• PLL Controller

• Power and Sleep Controller (PSC)

• System Module

(1)

DM6446

2.3.1 ARM926EJ-S RISC MPU

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

8 Device Overview

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2.3.2 CP15

2.3.3 MMU

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

• Memory Management Unit (MMU)

• Separate instruction and data Caches

• Write buffer

• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux, WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are:

– 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

2.3.4 Caches and Write Buffer

The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with

two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables.

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,

providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.5 Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. Placing the instruction region at 0x0000 is necesssary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks.

2.3.6 Advanced High-performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM644X also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The DM644X trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

2.3.8 ARM Memory Mapping

The ARM memory map is shown in the Memory Map section of this document. The ARM has access to memories shown in the following sections.

2.3.8.1 ARM Internal Memories

The ARM has access to the following ARM internal memories:

• 16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow simulatenous access on any given cycle if there are separate acecsses for code (I-TCM bus) and data (D-TCM) to the different memory regions.

• 16KB ARM Internal ROM

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2.3.8.2 External Memories

The ARM has access to the following External memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash / NAND Flash

• ATA/CF

• Flash card devices:

– MMC/SD – xD – SmartMedia

2.3.8.3 DSP Memories

The ARM has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.3.8.4 VICP Registers and Memories

The ARM has access to the registers and memories of the Video/Imaging Co-Processor (VICP) Subsystem. The VICP Subsystem consists of the Sequencer, IMX, and VLCD, and the memories associated with these modules. For complete details on the VICP Subsystem, refer to the Documentation Support Section of this document for the VICP Subsystem Guide.

2.3.8.5 ARM-DSP Integration

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

DM6446 ARM and DSP integration features are as follows:

• DSP visibility from ARM’s memory map, see the Memory Map section for details

• Boot Modes for DSP - see the Device Configurations section for details

• ARM control of DSP boot / reset - see the Device Configurations section for details

• ARM control of DSP isolation and powerdown / powerup - see the Device Configurations section

• ARM & DSP Interrupts - see the Interrupts section

2.3.9 Peripherals

The ARM9 has access to all of the peripherals on the DM6446 device with the exception of the VICP.

2.3.10 PLL Controller (PLLC)

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for configuring DM6446’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following configuration and control:

• PLL Bypass Mode

• Set PLL multiplier parameters

• Set PLL divider parameters

• PLL power down

• Oscillator power down

The PLLs are briefly described in this document in the Clocking section. For more detailed information on the PLLs and PLL Controller register descriptions, see the Documentation Support section of this document for the ARM Subsystem Guide .

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2.3.11 Power and Sleep Controller (PSC)

The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power domain shut-off. Brief details on the PSC are given in the Power Supply section. For more detailed information and complete register descriptions for the PSC, see the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.12 ARM Interrupt Controller (AINTC)

The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ (interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.13 System Module

The ARM Subsystem includes the System module. The System module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the System module, see the Device Configurations section and the Documentation Support section of this document for the ARM Subsystem Guide.

2.3.14 Power Management

DM6446 has several means of managing power consumption. There is extensive use of clock gating, which reduces the power used by global device clocks and individual peripheral clocks. The DSP and VICP power can be disabled through register settings. Voltage/Frequency scaling can be used to allow the user to lower the core power supply voltage if the frequency needs for a particular application are lower. Clock management can be utilized to reduce clock frequencies in order to reduce switching power. For more details on power management techniques, see the Device Configurations and Peripheral sections of this document and the Documentation Support section of this document for the ARM Subsystem Guide.

DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to customize an optimal power management strategy. Several typical power management scenarios are described in the following sections.

2.3.14.1 Standby Power Mode

This mode consumes the lowest power, with the minimum set of modules kept alive that are required to wake up the chip to a higher power mode. DSP and coprocessor subsystems are not powered. The rest of the chip is powered and clocks are suspended, except for GPIO (interrupts), UARTs, I2C (in slave mode), and the PWM peripheral. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. DDR2 clock is suspended and the DDR2 Memory Controller is put into self-refresh mode.

2.3.14.2 Low-Power Mode

This mode is for the ARM to sustain some basic control functions. DSP and coprocessor subsystems are not powered. The rest of the chip is powered, but most clocks are suspended, except for ARM, GPIO, UARTs, SPI, I2C, PWMs, and Timers. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. ARM runs at 13.5 MHz, and handles all peripherals by direct access. DDR2 clock is suspended and DDR2 Memory Controller is put into self-refresh mode. ARM will not have access to DDR2 and its caches are either frozen or inaccessible.

2.3.14.3 Active Power Mode

The entire chip is powered. All modules operate at nominal clock frequency. Unused peripherals have their clocks suspended. Active peripherals have their clocks suspended when unneeded.

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2.4 DSP Subsystem

The DSP Subsystem includes the following features:

• C64X+ DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)

• 80KB L1 Data (L1D)/Cache (up to 32KB)

• 64KB Unified Mapped RAM/Cache (L2)

• Little endian

2.4.1 C64X+ DSP CPU Description

The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1 . The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

TMS320DM6446

Digital Media System on-Chip

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The C64x+ CPU extends the performance of the C64x core through enhancements and new features. Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilites (including a complex multiply). There is also support for Galois field mutiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Futhermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.

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• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.

• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

• TMS320C64x Technical Overview (literature number SPRU395)

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src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

even dst

odd dst

dst1

dst

src2

long src

DA1

ST1b

LD1b LD1a

ST1a

Data path A

Odd

file A

(A1, A3,

A5...A31)

Odd

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB 32 LSB

dst2

(A)

32 MSB 32 LSB

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B) (A)

(C)

Even

file A

(A0, A2,

A4...A30)

Even

file B

(B0, B2,

B4...B30)

(D)

A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

Digital Media System on-Chip

TMS320DM6446

SPRS283 – DECEMBER 2005

Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths

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2.4.1.1 C64X+ CPU Cache Registers

Table 2-2 shows a memory map of the C64x+ CPU cache Registers for the device.

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2

0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register

0x0184 401C L2IWC L2 invalidate word count register

0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register

0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P Global Invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate

0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF

0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF

0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF

Table 2-2. C64x+ Cache Registers

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Digital Media System on-Chip

Table 2-2. C64x+ Cache Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 8108 - 0x0184 813C MAR66 - MAR79

0x0184 8140 MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF

0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF

2.4.2 DSP Memory Mapping

The DSP memory map is shown in Section 2.5 . Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections.

2.4.2.1 ARM Internal Memories

The DSP has access to the 16KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).

2.4.2.2 External Memories

The DSP has access to the following External memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash

2.4.2.3 DSP Internal Memories

Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 0x4FFF FFFF

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The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.4.2.4 VICP Registers and Memories

The DSP has access to the registers and memories of the VICP Subsystem. The VICP Subsystem consists of the Sequencer, IMX, and VLCD, and the memories associated with these modules.

The VICP register descriptions are shown in the Table 2-3 - Table 2-6 . For complete details on the VICP Subsystem, refer to the VICP Subsystem Guide.

Table 2-3. Imaging Coprocessors (VICP) Register Descriptions

Address Register Description

0x01CC 0400 CLKC Clock Controller 0x01CC 0404 RSV Reserved 0x01CC 0998 BUFSW Buffer Switch 0x01CC 0A08 RSV Reserved 0x01CC 1698 INTC_GEN Interrupt Generation 0x01CC 1702 INTC_CFG Sequencer Interrupt Controller Configuration 0x01CC 1712 INTC_STAT Sequencer Interrupt or Sync State 0x01CC 1716 INTC_MSK Sequencer SyncIinterrupt Mask 0x01CC 1720 INTC_ARMCFG ARM-to-Sequencer Interrupt Configuration 0x01CC 1730 INTC_DSPCFG DSP-to-Sequencer Interrupt Configuration 0x01CC 1734 INTC_SDMACFG System DMA-to-Sequencer Interrupt Configuration 0x01CC 1744 INTC_LDMACFG Local DMA-to-Sequencer Interrupt Configuration 0x01CC 1748 INTC_IMXCFG iMX-to-Sequencer Interrupt Configuration 0x01CC 1752 INTC_VLCDCFG VLCD-to-Sequencer Interrupt Configuration

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Table 2-3. Imaging Coprocessors (VICP) Register Descriptions (continued)

Address Register Description

0x01CC 1762 RSV Reserved 0x01CC 1766 RSV Reserved 0x01CC 1776 INTC_DBGC Sequencer Debug Control 0x01CC 1780 INTC_HWBPA Sequencer Hardware Breakpoint Address 0x01CC 1784 INTC_BPST Sequencer Breakpoint Status 0x01CC 1794 INTC_TMR Sequencer Performance Timer 0x01CC 1798 INTC_AERR Memory Access Error Status 0x01CC 1808 RSV Reserved 0x01CC 1C96 LDMA_ADR Local DMA Address 0x01CC 1D06 LDMA_CTRL Local DMA Control 0x01CC 1D10 RSV Reserved 0x01CC 4532 CFG_DMA System CFG Bus DMA Setup 0x01CC 4536 CFG_RADDR System CFG Bus Read Address 0x01CC 4546 CFG_WADDR Systen CFG Bus Write Address 0x01CC 4550 CFG_RDATA CFG bus Request Read Data 0x01CC 4560 CFG_WDATA CFG bus Request Write Data

Table 2-4. Imaging Accelerator (IMX) Register Descriptions

Address Acronym Register Description

0x01CC 0900 EMU IMX EMU Register 0x01CC 0904 START IMX Start Register 0x01CC 0908 INTR_EN IMX INTR Enable Register 0x01CC 0918 BUSY IMX Busy Register 0x01CC 0922 CMDPTR IMX Command Pointer 0x01CC 0932 ABORT IMX Abort Register

0x01CC 0933 - Reserved Reserved

0x01CC 09FF

Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)

Address Register Description

0x01CC 0A00 START VLCD Start Register 0x01CC 0A02 MODE VLCD Mode Register 0x01CC 0A04 QIN_ADDR Quantization Input Address Register 0x01CC 0A06 QOUT_ADDR Quantization Output Address Register 0x01CC 0A08 IQIN_ADDR Inverse Quantization Input Address Register 0x01CC 0A16 IQOUT_ADDR Inverse Quantization Output Address Register 0x01CC 0A18 VLCDIN_ADDR VLCD Input Address 0x01CC 0A20 VLCDOUT_ADDR VLCD Output Address 0x01CC 0A22 DC_PRED0 Quantization DC Predictor 0 Register 0x01CC 0A24 DC_PRED1 Quantization DC Predictor 1 Register 0x01CC 0A32 DC_PRED2 Quantization DC Predictor 2 Register 0x01CC 0A34 DC_PRED3 Quantization DC Predictor 3 Register 0x01CC 0A36 DC_PRED4 Quantization DC Predictor 4 Register 0x01CC 0A38 DC_PRED5 Quantization DC Predictor 5 Register 0x01CC 0A40 IDC_PRED0 Inverse Quantization DC Predictor 0 Register 0x01CC 0A48 IDC_PRED1 Inverse Quantization DC Predictor 1 Register

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Digital Media System on-Chip

Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)

(continued)

Address Register Description

0x01CC 0A50 IDC_PRED2 Inverse Quantization DC Predictor 2 Register 0x01CC 0A52 IDC_PRED3 Inverse Quantization DC Predictor 3 Register 0x01CC 0A54 IDC_PRED4 Inverse Quantization DC Predictor 4 Register 0x01CC 0A56 IDC_PRED5 Inverse Quantization DC Predictor 5 Register 0x01CC 0A64 MPEG_INVQ MPEG Inverse Quantization Scale Register 0x01CC 0A66 MPEG_Q MPEG Quantization Scale Register 0x01CC 0A68 MPEG_DELTA_Q MPEG Quantization Delta Register 0x01CC 0A70 MPEG_DELTA_IQ MPEG Inverse Quantization Delta Register 0x01CC 0A72 MPEG_THRED MPEG Thred Register 0x01CC 0A80 MPEG_CBP MPEG Coded Block Pattern Register 0x01CC 0A82 LUMA_VECTOR LUMA Bit Vector Register 0x01CC 0A84 HUFFTAB_DCY Huffman DC Y Table Base Address Register 0x01CC 0A86 HUFFTAB_DCUV Huffman DC UV Table Base Address Register 0x01CC 0A88 HUFFTAB_AC0 Huffman AC0 Table Base Address Register 0x01CC 0A96 HUFFTAB_AC1 Huffman AC1 Table Base Address Register 0x01CC 0A98 OFLEV_MAXOTAB MPEG Max 0 Level Table Base Address Register 0x01CC 0A00 OFLEV_MAX1TAB MPEG Max 1 Level Table Base Address Register 0x01CC 0A02 CTLTAB_DCY DC Y Control Lookup Table Base Address Register 0x01CC 0B04 CTLTAB_DCUV DC UV Control Lookup Table Base Address Register 0x01CC 0B12 CTLTAB_AC0 AC0 Control Lookup Table Base Address Register 0x01CC 0B14 CTLTAB_AC1 AC1 Control Lookup Table Base Address Register 0x01CC 0B16 OFFSET_DCY DC Y Symbol Lookup Table Address Offset Register 0x01CC 0B18 OFFSET_DCUV DC UV Symbol Lookup Table Address Offset Register 0x01CC 0B20 OFFSET_AC0 AC0 Symbol Lookup Table Address Offset Register 0x01CC 0B28 OFFSET_AC1 AC1 Symbol Lookup Table Address Offset Register 0x01CC 0B30 SYMTAB_DCY DC Y Symbol Lookup Table Base Address Register 0x01CC 0B32 SYMTAB_DCUV DC UV Symbol Lookup Table Base Address Register 0x01CC 0B34 SYMTAB_AC0 AC0 Symbol Lookup Table Base Address Register 0x01CC 0B36 SYMTAB_AC1 AC1 Symbol Lookup Table Base Address Register 0x01CC 0B44 CTL VLD Control Register 0x01CC 0B46 VLD_NRBIT_DC DC Number of Bits Register 0x01CC 0B48 VLD_NRBIT_AC AC Number of Bits Register 0x01CC 0B50 BITS_BPTR Bits Pointer Register 0x01CC 0B52 BITS_WORD Bits Word Register 0x01CC 0C56 BYTE_ALIGN Byte Align Register 0x01CC 0C58 HEAD_ADDR Header Address Register 0x01CC 0C60 HEAD_NUM Number of Header Data Register 0x01CC 0C62 QIQ_CONFIG0 QIQ Configuration Register #0 0x01CC 0C64 QIQ_CONFIG1 QIQ Configuration Register #1 0x01CC 0C72 QIQ_CONFIG2 QIQ Configuration Register #2 0x01CC 0C74 QIQ_CONFIG3 QIQ Configuration Register #3 0x01CC 0C76 QIQ_CONFIG4 QIQ Configuration Register #4 0x01CC 0C78 QIQ_CONFIG5 QIQ Configuration Register #5 0x01CC 0C80 VLD_ERRCTL VLD Error Control Register 0x01CC 0C88 VLD_ERRSTAT VLD Error Status Register 0x01CC 0C90 RING_START Ring Buffer Start Address Register

TMS320DM6446

SPRS283 – DECEMBER 2005

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Table 2-5. Imaging Coprocessor Variable Length Coder/Decoder Register Descriptions (VLCD)

(continued)

Address Register Description

0x01CC 0C92 RING_END Ring Buffer End Address Register 0x01CC 0C94 CLKCTRL VLD Prefix Register - DC 0x01CC 0C96 VLD_PREFIX_DC VLD Prefix Register - DC 0x01CC 0D04 VLD_PREFIX_AC VLD Prefix Register - AC 0x01CC 0D06 WMV9_CFG WMV9 Configuration 0x01CC 0D08 FIRST_FRAME First Frame 0x01CC 0D10 H264_MODE H.264 Mode 0x01CC 0D12 NRBITS_THRED First Frame

Table 2-6. Imaging Coprocessor Sequencer Register Descriptions (SEQ)

Address Acronym Description

0x01CC 0B00 Reserved Reserved 0x01CC 0B04 CTRL Sequencer Control Register 0x01CC 0B08 BOOT Sequencer Boot Address Register 0x01CC 0B18 AREG A Register of Sequencer (debug) 0x01CC 0B22 BREG B Register of Sequencer (debug) 0x01CC 0B36 CREG C Register of Sequencer (debug) 0x01CC 0B40 PREG P1 Register of Sequencer (debug) 0x01CC 0B40 P2REG P2 Register of Sequencer (debug) 0x01CC 0B50 PCREG PC Register of Sequencer (debug) 0x01CC 0B54 STATUS Status Register of Sequencer (debug)

0x01CC 0B58 - Reserved Reserved

0x01CC 0BFF

2.4.3 Peripherals

The DSP has controllability for the following peripherals:

• VICP

• EDMA

• ASP

• 2 Timers (Timer 0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers

2.4.4 DSP Interrupt Controller

The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts section. For more detailed on the DSP Interrupt Controller, see the Documentation Support section of this document for the C64x+ CPU User's Guide.

2.5 Memory Map Summary

Table 2-7 shows the memory map address ranges of the device. Table 2-8 depicts the expanded map of

the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

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Table 2-7. Memory Map Summary

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

START END SIZE EDMA/

ADDRESS ADDRESS (Bytes) PERIPHERAL

0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) Reserved Reserved Reserved 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) Reserved Reserved Reserved 0x0000 4000 0x0000 7FFF 16K ARM ROM (Instruction) Reserved Reserved Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) Reserved ARM RAM0 Reserved 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) Reserved ARM RAM1 Reserved 0x0000 C000 0x0000 FFFF 16K ARM ROM (Data) Reserved ARM ROM Reserved 0x0001 0000 0x000F FFFF 960K Reserved Reserved Reserved Reserved 0x0010 0000 0x001F FFFF 1M Reserved VICP Reserved Reserved 0x0020 0000 0x007F FFFF 6M Reserved Reserved Reserved Reserved 0x0080 0000 0x0080 FFFF 64K Reserved L2 RAM/Cache Reserved Reserved 0x0081 0000 0x00DF FFFF 6080K Reserved Reserved Reserved Reserved 0x00E0 0000 0x00E0 3FFF 16K Reserved Reserved Reserved Reserved 0x00E0 4000 0x00E0 7FFF 16K Reserved Reserved Reserved Reserved 0x00E0 8000 0x00E0 FFFF 32K Reserved L1P Cache Reserved Reserved 0x00E1 0000 0x00F0 3FFF 976K Reserved Reserved Reserved Reserved 0x00F0 4000 0x00F0 FFFF 48K Reserved L1D RAM Reserved Reserved 0x00F1 0000 0x00F1 7FFF 32K Reserved L1D Cache Reserved Reserved 0x00F1 8000 0x017F FFFF 9120K Reserved Reserved Reserved Reserved 0x0180 0000 0x01BB FFFF 3840K Reserved CFG Space Reserved Reserved 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory CFG Space Reserved Reserved 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space Reserved Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher CFG Space Reserved Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved CFG Space Reserved Reserved 0x01BD 0000 0x01BF FFFF 192K Reserved CFG Space Reserved Reserved 0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus CFG Bus Reserved

0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data) Reserved 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved VLYNQ (Remote) Reserved 0x1000 0000 0x1000 7FFF 32K Reserved Reserved Reserved Reserved 0x1000 8000 0x1000 9FFF 8K Reserved ARM RAM0 ARM RAM0 Reserved 0x1000 A000 0x1000 BFFF 8K Reserved ARM RAM1 ARM RAM1 Reserved 0x1000 C000 0x1000 FFFF 16K Reserved ARM ROM ARM ROM Reserved 0x1001 0000 0x110F FFFF 17344K Reserved Reserved Reserved Reserved 0x1110 0000 0x111F FFFF 1M VICP VICP VICP Reserved 0x1120 0000 0x117F FFFF 6M Reserved Reserved Reserved Reserved 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache Reserved 0x1181 0000 0x11DF FFFF 6080K Reserved Reserved Reserved Reserved 0x11E0 0000 0x11E0 3FFF 16K Reserved Reserved Reserved Reserved 0x11E0 4000 0x11E0 7FFF 16K Reserved Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache Reserved 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM Reserved 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache Reserved 0x11F1 8000 0x1FFF FFFF 241M-32K Reserved Reserved Reserved Reserved

ARM C64x+ VPSS

Peripherals Peripherals

Device Overview 21

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

START END SIZE EDMA/

ADDRESS ADDRESS (Bytes) PERIPHERAL

0x2000 0000 0x2000 7FFF 32K DDR2 Control Regs DDR2 Control DDR2 Control Regs Reserved

0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved Reserved 0x4200 0x4FFF FFFF 224M Reserved EMIFA/VLYNQ EMIFA/VLYNQ Reserved

(1)

0000 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved

(1) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000

through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be used by C64x+ for both code execution and data accesses.

START END SIZE ARM/EDMA/SEQUENCER C64x+ ADDRESS ADDRESS (Bytes)

0x0180 0000 0x0180 FFFF 64K Reserved C64x+ Interrupt Controller 0x0181 0000 0x0181 0FFF 4K Reserved C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K Reserved C64x+ Security ID 0x0181 2000 0x0181 2FFF 4K Reserved C64x+ Revision ID 0x0182 0000 0x0182 FFFF 64K Reserved C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved Reserved 0x0184 0000 0x0184 FFFF 64K Reserved C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved Reserved 0x0188 0000 0x01BB FFFF 3328K Reserved Reserved 0x01BC 0000 0x01BC 00FF 256 Reserved AET Registers 0x01BC 0100 0x01BC 01FF 256 Reserved Pin Manager and Trace 0x01BC 0400 0x01BC 042F 48 Reserved Reserved 0x01BC 0430 0x01BC 044F 208 Reserved Reserved 0x01BC 0500 0x01BC FFFF 64255 Reserved Reserved 0x01BD 0000 0x01BF FFFF 192K Reserved Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA CC EDMA CC 0x01C1 0000 0x01C1 03FF 1K EDMA TC0 EDMA TC0 0x01C1 0400 0x01C1 07FF 1K EDMA TC1 EDMA TC1 0x01C1 8800 0x01C1 9FFF 6K Reserved Reserved 0x01C1 A000 0x01C1 FFFF 24K Reserved Reserved 0x01C2 0000 0x01C2 03FF 1K UART0 Reserved 0x01C2 0400 0x01C2 07FF 1K UART1 Reserved 0x01C2 0800 0x01C2 0BFF 1K UART2 Reserved 0x01C2 0C00 0x01C2 0FFF 1K Reserved Reserved 0x01C2 1000 0x01C2 13FF 1K I2C Reserved 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2 (WatchDog) Reserved 0x01C2 2000 0x01C2 23FF 1K PWM0 Reserved 0x01C2 2400 0x01C2 27FF 1K PWM1 Reserved 0x01C2 2800 0x01C2 2BFF 1K PWM2 Reserved 0x01C2 2C00 0x01C3 FFFF 117K Reserved Reserved

Memory Map Summary (continued)

ARM C64x+ VPSS

Regs

Shadow Shadow

Table 2-8. Configuration Memory Map Summary

22 Device Overview

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Configuration Memory Map Summary (continued)

START END SIZE ARM/EDMA/SEQUENCER C64x+ ADDRESS ADDRESS (Bytes)

0x01C4 0000 0x01C4 07FF 2K System Module System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1 Reserved 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2 Reserved 0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and Sleep Controller 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP Reg 0x01C4 2034 0x01C4 23FF 1K - 52 Reserved Reserved 0x01C4 2400 0x01C4 7FFF 23K Reserved Reserved 0x01C4 8000 0x01C4 83FF 1K ARM Interrupt Controller Reserved 0x01C4 8400 0x01C5 FFFF 95K Reserved Reserved 0x01C6 0000 0x01C6 3FFF 16K Reserved Reserved 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Regs / RAM Reserved 0x01C6 6000 0x01C6 67FF 2K ATA/CF Reserved 0x01C6 6800 0x01C6 6FFF 2K SPI Reserved 0x01C6 7000 0x01C6 77FF 2K GPIO Reserved 0x01C6 7800 0x01C6 7FFF 2K Reserved Reserved 0x01C6 8000 0x01C6 FFFF 32K Reserved Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Regs Reserved 0x01C7 4000 0x01C7 FFFF 48K Reserved Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC Control Regs Reserved 0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Regs Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC Contol Module RAM Reserved 0x01C8 4000 0x01C8 47FF 2K MDIO Control Regs Reserved 0x01C8 4800 0x01C8 4FFF 2K Reserved Reserved 0x01C8 5000 0x01CB FFFF 236K Reserved Reserved 0x01CC 0000 0x01CD FFFF 128K Image Coprocessor Image Coprocessor 0x01CE 0000 0x01CF FFFF 128K Reserved Reserved 0x01D0 0000 0x01DF FFFF 1M Reserved Reserved 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control Reserved 0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Regs Reserved 0x01E0 2000 0x01E0 3FFF 8K ASP ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved Reserved 0x01E1 0000 0x01E1 FFFF 64K MMC/SD Reserved 0x01E2 0000 0x01E3 FFFF 128K Reserved Reserved 0x01E4 0000 0x01FF FFFF 1792K Reserved Reserved 0x0200 0000 0x03FF FFFF 32M EMIFA Data (CE0) EMIFA Data (CE0) 0x0400 0000 0x05FF FFFF 32M EMIFA Data (CE1) EMIFA Data (CE1) 0x0600 0000 0x07FF FFFF 32M EMIFA Data (CE2) EMIFA Data (CE2) 0x0800 0000 0x09FF FFFF 32M EMIFA Data (CE3) EMIFA Data (CE3) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

2.6 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

Device Overview 23

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PRODUCT PREVIEW

10987654321

DDR_D[1]

DDR

EM_A[4]/

GPIO27

CLK_OUT0/

GPIO48

MXI/CLKIN

EM_A[5]/

GPIO26

MXV

PLLV

DD18

APLLREFV

EM_A[6]/

GPIO25

EM_A[8]/

GPIO23

EM_A[7]/

GPIO24

EM_A[13]/

GPIO18

EM_A[10]/

GPIO21

EM_A[15]/

GPIO16/

VLYNQ_TXD3

EM_A[11]/

GPIO20

EM_A[17]/

GPIO14/

VLYNQ_TXD2

EM_A[19]/

GPIO12/

VLYNQ_TXD1

EM_A[20]/

GPIO11/

VLYNQ_RXD0

EM_CS4/

GPIO9/

VLYNQ_

SCRUN

DDR_

DQM[0]

DDR_D[0]

EM_A[21]/

GPIO10/

VLYNQ_TXD0

EM_A[14]/

GPIO17/

VLYNQ_RXD3

EM_A[9]/

GPIO22

MXV

RESET

RSV3

DDR

DDR_A[11]DDR_A[12]DDR_CLK0DDR_CLK0DDR_D[14]

DDR

DDR_D[5]

DDR_D[6]

DDR_D[9]

DD18

EM_A[16]/

GPIO15/

VLYNQ_RXD2

DDR2

DDR_BS[2]

DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8]

DDR

DDR_

DQM[1]

DDR_CAS DDR_WE DDR_VDDDLL

DDDSP

DDR_DQS[1] DDR_RAS DDR_A[10]

DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1]

DDR_D[4] DDR_D[12]

EM_A[3]/

GPIO28

DD18

RSV7

MXO V

DD18

EM_A[18]/

GPIO13/

VLYNQ_RXD1

EM_A[12]/

GPIO19

DDR_CS

DDDSP

DDR_DQS[0] DDR_D[10] DDR_BS[0]

EM_CS5/

GPIO8/

VLYNQ_CLK

RSV6

DDR_D[7]

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

2.6.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A,

B, C, and D).

24 Device Overview

Figure 2-2. Pin Map [Quadrant A]

www.ti.com

191817161514131211

DDR_A[9]

DDR2

DDR_

VSSDLL

DDR_ZPDDR_ZN

DD18

HD PCLK

DDA_1P8V

CI6/CCD14/

UART_TXD2

CI7/CCD15/

UART_RXD2

DAC_IOUT_B

RSV4DDR_D[29]DDR_D[27]DDR_D[21]DDR_D[18]

DAC_IOUT_A

YI4/CCD4

DAC_RBIAS

DDR_A[3]

DDR_A[4]

DDR_A[0]

DDR_DQM[2]

DDR_D[26]

YI7/CCD7

DDR_D[17] DDR_D[22] DDR_D[24] DDR_D[30]

YI0/CCD0

SSA_1P8V

CI5/CCD13/

UART_CTS2

CI1/CCD9

CI4/CCD12/

UART_RTS2

DDR_REF DDR_DQM[3] DDR_D[23] DAC_IOUT_D

YI1/CCD1 YI3/CCD3

DDR_D[20] DDR_DQS[3] DDR_D[31]

YI6/CCD6 VD

DDR_A[7] DDR_A[2] DDR_D[19] DDR_D[28]

DDR_A[6] DDR_D[16]

DAC_IOUT_C

DDDSP

CI2/CCD10

YI5/CCD5

DAC_V

REF

DD18

CI0/CCD8

CI3/CCD11

DDR2

DDA_1P1V

DDR2

SSA_1P1V

YI2/CCD2

DDR_A[1] DDR_DQS[2] DDR_D[25]

DDR_A[5]

Digital Media System on-Chip

TMS320DM6446

SPRS283 – DECEMBER 2005

Figure 2-3. Pin Map [Quadrant B]

Device Overview 25

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PRODUCT PREVIEW

191817161514131211

DDDSP

YOUT4/R4/

AEAW4

GPIOV33_1/

TXCLK

GPIOV33_2/

COL

GPIOV33_9/

RXD2

GPIOV33_8/

RXD1

GPIOV33_6/

TXD3

GPIOV33_4/

TXD1

GPIOV33_12/

RXDV

GPIO2/G0

GPIOV33_7/

RXD0

GPIOV33_10/

RXD3

DD33

GPIO1/

C_WE

GPIO0/

LCD_OE

GPIO4/R0/

C_FIELD

GPIOV33_0/

TXEN

GPIO6/B1

VSYNC VPBECLK

M24XI

YOUT3/G8/

AEAW3

VCLK

YOUT7/R7

CLK_OUT1/

TIM_IN/ GPIO49

PWM1/R2/

GPIO46

M24V

DDDSP

GPIO38/R1

DD18

USB_R1

COUT5/G2

COUT0/B3/

BTSEL0

YOUT6/R6

YOUT2/G7/

AEAW2

COUT7/G4

YOUT1/G6/

AEAW1

DD18

USB_

SSREF

USB_

SSA1P2LD0

USB_DP

COUT2/B5/

EM_WIDTH

RSV2

USB_V

SS1P8

USB_DM

COUT3/B6/

DSP_BT

COUT6/G3

M24XO

GPIOV33_5/

TXD2

PWM2/

B2/GPIO47

HSYNC

COUT1/B4/

BTSEL1

M24V

GPIO3/B0/

LCD_FIELD

PWM0/

GPIO45

YOUT0/G5/

AEAW0

GPIO5/G1 YOUT5/R5

USB_

DDA1P2LD0

COUT4/B7

DD18

USB_V

DD1P8

GPIOV33_3/

TXD0

DDDSP

USB_

SSA3P3

DD18

USB_ID

USB_

DDA3P3

DDDSP

USB_VBUS

BOLD text denotes a DaVinci device pin function

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Figure 2-4. Pin Map [Quadrant C]

26 Device Overview

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10987654321

EM_BA[1]/

DA1/

GPIO52

TMS

SPI_EN0/

GPIO37

RSV1

EM_CS3

SPI_CLK/

GPIO39

SPI_EN1/

HDDIR/ GPIO42

EM_CS2

GPIO7

EM_D12/

DD12

EM_D1/

DD1

EM_D5/

DD5

RSV5

EM_D15/

DD15

EM_D3/

DD3

EM_D9/

DD9

EM_D13/

DD13

EM_D6/

DD6

EM_D8/

DD8

EM_WE/(WE)/

(IOWR)/DIOW

EM_D11/

DD11

ATA_CS1/

GPIO51

EM_R/W/

INTRQ

EM_D4/

DD4

SCL/

GPIO43

TDOSDA/GPIO44

TDI

SD_DATA3

GPIOV33_14/

CRS

SD_DATA2

GPIOV33_13/

RXER

SD_DATA1

GPIOV33_15/

MDIO

RTCK

DMACK/

UART_TXD1

EM_BA[0]/

DA0

UART_RXD0/

GPIO35

EM_D2/

DD2

EM_D10/

DD10

SD_CMD

ATA_CS0/

GPIO50

DD18

DDDSP

DR/

GPIO34

SD_DATA0

FSR/

GPIO32

TRST

DD18

CLKR/

GPIO30

GPIOV33_11/

RXCLK

DD18

DDDSP

CLKX/

GPIO29

GPIOV33_16/

MDCLK

EM_A[2]/

(CLE)

EM_A[1]/

(ALE)

EM_A[0]/

DA2/

GPIO53

DDDSP

DD33

SPI_DO/

GPIO41

TCK

FSX/

GPIO31

DX/

GPIO33

DD18

EM_D7/

DD7

UART_TXD0/

GPIO36

EMU1

EMU0

EM_D0/

DD0

DD18

EM_WAIT/

(RDY/BSY)/

IORDY

DD18

SD_CLK

EM_OE

/(RE)/

(IORD)/DIOR

EM_D14/

DD14

DDDSP

DMARQ/

UART_RXD1

SPI_DI/ GPIO40

Digital Media System on-Chip

TMS320DM6446

SPRS283 – DECEMBER 2005

Figure 2-5. Pin Map [Quadrant D]

Device Overview 27

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PRODUCT PREVIEW

DDR_CLK0

DDR_D[31:0]

DDR_CS

DDR_A[12:0]

Data

Memory Map

Space Select

Address

Byte Enables

External

Memory I/F

Control

DDR2 Memory Controller (32-bit)

DDR_CAS

DDR_CKE

DDR_CLK0_#

DDR_DQS[3:0]

DDR_RAS DDR_WE

DDR_REF

Bank Address

DDR_BA[2:0]

DDR_DQM[3] DDR_DQM[2]

DDR_DQM[1] DDR_DQM[0]

DDR_VSSDLL

DDR_VDDDLL

200 

DDR_ZN

DDR_ZP

DDR2

(1.8 V)

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

2.6.2 Signal Groups Description

28 Device Overview

Figure 2-6. DDR2 Memory Controller Signals

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2.7 Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

The terminal functions tables (Table 2-9 through Table 2-33 ) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see the Device Configurations section of this data sheet.

Table 2-9. BOOT Terminal Functions

SIGNAL

NAME NO.

COUT0/

B3/ A16 I/O/Z IPD

BTSEL0

COUT1/

B4/ B16 I/O/Z IPD 0 1 ARM EMIFA Boot (NOR)

BTSEL1

COUT2/

B5/ A17 I/O/Z IPD

EM_WIDTH

COUT3/

B6/ B17 I/O/Z IPD

DSP_BT

YOUT0/

G5/ D15 I/O/Z IPD

AEAW0

YOUT1/

G6/ D16 I/O/Z IPD

AEAW1

YOUT2/ input states of AEAW[4:0] are sampled to set the EMIFA address bus

G7/ D17 I/O/Z IPD width. See the Peripheral Selection at Device Reset section for details.

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 YOUT3/

R3/ D18 I/O/Z IPD

AEAW3

YOUT4/

R4/ E15 I/O/Z IPD

AEAW4

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)

(1)

TYPE

IPD/

(2)

IPU

BOOT

These pins are multiplexed between ARM boot mode and the VPBE. At

reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to

determine the ARM boot configuration. See below for the boot modes set

by these inputs. See the Bootmode section for more details.

After reset, these are video encoder outputs COUT0 and COUT1, or

BTSEL1 BTSEL0 ARM Boot Mode

This pin is multiplexed between EMIFA and the VPBE. At reset, the input

state is sampled to set the EMIFA data bus width (EM_WIDTH). For an

8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data

After reset, it is video encoder output COUT2 or RGB666/888 Blue output

This pin is multiplexed between DSP boot and the VPBE. At reset, the

input state is sampled to set the DSP boot source DSP_BT. The DSP is

booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when

After reset, it is video encoder output COUT3 or RGB666/888 Blue data

These pins are multiplexed between EMIFA and the VPBE. At reset, the

RGB666/888 Blue output data bits 3 and 4 B3/B4.

0 0 ARM ROM Boot (NAND) [default]

1 0 Reserved 1 1 ARM ROM Boot (UART)

Red and Green data bit outputs G5, G6, G7, R3, and R4.

DESCRIPTION

bus, EM_WIDTH = 1.

data bit 5 B5.

DSP_BT=1.

bit 6 output B6.

Device Overview 29

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-10. Oscillator/PLL Terminal Functions

SIGNAL

NAME NO.

MXI/ Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz).

CLKIN If the internal oscillator is bypassed, this is the external oscillator clock input.

MXO M1 O Crystal output for MX oscillator

MXV

M24XI F18 I Crystal input for M24 oscillator (24 MHz for USB)

M24XO F19 O Crystal output for M24 oscillator

M24V

PLLV

DD18

APLLREFV M3 S Core voltage reference for PLL logic and bandgap backup

F16 S 1.8V power supply for M24 oscillator F17 GND Ground for M24 oscillator

TYPE

L1 I

L5 S 1.8V power supply for MX oscillator L2 GND Ground for MX oscillator

M2 S 1.8 Volt power supply for PLLs (system and USB)

IPD/

(1)

(2)

IPU

OSCILLATOR, PLL

DESCRIPTION

Table 2-11. Clock Generator Terminal Functions

SIGNAL

NAME NO.

CLK_OUT0/ clock generator, it is clock output CLK_OUT0. This is configurable for 13.5 MHz or

GPIO48 27 MHz clock outputs.

CLK_OUT1/ the USB clock generator, it is clock output CLK_OUT1. This is configurable for 12

TIM_IN/ E19 I/O/Z IPD MHz or 24 MHz clock outputs. GPIO49 For Timer0, it is the timer event capture input TIM_IN.

TYPE

K1 I/O/Z IPD

IPD/

(1)

(2)

IPU

CLOCK GENERATOR

This pin is multiplexed between the PLL1 clock generator and GPIO. For the PLL1

This pin is multiplexed between the USB clock generator, timer, and GPIO. For

DESCRIPTION

For GPIO, it is GPIO48 [default].

For GPIO, it is GPIO49 [default].

SIGNAL

NAME NO.

RESET L4 I IPU This is the active low Global reset input.

TMS E6 I IPU JTAG test-port mode select input

TDO B5 O/Z JTAG test-port data output

TDI A5 I IPU JTAG test-port data input

TCK A6 I IPU JTAG test-port clock input

RTCK B6 O/Z JTAG test-port return clock output TRST D7 I IPD EMU1 C6 I/O/Z IPU Emulation pin 1

EMU0 D6 I/O/Z IPU Emulation pin 0

Device Overview30

Table 2-12. RESET and JTAG Terminal Functions

IPD/

(1)

TYPE

(2)

IPU

RESET

JTAG

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

DESCRIPTION

JTAG compatibility statement portion of this data sheet.

www.ti.com

Table 2-13. EMIFA Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

SIGNAL

NAME NO.

COUT2/ sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA

B5/ A17 I/O/Z IPD data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1.

EM_WIDTH After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit

COUT3/ is sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM

B6/ B17 I/O/Z IPD when DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.

DSP_BT After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6

YOUT0/

G5/ D15 I/O/Z IPD

AEAW0

YOUT1/

G6/ D16 I/O/Z IPD

AEAW1

YOUT2/ states of AEAW[4:0] are sampled to set the EMIFA address bus width. See the

G7/ D17 I/O/Z IPD Peripheral Selection at Device Reset section for details.

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and YOUT3/

R3/ D18 I/O/Z IPD

AEAW3

YOUT4/

R4/ E15 I/O/Z IPD

AEAW4

EM_CS2 C2 I/O/Z IPD memories (i.e., NOR flash) or NAND flash. This is the chip select for the default

EM_CS3 B1 I/O/Z IPD

EM_CS4/ Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

GPIO9/ T2 I/O/Z IPD NAND flash.

VLYNQ_SCRUN For GPIO, it is GPIO9.

EM_CS5/ Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

GPIO8/ T1 I/O/Z IPD NAND flash.

VLYNQ_CLOCK For GPIO, it is GPIO pin 8 GPIO8

EM_R/ W/

INTRQ

EM_WAIT/

(RDY/ BSY)/ F1 I/O/Z IPD

IORDY

EM_OE/

( RE)/

( IORD)/

DIOR

TYPE

G3 I/O/Z IPD output EM_R/ W.

H4 I/O/Z IPD For NAND/SmartMedia/xD, it is read enable output ( RE).

IPD/

(1)

(2)

IPU

EMIFA BOOT CONFIGURATION

This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is

This pin is multiplexed between DSP boot and the VPBE. At reset, the input state

These pins are multiplexed between EMIFA and the VPBE. At reset, the input

EMIFA FUNCTIONAL PINS: ASYNC / NOR

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, it is read/write

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

DESCRIPTION

5 B5.

output B6.

Green data bit outputs G5, G6, G7, R3, and R4.

boot and ROM boot modes.

memories (i.e., NOR flash) or NAND flash.

For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN.

For VLYNQ, it is the clock VLYNQ_CLOCK.

For ATA/CF, it is interrupt request input INTRQ.

EMIFA, it is wait state extension input EM_WAIT.

For NAND/SmartMedia/xD, it is ready/busy input (RDY/ BSY).

For ATA/CF, it is IO Ready input IORDY.

EMIFA, it is output enable output EM_OE.

For CF, it is read strobe output ( IORD). For ATA, it is read strobe output DIOR.

Device Overview 31

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SIGNAL

NAME NO.

EM_WE

( WE)

( IOWR)/

DIOW

EM_BA[0]/ this pin is the lowest order bit of the byte address. When connected to a 16-bit

DA0 asynchronous memory, this pin has the same function as EMIF address pin 22

EM_BA[1]/

DA1/ H2 I/O/Z IPD

GPIO52

EM_A[21]/

GPIO10/ T3 I/O/Z IPD

VLYNQ_TXD0

EM_A[20]/

GPIO11/ R3 I/O/Z IPD

VLYNQ_RXD0

EM_A[19]/

GPIO12/ R4 I/O/Z IPD

VLYNQ_TXD1

EM_A[18]/

GPIO13/ P5 I/O/Z IPD

VLYNQ_RXD1

EM_A[17]/

GPIO14/ R2 I/O/Z IPD

VLYNQ_TXD2

EM_A[16]/

GPIO15/ R5 I/O/Z IPD

VLYNQ_RXD2

EM_A[15]/

GPIO16/ P3 I/O/Z IPD

VLYNQ_TXD3

EM_A[14]/

GPIO17/ P4 I/O/Z IPD

VLYNQ_RXD3

EM_A[13]/

GPIO18

EM_A[12]/

GPIO19

EM_A[11]/

GPIO20

EM_A[10]/

GPIO21

G2 I/O/Z IPD For NAND/SmartMedia/xD, it is write enable output ( WE).

J3 I/O/Z IPD

N4 I/O/Z IPD output EM_A[13].

R1 I/O/Z IPD output EM_A[12].

P2 I/O/Z IPD output EM_A[11].

P1 I/O/Z IPD output EM_A[10].

Table 2-13. EMIFA Terminal Functions (continued)

IPD/

(1)

TYPE

(2)

IPU

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.

This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, this is the Bank

Address 0 output (EM_BA[0]). When connected to an 8-bit asynchronous memory,

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is

the Bank Address 1 output EM_BA[1]. When connected to a 16 bit asynchronous

memory this pin is the lowest order bit of the 16-bit word address. When

connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 13

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 12

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 11

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 10

DESCRIPTION

For CF, it is write strobe output ( IOWR). For ATA, it is write strobe output DIOW.

(EM_A[22]).

For ATA/CF, it is Device address bit 0 output DA0.

For ATA/CF, it is Device address bit 1 output DA1.

In GPIO mode, it is GPIO52.

address bit 21 output EM_A[21].

For GPIO, it is GPIO10.

For VLYNQ, it is bit 0 of the transmit bus VLYNQ_TXD0.

address bit 20 output EM_A[20].

For GPIO, it is GPIO11.

For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.

address bit 19 output EM_A[19].

For GPIO, it is GPIO12.

For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.

address bit 18 output EM_A[18].

For GPIO, it is GPIO13.

For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.

address bit 17 output EM_A[17].

For GPIO, it is GPIO14.

For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.

address bit 16 output EM_A[16].

For GPIO, it is GPIO15.

For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.

address bit 15 output EM_A[15].

For GPIO, it is GPIO16.

For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.

address bit 14 output EM_A[14].

For GPIO, it is GPIO17.

For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.

For GPIO, it is GPIO18.

For GPIO, it is GPIO19.

For GPIO, it is GPIO20.

For GPIO, it is GPIO21.

32 Device Overview

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-13. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_A[9]/

GPIO22

EM_A[8]/

GPIO23

EM_A[7]/

GPIO24

EM_A[6]/

GPIO25

EM_A[5]/

GPIO26

EM_A[4]/

GPIO27

EM_A[3]/

GPIO28

EM_A[2]/ For EMIFA, this pin is the EM_A[2] address line.

(CLE) For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

EM_A[1]/ When used for EMIFA, it is address output EM_A[1].

(ALE) For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

EM_A[0]/ address. When connected to a 16-bit asynchronous memory, this pin is the 2nd bit

DA2/ J4 I/O/Z IPD of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the

GPIO53 address.

TYPE

M4 I/O/Z IPD output EM_A[9].

N3 I/O/Z IPD output EM_A[8].

N2 I/O/Z IPD output EM_A[7].

N1 I/O/Z IPD output EM_A[6].

K3 I/O/Z IPD output EM_A[5].

K4 I/O/Z IPD output EM_A[4].

K2 I/O/Z IPD output EM_A[3].

J1 I/O/Z IPD

J2 I/O/Z IPD

IPD/

(1)

(2)

IPU

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 9

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 8

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 7

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 6

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 5

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 4

This pin is multiplexed between EMIFA and GPIO. For EMIFA, it is address bit 3

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is

Address output EM_A[0], which is the least significant bit on a 32-bit word

For ATA/CF, it is Device address bit 2 output DA2.

DESCRIPTION

For GPIO, it is GPIO22.

For GPIO, it is GPIO23.

For GPIO, it is GPIO24.

For GPIO, it is GPIO25.

For GPIO, it is GPIO26.

For GPIO, it is GPIO27.

For GPIO, it is GPIO28.

In GPIO mode, it is GPIO53.

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TMS320DM6446 Digital Media System on-Chip

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SIGNAL

NAME NO.

EM_D0/

DD0

EM_D1/

DD1

EM_D2/

DD2

EM_D3/

DD3

EM_D4/

DD4

EM_D5/

DD5

EM_D6/

DD6

EM_D7/

DD7

EM_D8/

DD8

EM_D9/

DD9

EM_D10/

DD10

EM_D11/

DD11

EM_D12/

DD12

EM_D13/

DD13

EM_D14/

DD14

EM_D15/

DD15

EM_A[1]/ When used for EMIFA, it is address output EM_A[1].

(ALE) For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

EM_A[2]/ For EMIFA, this pin is the EM_A[2] address line.

(CLE) For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

EM_WAIT/

(RDY/ BSY)/ F1 I/O/Z IPD

IORDY

EM_OE/

( RE)/

( IORD)/

DIOR

EM_WE

( WE)

( IOWR)/

DIOW

EM_CS2 C2 I/O/Z IPD memories (i.e. NOR flash) or NAND flash. This is the chip select for the default

EM_CS3 B1 I/O/Z IPD

E5 I/O/Z IPD

D3 I/O/Z IPD

F5 I/O/Z IPD

E3 I/O/Z IPD

E4 I/O/Z IPD

D2 I/O/Z IPD

F4 I/O/Z IPD

C1 I/O/Z IPD

F3 I/O/Z IPD

E2 I/O/Z IPD

G5 I/O/Z IPD

G4 I/O/Z IPD

D1 I/O/Z IPD

F2 I/O/Z IPD

H5 I/O/Z IPD

E1 I/O/Z IPD

J2 I/O/Z IPD

J1 I/O/Z IPD

H4 I/O/Z IPD For NAND/SmartMedia/xD, it is read enable output ( RE).

G2 I/O/Z IPD For NAND/SmartMedia/xD, it is write enable output ( WE).

Table 2-13. EMIFA Terminal Functions (continued)

IPD/

(1)

TYPE

EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD

(2)

IPU

These pins are multiplexed between EMIFA (NAND) and ATA/CF. In all cases

they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous

EMIFA, it is wait state extension input EM_WAIT.

For NAND/SmartMedia/xD, it is ready/busy input (RDY/ BSY).

DESCRIPTION

EM_D[15:0].

For ATA/CF, these are DD[15:0].

For ATA/CF, it is IO Ready input IORDY.

EMIFA, it is output enable output EM_OE.

For CF, it is read strobe output ( IORD). For ATA, it is read strobe output DIOR.

EMIFA, it is write enable output EM_WE.

For CF, it is write strobe output ( IOWR). For ATA, it is write strobe output DIOW.

boot and ROM boot modes.

memories (i.e. NOR flash) or NAND flash.

34 Device Overview

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-13. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_CS4/ Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

GPIO9/ T2 I/O/Z IPD NAND flash.

VLYNQ_SCRUN For GPIO, it is GPIO9.

EM_CS5/ Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

GPIO8/ T1 I/O/Z IPD NAND flash.

VLYNQ_CLOCK For GPIO, it is GPIO pin 8 GPIO8

EM_D0/

DD0

EM_D1/

DD1

EM_D2/

DD2

EM_D3/

DD3

EM_D4/

DD4

EM_D5/

DD5

EM_D6/

DD6

EM_D7/

DD7

EM_D8/

DD8

EM_D9/

DD9

EM_D10/

DD10

EM_D11/

DD11

EM_D12/

DD12

EM_D13/

DD13

EM_D14/

DD14

EM_D15/

DD15

TYPE

E5 I/O/Z IPD

D3 I/O/Z IPD

F5 I/O/Z IPD

E3 I/O/Z IPD

E4 I/O/Z IPD

D2 I/O/Z IPD

F4 I/O/Z IPD

C1 I/O/Z IPD

F3 I/O/Z IPD

E2 I/O/Z IPD

G5 I/O/Z IPD

G4 I/O/Z IPD

D1 I/O/Z IPD

F2 I/O/Z IPD

H5 I/O/Z IPD

E1 I/O/Z IPD

IPD/

(1)

(2)

IPU

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

For VLYNQ, it is the clock VLYNQ_CLOCK.

These pins are multiplexed between EMIFA (NAND) and ATA/CF. In all cases

they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are

For ATA/CF, these are DD[15:0].

DESCRIPTION

EM_D[15:0].

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Table 2-14. DDR2 Memory Controller Terminal Functions

SIGNAL

NAME NO.

DDR_CLK0 W7 I/O/Z DDR2 Clock

DDR_CLK0_# W8 I/O/Z DDR2 Differential clock

DDR_CKE V8 I/O/Z DDR2 Clock Enable

DDR_CS T9 I/O/Z DDR2 Active low chip select

DDR_WE T8 I/O/Z DDR2 Active low Write enable DDR_DQM[3] T16 I/O/Z DDR_DQM[2] T14 I/O/Z DDR_DQM[1] T6 I/O/Z DDR_DQM[0] T4 I/O/Z

DDR_RAS U7 I/O/Z DDR2 Row Access Signal output

DDR_CAS T7 I/O/Z DDR2 Column Access Signal output DDR_DQS[0] U4 I/O/Z Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to DDR_DQS[1] U6 I/O/Z DDR_DQS[2] U14 I/O/Z

DDR_DQS[3] U16 I/O/Z

DDR_BS[0] U8 DDR_BS[1] V9 I/O/Z Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10

DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 I/O/Z DDR2 address bus DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] U13 DDR_A[0] W13

TYPE

IPD/

(1)

(2)

IPU

DDR2 Memory Controller

DQM3: For upper byte data bus DDR_D[31:24]

DQM0: For lower byte DDR_D[7:0]

the DDR2 memory when writing and inputs when reading. They are used to

DQS3 : For upper byte DDR_D[31:24]

DQS0: For bottom byte DDR_D[7:0]

DESCRIPTION

DDR2 Data mask outputs

DQM2: For DDR_D[23:16]

DQM1: For DDR_D[15:8]

synchronize the data transfers.

DQS2: For DDR_D[23:16]

DQS1: For DDR_D[15:8]

36 Device Overview

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Digital Media System on-Chip

Table 2-14. DDR2 Memory Controller Terminal Functions (continued)

SIGNAL

NAME NO.

DDR_D[31] U19 DDR_D[30] V19 DDR_D[29] W18 DDR_D[28] V18 DDR_D[27] W17 DDR_D[26] U18 DDR_D[25] U17 DDR_D[24] V17 DDR_D[23] T17 DDR_D[22] V16 DDR_D[21] W16 DDR_D[20] U15 DDR_D[19] V15 DDR_D[18] W15 DDR_D[17] V14 DDR_D[16] W14 DDR_D[15] V7 DDR_D[14] W6 DDR_D[13] V6 DDR_D[12] W5 DDR_D[11] V5 DDR_D[10] U5

DDR_D[9] W4 DDR_D[8] V4 DDR_D[7] W3 DDR_D[6] V3 DDR_D[5] U3 DDR_D[4] W2 DDR_D[3] V2 DDR_D[2] V1 DDR_D[1] U2 DDR_D[0] U1

DDR_VREF T15 I Reference voltage input for the SSTL_18 IO buffers. DDR_VSSDLL T11 GND Ground for the DDR2 DLL DDR_VDDDLL T10 S Power (1.8 Volts) for the DDR2 DLL

DDR_ZN T12 O/Z

DDR_ZP T13 O/Z

TYPE

I/O/Z DDR2 data bus can be configured as 32 bits wide or 16 bits wide.

IPD/

(1)

(2)

IPU

Impedance control for DDR2 outputs. This must be connected via a 200 Ω resistor

DESCRIPTION

to DV

to VSS.

DDR2

TMS320DM6446

SPRS283 – DECEMBER 2005

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Table 2-15. I2C Terminal Functions

SIGNAL

NAME NO.

SCL/ This pin is multiplexed between I2C and GPIO. For I2C, it is clock output SCL.

GPIO43 For GPIO, it is GPIO43.

SDA/

GPIO44

TYPE

C4 I/O/Z IPD

B4 I/O/Z IPD signal SDA.

IPD/

(1)

(2)

IPU

I2C

This pin is multiplexed between I2C and GPIO. For I2C, it is bi-directional data

DESCRIPTION

For GPIO, it is GPIO44.

Table 2-16. Audio Serial Port (ASP) Terminal Functions

SIGNAL

NAME NO.

CLKX/

GPIO29

CLKR/

GPIO30

FSX/

GPIO31

FSR/

GPIO32

DX/

GPIO33

DR/

GPIO34

TYPE

B8 I/O/Z IPD CLKX.

A8 I/O/Z IPD CLKR.

C8 I/O/Z IPD synchronization IO FSX.

C7 I/O/Z IPD synchronization IO FSR.

B7 I/O/Z IPD output DX.

A7 I/O/Z IPD DR.

IPD/

(1)

(2)

IPU

Audio Serial Port (ASP)

This pin is multiplexed between ASP and GPIO. For ASP, it is Transmit clock IO

This pin is multiplexed between ASP and GPIO. For ASP, it is Receive clock IO

This pin is multiplexed between ASP and GPIO. For ASP, it is Transmit frame

This pin is multiplexed between ASP and GPIO. For ASP, it is Receive frame

This pin is multiplexed between ASP and GPIO. For ASP, it is Data Transmit

This pin is multiplexed between ASP and GPIO. For ASP, it is Data Receive input

DESCRIPTION

For GPIO, it is GPIO29.

For GPIO, it is GPIO30

For GPIO, it is GPIO31.

For GPIO, it is GPIO32.

For GPIO, it is GPIO33.

For GPIO, it is GPIO34.

SIGNAL

NAME NO.

SPI_EN0/

GPIO37

SPI_EN1/

HDDIR/ B2 I/O/Z IPD

GPIO42

SPI_CLK/

GPIO39

SPI_DI/ This pin is multiplexed between SPI and GPIO. For SPI, it is data input SPI_DI.

GPIO40 For GPIO, it is GPIO40.

38 Device Overview

A4 I/O/Z IPD device 0 enable output SPI_EN0.

A3 I/O/Z IPD SPI_CLK.

B3 I/O/Z IPD

Table 2-17. SPI Terminal Functions

IPD/

(1)

TYPE

(2)

IPU

Serial Port Interface (SPI)

This pin is multiplexed between SPI and GPIO. When used by SPI, it is SPI slave

This pin is multiplexed between SPI, ATA, and GPIO. When used by SPI, it is SPI

This pin is multiplexed between SPI and GPIO. For SPI, it is clock output

slave device 1 enable output SPI_EN1.

For ATA, it is buffer direction control output HDDIR.

DESCRIPTION

For GPIO, it is GPIO37.

For GPIO, it is GPIO42.

For GPIO, it is GPIO39.

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Table 2-17. SPI Terminal Functions (continued)

SIGNAL

NAME NO.

SPI_DO/ This pin is multiplexed between SPI and GPIO. For SPI it is data output SPI_DO.

GPIO41 For GPIO, it is GPIO41.

TYPE

A2 I/O/Z IPD

Table 2-18. EMAC and MDIO Terminal Functions

IPD/

(1)

(2)

IPU

DESCRIPTION

SIGNAL

NAME NO.

GPIOV33_0/

TXEN

GPIOV33_1/

TXCLK

GPIOV33_2/

COL

GPIOV33_6/

TXD3

GPIOV33_5/

TXD2

GPIOV33_4/

TXD1

GPIOV33_3/

TXD0

GPIOV33_11/

RXCLK

GPIOV33_12/

RXDV

GPIOV33_13/

RXER

GPIOV33_14/

CRS

GPIOV33_10/

RXD3

GPIOV33_9/

RXD2

GPIOV33_8/

RXD1

GPIOV33_7/

RXD0

B13 I/O/Z IPD is 3.3V GPIO pin GPIOV33_0.

A13 I/O/Z IPD 3.3V GPIO GPIOV33_1.

A12 I/O/Z IPD 3.3V GPIO GPIOV33_2.

C12 I/O/Z IPD 3.3V GPIO GPIOV33_6.

A11 I/O/Z IPD 3.3V GPIO GPIOV33_5.

D12 I/O/Z IPD 3.3V GPIO GPIOV33_4.

B12 I/O/Z IPD 3.3V GPIO GPIOV33_3.

A10 I/O/Z IPD 3.3V GPIO GPIOV33_11.

D11 I/O/Z IPD 3.3V GPIO GPIOV33_12.

D10 I/O/Z IPD 3.3V GPIO GPIOV33_13.

C10 I/O/Z IPD 3.3V GPIO GPIOV33_14.

E11 I/O/Z IPD 3.3V GPIO GPIOV33_10.

B11 I/O/Z IPD 3.3V GPIO GPIOV33_9.

C11 I/O/Z IPD 3.3V GPIO GPIOV33_8.

E12 I/O/Z IPD 3.3V GPIO GPIOV33_7.

TYPE

IPD/

(1)

(2)

IPU

EMAC

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, this pin

In Ethernet MAC mode, it is Transmit Enable output TXEN.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Clock output TXCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Collision Detect input COL.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 3 output TXD3.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 2 output TXD2.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 1 output TXD1.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 0 output TXD0.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Clock input RXCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data Valid input RXDV.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Error input RXER.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Carrier Sense input CRS.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 3 input RXD3.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 2 input RXD2.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive data 1 input RXD1.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 0 input RXD0.

DESCRIPTION

Device Overview 39

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TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

SIGNAL

NAME NO.

GPIOV33_16/

MDCLK

GPIOV33_15/

MDIO

Table 2-18. EMAC and MDIO Terminal Functions (continued)

TYPE

B10 I/O/Z IPD 3.3V GPIO GPIOV33_16.

E10 I/O/Z IPD 3.3V GPIO GPIOV33_15.

(2)

IPU

MDIO

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Management Data Clock output MDCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Management Data IO MDIO.

IPD/

(1)

Table 2-19. GPIOV33 Terminal Functions

DESCRIPTION

SIGNAL

NAME NO.

GPIOV33_16/

MDCLK

GPIOV33_15/

MDIO

GPIOV33_14/

CRS

GPIOV33_13/

RXER

GPIOV33_12/

RXDV

GPIOV33_11/

RXCLK

GPIOV33_10/

RXD3

GPIOV33_9/

RXD2

GPIOV33_8/

RXD1

GPIOV33_7/

RXD0

GPIOV33_6/

TXD3

B10 I/O/Z IPD 3.3V GPIO GPIOV33_16.

E10 I/O/Z IPD 3.3V GPIO GPIOV33_15.

C10 I/O/Z IPD 3.3V GPIO GPIOV33_14.

D10 I/O/Z IPD 3.3V GPIO GPIOV33_13.

D11 I/O/Z IPD 3.3V GPIO GPIOV33_12.

A10 I/O/Z IPD 3.3V GPIO GPIOV33_11.

E11 I/O/Z IPD 3.3V GPIO GPIOV33_10.

B11 I/O/Z IPD 3.3V GPIO GPIOV33_9.

C11 I/O/Z IPD 3.3V GPIO GPIOV33_8.

E12 I/O/Z IPD 3.3V GPIO GPIOV33_7.

C12 I/O/Z IPD 3.3V GPIO GPIOV33_6.

GPIOV33_5/

TXD2

GPIOV33_4/

TXD1

GPIOV33_3/

TXD0

A11 I/O/Z IPD 3.3V GPIO GPIOV33_5.

D12 I/O/Z IPD 3.3V GPIO GPIOV33_4.

B12 I/O/Z IPD 3.3V GPIO GPIOV33_3.

TYPE

(2)

IPU

GPIOV33

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Management Data Clock output MDCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Management Data IO MDIO.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Carrier Sense input CRS.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Error input RXER.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data Valid input RXDV.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Clock input RXCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 3 input RXD3.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 2 input RXD2.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive data 1 input RXD1.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Receive Data 0 input RXD0.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 3 output TXD3.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 2 output TXD2.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 1 output TXD1.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

In Ethernet MAC mode, it is Transmit Data 0 output TXD0.

DESCRIPTION

IPD/

(1)

40 Device Overview

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SIGNAL

NAME NO.

GPIOV33_2/

COL

GPIOV33_1/

TXCLK

GPIOV33_0/

TXEN

Table 2-19. GPIOV33 Terminal Functions (continued)

TYPE

(2)

IPU

IPD/

(1)

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

A12 I/O/Z IPD 3.3V GPIO GPIOV33_2.

In Ethernet MAC mode, it is Collision Detect input COL.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, it is

A13 I/O/Z IPD 3.3V GPIO GPIOV33_1.

In Ethernet MAC mode, it is Transmit Clock output TXCLK.

This pin is multiplexed between GPIO and Ethernet MAC. In GPIO mode, this pin

B13 I/O/Z IPD is 3.3V GPIO pin GPIOV33_0.

In Ethernet MAC mode, it is Transmit Enable output TXEN.

Table 2-20. Standalone GPIOV18 Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

DESCRIPTION

SIGNAL

NAME NO.

TYPE

IPD/

(1)

(2)

IPU

DESCRIPTION

Standalone GPIOV18

GPIO7 C3 I/O/Z IPD This pin is standalone and functions as GPIO7.

Table 2-21. USB Terminal Functions

SIGNAL

NAME NO.

TYPE

M24XI F18 I Crystal input for M24 oscillator (24 MHz for USB)

M24X0 F19 O Crystal output for M24 oscillator

M24V

PLLV

DD18

F16 S 1.8V power supply for M24 oscillator F17 GND Ground for M24 oscillator

M2 S 1.8 Volt power supply for PLLs (system and USB)

USB_VBUS J17 A I/O 5V input that signifies that VBUS is connected

USB_ID J16 A I/O pin to ground (V

USB_DP G19 A I/O

USB_DM H19 A I/O

USB_R1 H18 A I/O

USB_V

SSREF

USB_V

DDA3P3

USB_V

SSA3P3

USB_V

DD1P8

USB_V

SS1P8

USB_V

DDA1P2LDO

USB_V

SSA1P2LDO

G16 GND Ground for reference current.

J19 S Analog 3.3 V power supply for USB phy

J18 GND Analog ground for USB phy H17 S 1.8 V I/O power supply for USB phy H16 GND I/O Ground for USB phy

G18 S

G17 GND

IPD/

(1)

(2)

IPU

DESCRIPTION

USB 2.0

USB operating mode identification pin. For Host mode operation, pull down this

) via an external 1.5-k Ω resistor. For Device mode operation,

pull up this pin to DV

rail via an external 1.5-k Ω resistor.

DD33

USB bi-directional Data Differential signal pair [positive/negative].

Reference current output. This must be connected via a 10 k Ω ± 1% resistor to USB_V

SSREF

Core Power supply LDO output for USB phy. This must be connected via 1 µF capacitor to USB_V

SSA1P2LDO

. Do not connect this to other supply pins.

Core Ground for USB phy. This must be connected via 1 µF capacitor to USB_V

DDA1P2LDO

Device Overview 41

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Table 2-22. VLYNQ Terminal Functions

SIGNAL

NAME NO.

EM_CS5/ Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

GPIO8/ T1 I/O/Z IPD NAND flash.

VLYNQ_CLOCK For GPIO, it is GPIO pin 8 GPIO8

EM_CS4/ Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

GPIO9/ T2 I/O/Z IPD NAND flash.

VLYNQ_SCRUN For GPIO, it is GPIO9.

EM_A[15]/

GPIO16/ P3 I/O/Z IPD

VLYNQ_TXD3

EM_A[17]/

GPIO14/ R2 I/O/Z IPD

VLYNQ_TXD2

EM_A[19]/

GPIO12/ R4 I/O/Z IPD

VLYNQ_TXD1

EM_A[21]/

GPIO10/ T3 I/O/Z IPD

VLYNQ_TXD0

EM_A[14]/

GPIO17/ P4 I/O/Z IPD

VLYNQ_RXD3

EM_A[16]/

GPIO15/ R5 I/O/Z IPD

VLYNQ_RXD2

EM_A[18]/

GPIO13/ P5 I/O/Z IPD

VLYNQ_RXD1

EM_A[20]/

GPIO11/ R3 I/O/Z IPD

VLYNQ_RXD0

TYPE

IPD/

(1)

(2)

IPU

VLYNQ

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

For VLYNQ, it is the clock (VLYNQ_CLOCK).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

For VLYNQ, it is the Serial Clock run request (VLYNQ_SCRUN).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.

DESCRIPTION

address bit 15 output EM_A[15].

For GPIO, it is GPIO16.

address bit 17 output EM_A[17].

For GPIO, it is GPIO14.

address bit 19 output EM_A[19].

For GPIO, it is GPIO12.

address bit 21 output EM_A[21].

For GPIO, it is GPIO10.

address bit 14 output EM_A[14].

For GPIO, it is GPIO17.

address bit 16 output EM_A[16].

For GPIO, it is GPIO15.

address bit 18 output EM_A[18].

For GPIO, it is GPIO13.

address bit 20 output EM_A[20].

For GPIO, it is GPIO11.

SIGNAL

NAME NO.

PCLK M19 I

VD L19 I/O/Z

42 Device Overview

Table 2-23. VPFE Terminal Functions

IPD/

(1)

TYPE

(2)

IPU

VIDEO/IMAGE IN (VPFE)

Pixel clock input used to load image data into the CCD Controller (CCDC) on pins

Vertical synchronization signal that can be either an input (slave mode) or an

output (master mode), which signals the start of a new frame to the CCDC.

DESCRIPTION

CI[7:0] and YI[7:0].

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-23. VPFE Terminal Functions (continued)

SIGNAL

NAME NO.

HD M18 I/O/Z

CI7/ In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD15.

CCD15/ N19 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7 inputs.

UART_RXD2 In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the

CI6/ AFE mode, it is input CCD14.

CCD14/ N18 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6 inputs.

UART_TXD2 In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the

CI5/ In 16-bit CCD AFE mode, it is input CCD13.

CCD13/ N17 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB5 and CR5 inputs.

UART_CTS2 In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the

CI4/ In 16-bit CCD AFE mode, it is input CCD12.

CCD12/ N16 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB4 and CR4 inputs.

UART_RTS2 In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the

CI3/

CCD11

CI2/

CCD10

CI1/

CCD9

CI0/

CCD8

YI7/

CCD7

YI6/ In 16-bit CCD AFE mode, it is input CCD6.

CCD6 In 16-bit YCbCr mode, it is input Y6.IPDIn 8-bit YCbCr mode, it is time multiplexed

N15 I IPD In 16-bit YCbCr mode, it is time multiplexed between CB3 and CR3 inputs.

M17 I IPD In 16-bit YCbCr mode, it is time multiplexed between CB2 and CR2 inputs.

M16 I IPD In 16-bit YCbCr mode, it is time multiplexed between CB1 and CR1 inputs.

M15 I IPD In 16-bit YCbCr mode, it is time multiplexed between CB0 and CR0 inputs.

L18 I IPD In 16-bit YCbCr mode, it is input Y7.

L17 I IPD

TYPE

IPD/

(1)

(2)

IPU

Horizontal synchronization signal that can be either an input (slave mode) or an

output (master mode), which signals the start of a new line to the CCDC.

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

When used by UART2 it is the receive data input UART_RXD2.

When used by the CCDC as input CI6, it supports several modes. In 16-bit CCD

In UART2 mode, it is the transmit data output UART_TXD2.

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

In UART2 mode, it is the clear to send input UART_CTS2.

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

In UART2 mode, it is the ready to send output UART_RTS2.

This pin is CCDC input CI3 and it supports several modes. In 16-bit CCD AFE

In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the

This pin is CCDC input CI2 and it supports several modes. In 16-bit CCD AFE

In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the

This pin is CCDC input CI1 and it supports several modes.

In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the

This pin is CCDC input CI0 and it supports several modes.

In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the

This pin is CCDC input YI7 and it supports several modes.

In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the

This pin is CCDC input YI6 and it supports several modes.

as input CI7, it supports several modes.

This pin is multiplexed between the CCDC and UART2.

as input CI5, it supports several modes.

as input CI4, it supports several modes.

In 16-bit CCD AFE mode, it is input CCD9.

In 16-bit CCD AFE mode, it is input CCD8.

In 16-bit CCD AFE mode, it is input CCD7.

between Y6, CB6, and CR6 of the lower 8-bit channel.

DESCRIPTION

upper 8-bit channel.

mode, it is input CCD11.

upper 8-bit channel.

mode, it is input CCD10.

upper 8-bit channel.

lower 8-bit channel.

Device Overview 43

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SIGNAL

NAME NO.

YI5/

CCD5

YI4/

CCD4

YI3/

CCD3

YI2/

CCD2

YI1/

CCD1

YI0/

CCD0

GPIO1/

C_WE

GPIO4/

R0/ B14 I/O/Z IPD

C_FIELD

Table 2-23. VPFE Terminal Functions (continued)

IPD/

(1)

TYPE

L16 I IPD In 16-bit YCbCr mode, it is input Y5.

L15 I IPD In 16-bit YCbCr mode, it is input Y4.

K19 I IPD In 16-bit YCbCr mode, it is input Y3.

K18 I IPD In 16-bit YCbCr mode, it is input Y2.

K17 I IPD In 16-bit YCbCr mode, it is input Y1.

K16 I IPD In 16-bit YCbCr mode, it is input Y0.

E13 I/O/Z IPD pin GPIO1.

(2)

IPU

This pin is CCDC input YI5 and it supports several modes. In 16-bit CCD AFE

In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the

This pin is CCDC input YI4 and it supports several modes.

In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD4.

In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the

This pin is CCDC input YI3 and it supports several modes.

In 16-bit CCD AFE mode, it is input CCD3.

In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the

This pin is CCDC input YI2 and it supports several modes.

In 16-bit CCD AFE mode, it is input CCD2.

In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the

This pin is CCDC input YI1 and it supports several modes.

In 16-bit CCD AFE mode, it is input CCD1.

In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the

This pin is CCDC input YI0 and it supports several modes.

In 16-bit CCD AFE mode, it is input CCD0.

In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the

This pin is multiplexed between GPIO and the VPFE. In GPIO mode, it is GPIO

In VPFE mode, it is the CCD Controller write enable input C_WE.

This pin is multiplexed between GPIO, the VPFE, and the VPBE. In GPIO mode, it

In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD.

In VPBE mode, it is RGB888 Red data bit 0 output R0.

DESCRIPTION

mode, it is input CCD5.

lower 8-bit channel.

is GPIO pin GPIO4.

SIGNAL

NAME NO.

HSYNC C17 I/O/Z IPD VPBE Horizontal Synch Output VSYNC C18 I/O/Z IPD VPBE Vertical Synch Output

VCLK D19 I/O/Z IPD VPBE Clock Output

VPBECLK C19 I/O/Z IPD VPBE Clock Input

COUT0/

B3/ A16 I/O/Z IPD

BTSEL0

44 Device Overview

Table 2-24. VPBE Terminal Functions

(1)

TYPE

IPD/

(2)

IPU

VIDEO OUT (VPBE)

These pins are multiplexed between ARM boot mode and the VPBE. At

reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to

determine the ARM boot configuration. See below for the boot modes set

by these inputs. See the Bootmode section for more details.

After reset, these are video encoder outputs COUT0 and COUT1, or

RGB666/888 Blue output data bits 3 and 4 B3/B4.

DESCRIPTION

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-24. VPBE Terminal Functions (continued)

SIGNAL

NAME NO.

COUT1/

B4/ B16 I/O/Z IPD 0 1 ARM EMIFA Boot (NOR)

BTSEL1

COUT2/

B5/ A17 I/O/Z IPD

EM_WIDTH

COUT3/

B6/ B17 I/O/Z IPD

DSP_BT

COUT4/

COUT5/

COUT6/

COUT7/

YOUT0/

G5/ D15 I/O/Z IPD

AEAW0

YOUT1/

G6/ D16 I/O/Z IPD

AEAW1

YOUT2/ input states of AEAW[4:0] are sampled to set the EMIFA address bus

G7/ D17 I/O/Z IPD width. See the Peripheral Selection at Device Reset section for details.

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 YOUT3/

R3/ D18 I/O/Z IPD

AEAW3

YOUT4/

R4/ E15 I/O/Z IPD

AEAW4

YOUT5/

YOUT6/

YOUT7/

GPIO0/

LCD_OE

GPIO2/

GPIO3/

B0/ C14 I/O/Z IPD

LCD_FIELD

A18 I/O/Z IPD Video encoder output COUT4 or RGB666/888 Blue data bit 7 output B7.

B18 I/O/Z IPD Video encoder output COUT5 or RGB666/888 Green data bit 2 output G2.

B19 I/O/Z IPD Video encoder output COUT6 or RGB666/888 Green data bit 3 output G3.

C16 I/O/Z IPD Video encoder output COUT7 or RGB666/888 Green data bit 4 output G4.

E16 I/O/Z IPD Video encoder output YOUT5 or RGB666/888 Red data bit 5 output R5.

E17 I/O/Z IPD Video encoder output YOUT6 or RGB666/888 Red data bit 6 output R6.

E18 I/O/Z IPD Video encoder output YOUT7 or RGB666/888 Red data bit 7 output R7.

C13 I/O/Z IPD GPIO pin GPIO0.

D13 I/O/Z IPD GPIO pin GPIO2.

(1)

TYPE

IPD/

(2)

IPU

BTSEL1 BTSEL0 ARM Boot Mode

0 0 ARM ROM Boot (NAND) [default]

1 0 Reserved 1 1 ARM ROM Boot (UART)

This pin is multiplexed between EMIFA and the VPBE. At reset, the input

state is sampled to set the EMIFA data bus width (EM_WIDTH). For an

8-bit wide EMIFA data bus, EM_WIDTH = 0 [default]. For a 16-bit wide

After reset, it is video encoder output COUT2 or RGB666/888 Blue output

This pin is multiplexed between DSP boot and the VPBE. At reset, the

input state is sampled to set the DSP boot source DSP_BT. The DSP is

booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when

After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit

These pins are multiplexed between EMIFA and the VPBE. At reset, the

Red and Green data bit outputs G5, G6, G7, R3, and R4.

This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is

In VPBE mode, it is the LCD output enable LCD_OE.

This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is

In VPBE mode, it is RGB888 Green data bit 0 output G0.

This pin is multiplexed between GPIO, and the VPBE. In GPIO mode, it is

In VPBE mode, it is RGB888 Blue data bit 0 output B0.

EMIFA data bus, EM_WIDTH = 1.

or LCD interlaced output LCD_FIELD.

DESCRIPTION

data bit 5 B5.

DSP_BT=1. 6 output B6.

GPIO pin GPIO3.

Device Overview 45

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TMS320DM6446 Digital Media System on-Chip

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SIGNAL

NAME NO.

GPIO4/

R0/ B14 I/O/Z IPD

C_FIELD

GPIO5/

GPIO6/

GPIO38/

PWM1/

R2/ B15 I/O/Z IPD

GPIO46

PWM2/

B2/ A15 I/O/Z IPD

GPIO47

Table 2-24. VPBE Terminal Functions (continued)

(1)

TYPE

E14 I/O/Z IPD GPIO pin GPIO5.

A14 I/O/Z IPD GPIO pin GPIO6.

D14 I/O/Z IPD is GPIO38.

IPD/

(2)

IPU

This pin is multiplexed between GPIO, the VPFE, and the VPBE. In GPIO

In VPBE mode, it is RGB888 Red data bit 0 output R0.

In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD.

This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is

In VPBE mode, it is RGB888 Green data bit 1 output G1.

This pin is multiplexed between GPIO and the VPBE. In GPIO mode, it is

In VPBE mode, it is RGB888 Blue data bit 1 output B1.

This pin is multiplexed between VPBE and GPIO. When used by GPIO, it

In VPBE mode, it is RGB888 Red output data bit 1.

This pin is multiplexed between PWM1, VPBE, and GPIO. For PWM1, it is

In VPBE mode, it is RGB888 Red output bit 2 (R2).

This pin is multiplexed between PWM2, VPBE, and GPIO. For PWM2, it is

In VPBE mode, it is RGB888 Blue output bit 2 (B2).

mode, it is GPIO pin GPIO4.

For GPIO, it is GPIO46.

For GPIO, it is GPIO47.

DESCRIPTION

output PWM1.

output PWM2.

SIGNAL

NAME NO.

DAC_VREF R17 A I Reference voltage input (0.5 V) DAC_IOUT_A P19 A O Output of DAC A DAC_IOUT_B P18 A O Output of DAC B DAC_IOUT_C R19 A O Output of DAC C DAC_IOUT_D T19 A O Output of DAC D

DDA_1P8V

SSA_1P8V

DDA_1P1V

SSA_1P1V

DAC_RBIAS R16 A I

R18 S 1.8 V Analog I/O power P17 GND Analog I/O ground P16 S 1.20 V Analog core supply voltage (-594 device) T18 GND Analog core ground

Table 2-25. DAC [Part of VPBE] Terminal Functions

IPD/

(1)

TYPE

(2)

IPU

DAC[A:D]

External resistor connection for current bias configuration. This must be connected

DESCRIPTION

via a 4 k Ω resistor to V

SSA_1P8V

Device Overview46

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Table 2-26. UART0, UART1, UART2 Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

SIGNAL

NAME NO.

CI7/ In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD15.

CCD15/ N19 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7 inputs.

UART_RXD2 In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the

CI6/ AFE mode, it is input CCD14.

CCD14/ N18 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6 inputs.

UART_TXD2 In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the

CI5/ In 16-bit CCD AFE mode, it is input CCD13.

CCD13/ N17 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB5 and CR5 inputs.

UART_CTS2 In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the

CI4/ In 16-bit CCD AFE mode, it is input CCD12.

CCD12/ N16 I/O/Z IPD In 16-bit YCbCr mode, it is time multiplexed between CB4 and CR4 inputs.

UART_RTS2 In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the

DMACK/

UART_TXD1

DMARQ/

UART_RXD1

UART_RXD0/

GPIO35

UART_TXD0/

GPIO36

TYPE

H3 I/O/Z IPD acknowledge output DMACK.

G1 I/O/Z IPD request DMARQ input.

D5 I/O/Z IPD input UART_RXD0.

C5 I/O/Z IPD output UART_TXD0.

IPD/

(1)

(2)

IPU

UART2

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

When used by UART2 it is the receive data input UART_RXD2.

When used by the CCDC as input CI6, it supports several modes. In 16-bit CCD

In UART2 mode, it is the transmit data output UART_TXD2.

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

In UART2 mode, it is the clear to send input UART_CTS2.

This pin is multiplexed between the CCDC and UART2. When used by the CCDC

In UART2 mode, it is the ready to send output UART_RTS2.

UART1

This pin is multiplexed between ATA/CF and UART1. For ATA/CF, it is DMA

UART0

This pin is multiplexed between UART0 and GPIO. For UART0, it is Receive Data

This pin is multiplexed between UART0 and GPIO. For UART0, it is Transmit Data

as input CI7, it supports several modes.

This pin is multiplexed between the CCDC and UART2.

as input CI5, it supports several modes.

as input CI4, it supports several modes.

For UART1, it is transmit data output UART_TXD1.

For UART1, it is receive data input UART_RXD1.

DESCRIPTION

upper 8-bit channel.

For GPIO, it is GPIO35.

For GPIO, it is GPIO36.

Table 2-27. PWM0, PWM1, PWM2 Terminal Functions

SIGNAL

NAME NO.

PWM2/

B2/ A15 I/O/Z IPD

GPIO47

TYPE

IPD/

(1)

(2)

IPU

PWM2

This pin is multiplexed between PWM2, VPBE, and GPIO. For PWM2, it is output

For the VPBE, it is RGB888 Blue output bit 2 (B2).

PWM1

DESCRIPTION

PWM2.

For GPIO, it is GPIO47.

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Table 2-27. PWM0, PWM1, PWM2 Terminal Functions (continued)

SIGNAL

NAME NO.

PWM1/

R2/ B15 I/O/Z IPD

GPIO46

PWM0/ This pin is multiplexed between PWM0 and GPIO. For PWM0, it is output PWM0.

GPIO45 For GPIO, it is GPIO45.

C15 I/O/Z IPD

TYPE

IPD/

(1)

(2)

IPU

This pin is multiplexed between PWM1, VPBE, and GPIO. For PWM1, it is output

Table 2-28. ATA/CF Terminal Functions

DESCRIPTION

PWM1.

For the VPBE, it is RGB888 Red output bit 2 (R2).

For GPIO, it is GPIO46.

PWM0

SIGNAL

NAME NO.

SPI_EN1/

HDDIR/ B2 I/O/Z IPD

GPIO42

GPIO50/ This pin is multiplexed between GPIO and ATA/CF. In GPIO mode, it is GPIO50.

ATA_CS0 In ATA mode, it is ATA/CF chip select output ATA_CS0.

GPIO51/ This pin is multiplexed between GPIO and ATA/CF. In GPIO mode, it is GPIO51.

ATA_CS1 In ATA mode, it is ATA/CF chip select output ATA_CS1.

EM_R/ W/

INTRQ

EM_WAIT/

(RDY/ BSY)/ F1 I IPD

IORDY

EM_OE/

( RE)/

( IORD)/

DIOR

EM_WE

( WE)

( IOWR)/

DIOW

DMACK/

UART_TXD1

DMARQ/

UART_RXD1

J5 O IPD

H1 O IPD

G3 I IPD read/write output EM_R/ W.

H4 O IPD For NAND/SmartMedia/xD, it is read enable output ( RE).

G2 O IPD For NAND/SmartMedia/xD, it is write enable output ( WE).

H3 O IPD acknowledge output DMACK.

G1 O IPD request DMARQ input.

TYPE

(2)

IPU

ATA/CF

This pin is multiplexed between SPI, ATA, and GPIO. When used by SPI, it is SPI

This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, it is EMIF

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

For NAND/SmartMedia/xD, it is ready/busy input (RDY/ BSY).

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

This pin is multiplexed between ATA/CF and UART1. For ATA/CF, it is DMA

slave device 1 enable output SPI_EN1.

For ATA, it is buffer direction control output HDDIR.

For ATA/CF, it is interrupt request input INTRQ.

EMIFA, it is wait state extension input EM_WAIT.

For ATA/CF, it is IO Ready input IORDY.

EMIFA, it is output enable output EM_OE.

For CF, it is read strobe output ( IORD). For ATA, it is read strobe output DIOR.

EMIFA, it is write enable output EM_WE.

For CF, it is write strobe output ( IOWR). For ATA, it is write strobe output DIOW.

For UART1, it is transmit data output UART_TXD1.

For UART1, it is receive data input UART_RXD1.

DESCRIPTION

For GPIO, it is GPIO42.

IPD/

(1)

48 Device Overview

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 2-28. ATA/CF Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D15/

DD15

EM_D14/

DD14

EM_D13/

DD13

EM_D12/

DD12

EM_D11/

DD11

EM_D10/

DD10

EM_D9/

DD9

EM_D8/

DD8

EM_D7/

DD7

EM_D6/

DD6

EM_D5/

DD5

EM_D4/

DD4

EM_D3/

DD3

EM_D2/

DD2

EM_D1/

DD1

EM_D0/

DD0

EM_A[0]/ address. When connected to a 16-bit asynchronous memory, this pin is the 2nd bit

DA2/ J4 I/O/Z IPD of the address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the

GPIO53 address.

EM_BA[1]/

DA1/ H2 I/O/Z IPD

GPIO52

EM_BA[0]/ this pin is the lowest order bit of the byte address. When connected to a 16-bit

DA0 asynchronous memory, this pin has the same function as EMIF address pin 22

TYPE

I/O/Z IPD

J3 I/O/Z IPD

IPD/

(1)

(2)

IPU

These pins are multiplexed between EMIFA (NAND) and ATA/CF. In all cases

they are used as a 16 bit bi-directional data bus. For EMIFA (NAND), these are

For ATA/CF, these are DD[15:0].

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is

Address output EM_A[0], which is the least significant bit on a 32-bit word

For ATA/CF, it is Device address bit 2 output DA2.

This pin is multiplexed between EMIFA, ATA/CF, and GPIO. For EMIFA, this is

the Bank Address 1 output EM_BA[1]. When connected to a 16 bit asynchronous

memory this pin is the lowest order bit of the 16-bit word address. When

connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address.

This pin is multiplexed between EMIFA and ATA/CF. For EMIFA, this is the Bank Address 0 output EM_BA[0]. When connected to an 8-bit asynchronous memory,

For ATA/CF, it is Device address bit 1 output DA1.

For ATA/CF, it is Device address bit 0 output DA0.

DESCRIPTION

EM_D[15:0].

In GPIO mode, it is GPIO53.

In GPIO mode, it is GPIO52.

EM_A[22].

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Table 2-29. MMC/SD Terminal Functions

SIGNAL

NAME NO.

SD_CLK A9 O IPD Data clock output SD_CLK

SD_CMD B9 O IPD Command IO output SD_CMD SD_DATA3 C9 I/O/Z IPD SD_DATA2 D9 I/O/Z IPD SD_DATA1 E9 I/O/Z IPD SD_DATA0 D8 I/O/Z IPD

TYPE

IPD/

(1)

(2)

IPU

MMC/SD

These pins are the nibble wide bi-directional data bus SD_DATA[3:0].

DESCRIPTION

Table 2-30. Timer 0, Timer 1, and Timer 2 Terminal Functions

SIGNAL

NAME NO.

No external pins. The Timer 2 and Timer 1 peripheral pins are not pinned out as external pins.

CLK_OUT1/ the USB clock generator, it is clock output CLK_OUT1. This is configurable for 12

TIM_IN/ E19 I/O/Z IPD MHz or 24 MHz clock outputs. GPIO49 For Timer0, it is the timer event capture input TIM_IN.

TYPE

IPD/

(1)

(2)

IPU

Timer 2 and Timer 1

Timer 0

This pin is multiplexed between the USB clock generator, timer, and GPIO. For

DESCRIPTION

For GPIO, it is GPIO49.

SIGNAL

NAME NO.

RSV1 A1 Reserved. This pin should not be connected. RSV2 A19 Reserved. This pin should not be connected. RSV3 W1 Reserved. This pin should not be connected. RSV4 W19 Reserved. This pin should not be connected. RSV5 D4 I IPD Reserved. This pin must be tied directly to V RSV6 L3 A O Reserved. This pin should not be connected. RSV7 R8 A Reserved. This pin should not be connected.

(1) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) (2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

Table 2-31. Reserved Terminal Functions

IPD/

(1)

TYPE

(2)

IPU

RESERVED

DESCRIPTION

for normal device operation.

Device Overview50

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Table 2-32. Supply Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

SIGNAL

NAME NO.

F10

DD33

DD18

DDR2

F11 F12 F13

G15 F14

J15 H14 K14

M14

L13

P10 N11 R11 P12 N13 R13 P14 R15

TYPE

F8 E7 G7

F6 H6 K6 M6

T5 P6 N7 P8 N9 R9

IPD/

(1)

(2)

IPU

SUPPLY VOLTAGE PINS

3.3 V I/O supply voltage (see the Power-Supply Decoupling section of this data sheet)

1.8 V I/O supply voltage (see the Power-Supply Decoupling section of this data sheet)

1.8 V DDR2 I/O supply voltage (see the Power-Supply Decoupling section of this data sheet)

DESCRIPTION

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SIGNAL

NAME NO.

DDDSP

F15 K12

M12

L11

M10

L10

K10

L8 M8

J13 H12 H11

J11 K11

J10 S H10

J9 K9 K8 H8

Table 2-32. Supply Terminal Functions (continued)

IPD/

(1)

TYPE

(2)

IPU

1.20 V core supply voltage (-594 device) (see the Power-Supply Decoupling section of this data sheet)

1.20 V DSPSS supply voltage (-594 devices) (see the Power-Supply Decoupling section of this data sheet)

DESCRIPTION

Device Overview52

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Table 2-33. Ground Terminal Functions

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

SIGNAL

NAME NO.

G10 N10 R10 G11

M11

P11 G12

J12

N12

L12 R12 G13 H13 K13

M13

P13 G14

J14

TYPE

K5 M5 G6

L6 N6 R6

F7 H7 K7 M7 P7 R7 E8 G8

J8 N8

F9 H9 M9 GND Ground pins P9

IPD/

(1)

(2)

IPU

GROUND PINS

DESCRIPTION

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SIGNAL

NAME NO.

2.8 Device Support

2.8.1 Development Support

TI offers an extensive line of development tools for the TMS320DM644x SoC platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Intergrated Development Environment (IDE).

The following products support development of TMS320DM644x SoC-based applications:

Table 2-33. Ground Terminal Functions (continued)

IPD/

(1)

TYPE

L14 N14 R14 H15 K15 P15

GND Ground pins

(2)

IPU

DESCRIPTION

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target

software needed to support any SoC application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator (supports TMS320DM644x SoC multiprocessor system debug) EVM (Evaluation Module)

For a complete listing of development-support tools for the TMS320DM644x SoC platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

2.8.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320DM6446ZWT). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical

specifications.

TMP Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

TMS Fully-qualified production device. Support tool development evolutionary flow:

54 Device Overview

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DM644x DSP:

DM6443 DM6446

PREFIX DEVICE SPEED RANGE

TMX 320 DM6446 ZWT ( )

TMX= Experimental device TMS= Qualified device

DEVICE FAMILY

320 = TMS320 DSP family

PACKAGE TYPE

(A)

ZWT = 361-pin plastic BGA, with Pb-free soldered balls

DEVICE

(B)

TEMPERATURE RANGE (DEFAULT: 0°C TO 85°C)

( )

Blank = 0°C to 85°C, commercial temperature

Blank = 594-MHz DSP, 297−MHz ARM9 [Default]

A. BGA = Ball Grid Array B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com).

( )

SILICON REVISION

Blank = Initial Silicon 1.0

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default [594-MHz DSP, 297-MHz ARM9]).

Figure 2-7 provides a legend for reading the complete device name for any TMS320DM644x SoC platform

member.

Figure 2-7. Device Nomenclature

2.8.3 Documentation Support

2.8.3.1 Related Documentation From Texas Instruments

The following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM644x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

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SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM

SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signal

SPRUE19 TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overview

SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas

SPRU732 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU

subsytem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem, the video processing subsystem, and a majority of the peripherals and external memories.

processor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

and briefly describes the peripherals available on the TMS320DM644x Digital Media System-on-Chip (DMSoC).

Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital

signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRAAA6 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating

from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.

Device Overview56

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Digital Media System on-Chip

SPRS283 – DECEMBER 2005

3 Device Configuration

3.1 System Module Registers

The system module includes status and control registers required for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1 . System Module registers required for device configurations are discussed in the following sections.

Table 3-1. System Module Register Memory Map

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x01C4 0000 PINMUX0 Pin multiplexing control 0. See Section 3.6.4 for details. 0x01C4 0004 PINMUX1 Pin multiplexing control 1. See Section 3.6.5 for details. 0x01C4 0008 DSPBOOTADDR Boot address of DSP. See Section 3.4.1.2 for details. 0x01C4 000C SUSPSRC Emulator Suspend Source. See Section 3.7 for details. 0x01C4 0010 INTGEN ARM/DSP Interrupt Status and Control. See ARM/DSP

Communucations Interrupts section for details. 0x01C4 0014 BOOTCFG Device boot configuration. See Section 3.4.1.1 for details. 0x01C4 0018 - 0x01C4 0027 – Reserved 0x01C4 0028 DEVICE_ID Device ID number. See the JTAG section for details. 0x01C4 002C – Reserved 0x01C4 0030 – Reserved 0x01C4 0034 USBPHY_CTL USB PHY control. See the USB peripheral section for details. 0x01C4 0038 CHP_SHRTSW Chip shorting switch control. See Section 3.2.1 for details. 0x01C4 003C MSTPRI0 Bus master priority control 0. See Section 3.6.1 for details. 0x01C4 0040 MSTPRI1 Bus master priority control 1. See Section 3.6.1 for details. 0x01C4 0044 VPSS_CLKCTL VPSS clock control. 0x01C4 0048 VDD3P3V_PWDN VDD 3.3V I/O powerdown control. See Section 3.2.2 for details. 0x01C4 004C DRRVTPER Enables access to the DDR2 VTP Register 0x01C4 0050 - 0x01C4 006F – Reserved

TMS320DM6446

3.2 Power Considerations

Global device power domains are controlled by the Power and Sleep Controller, except as shown in the following sections.

3.2.1 Power Configurations at Reset

As described in the DM6446 Power and Clock Domains section, the DM6446 has two power domains: Always On and DSP. There is a shorting switch between the two power domains that must be opened when the DSP domain is powered off and closed when the DSP domain is powered on.

The CHP_SHRTSW register, shown in Figure 3-1 , controls the shorting switch between the device always-on and DSP power domains. This switch should be enabled after powering-up the DSP domain. Setting the DSPPWRON bit to '1’ closes (enables) the switch and enables the DSP power domain. The default switch value is determined by the DSP_BT configuration input. If DSP self boot is selected (DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of '1'. For ARM boot operation (DSP_BT=0), DSPPWRON will be set to the disable value of '0' and must be set by the ARM before the DSP domain power is turned on.

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Figure 3-1. CHP_SHRTSW Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-0000 0000 0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PWR

R-0000 0000 0000 000 R/W-L

LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising

Table 3-2. CHP_SHRTSW Register Description

NAME DESCRIPTION

DSPPWRON DSP power domain enable.

0 = DSP power domain off 1 = DSP power domain on

3.2.2 Power Configurations after Reset

DSP

The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD and GPIOV33. The

3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and described in

Table 3-3 . By default, these pins are all disabled at reset.

The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD and GPIOV33. The

3.3V I/Os are separated into two groups for independent control as shown in Figure 3-2 and described in

Table 3-3 . By default, these pins are all disabled at reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LEGEND: R = Read, W = Write, n = value at reset

NAME DESCRIPTION

IOPWDN0 MMC/SD I/O Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins.

0 = I/O buffers powered up 1 = I/O buffers powered down

IOPWDN1 GIOV33 I/O Powerdown controls GIOV33[16:0] pins.

0 = I/O buffers powered up 1 = I/O buffers powered down

Figure 3-2. VDD3P3V_PWDN Register

RESERVED

R-0000 0000 0000 0000

RESERVED

R-0000 0000 0000 00 R/W-1 R/W-1

Table 3-3. VDD3P3V_PWDN Register Description

IO IO

PWDN1 PWDN0

3.3 Clocks Considerations

Global device and local peripheral clocks are controlled by the Power and Sleep Controller, except as shown in the following sections.

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

3.3.1 Clock Configurations at Reset

TBD

3.3.2 Clock Configurations after Power-On/Hard Reset

As described in the DM6446 Power and Clock Domains section, the DM6446 system includes two separate power domains and up to forty-one separate modules. The "AlwaysOn" power domain is always on when the chip is on. The "AlwaysOn" domain is powered by the CV majority of the DM6446 modules lie within the "AlwaysOn" power domain. The DSP Subsystem lies in a separate domain that is not always on. This domain is referred to as the "DSP" domain. The DSP power domain is powered by the CV

pin of the device.

DDDSP

Table 3-4 shows the state of each module after a chip Power-On/Hard Reset. The default state of the

"DSP" power domain and the DSP module is determined by the DSP boot select pin (COUT3/B6/ DSP_BT). If the DSP is selected to self boot (COUT3/B6/ DSP_BT = 1) at reset, the "DSP" domain will power up by default.

Table 3-4. Module Configuration

DEFAULT STATES

MODULE POWER DOMAIN POWER MODULE STATE LOCAL RESET STATE

NAME DOMAIN

VPSS Always On ON Disable -

EDMA Always On ON BTSEL[1:0] = 00 - Enable (NAND) -

USB2.0 Always On ON Disable -

ATA/CF Always On ON Disable -

VLNYQ Always On ON Disable -

DDR2 EMIF Always On ON Disable -

EMIFA Always On ON BTSEL[1:0] = 00 - Enable (NAND) -

MMC/SD Always On ON Disable -

ASP Always On ON Disable -

I2C Always On ON Disable -

UART0 Always On ON BTSEL[1:0] = 00 - SyncRst (NAND) -

UART1 Always On ON Disable UART2 Always On ON Disable -

SPI Always On ON Disable PWM0 Always On ON Disable PWM1 Always On ON Disable PWM2 Always On ON Disable -

GPIO Always On ON Disable TIMER0 Always On ON Enable TIMER1 Always On ON Disable TIMER2 Always On ON Enable -

EMAC/MDIO Always On ON Disable -

STATE

BTSEL[1:0] = 01 - Enable (NOR)

BTSEL[1:0] = 10 - Reserved

BTSEL[1:0] = 11- Enable (UART)

BTSEL[1:0] = 01 - Enable (NOR)

BTSEL[1:0] = 10 - Reserved

BTSEL[1:0] = 11- Enable (UART)

BTSEL[1:0] = 01 - SyncRst (NOR)

BTSEL[1:0] = 10 - Reserved

BTSEL[1:0] = 11- Enable (UART)

pin of the DM6446 chip. The

MODULE

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Table 3-4. Module Configuration (continued)

DEFAULT STATES

System Always On ON Enable Module

ARM Always On ON Enable -

Switched Always On ON Enable -

Central

Resource

(SCR)

DSP DSP OFF COUT3_DSP_BT COUT3_DSP_BT VICP DSP OFF Disable -

3.3.2.1 Power Domain and Module States Defined

3.3.2.1.1 Power Domain States

A power domain can only be in one of two states – ON or OFF, defined as follows:

• ON: Power to the power domain is on.

• OFF: Power to the power domain is off.

3.3.2.1.2 Module States

A module can be in one of four states – Disable, Enable, SwRstDisable, or SyncReset. As shown in

Table 3-5 , the four states correspond to combinations of module reset asserted or de-asserted and

module clock on or off.

MODULE STATE MODULE RESET MODULE CLOCK

Enable De-Asserted ON

Disable De-Asserted OFF

SyncReset Asserted ON

SwRstDisable Asserted OFF

The module states are defined as follows:

• Enable: A module in the enable state has its module reset de-asserted and its clock on.

• Disable: A module in the disable state has its module reset de-asserted and its clock off. This state

is typically used for disabling a module clock for power savings. The DM6446 is designed in full static CMOS, so when you stop a module clock, the modules state is retained. When the clock is restarted, the module resumes operating from the point it was stopped.

• SyncRst: A module in the SyncRst state has its module reset asserted and its clock on. After initial power-on, most modules are by default in the SyncRst state.

• SwRstDisable: A module in the SwRstDisable state has its module reset asserted and its clock off.

3.3.2.2 DAC and Video Encoder Clocks

The DAC and Video Encoder Clocks within the Video Processing SubSystem (VPSS) are controlled via the VPSS_CLK_CTRL register as shown in Figure 3-3 . Descriptions of the register fields are given in

Table 3-6 .

Table 3-5. Module States

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Figure 3-3. VPSS_CLK_CTRL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-0000 0000 0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED VPSS_MUXSEL

R-0000 0000 000 R/W-0 R/W-0 R/W-0 R/W-00

LEGEND: R = Read, W = Write, n = value at reset

Table 3-6. VPSS_CLK_CTRL Register Description

Name Description

DACCLKEN Video DAC clock control

0 = DAC clock disabled 1 = DAC clock enabled

VENCLKEN Video Encoder clock control

0 = Video Encoder clock disabled 1 = Video Encoder clock enabled

PCLK_INV Video Encoder PCLK polarity control

0 = VENC clock mux and CCDC receives normal PCLK 1 = VENC clock mux and CCDC receives inverted PCLK

VPSS_MUXSEL Video Encoder and DAC clock selection

VPSS_MUXSEL [1:0] VENC Clock DAC Clock 00 MXI (27 MHz) MXI (27 MHz) 01 MXI x 2 (54 MHz) MXI x 2 (54 MHz) 10 VPBECLK input VPBECLK input 11 PCLK or inverted PCLK off

DAC VEN PCLK_I

CLKEN CLKEN NV

3.4 Bootmode

The device is booted through multiple means: pin states captured at reset, primary bootloaders within internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and register configurations required for booting the device, are described in the following sections.

3.4.1 Bootmode Registers

The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status of various pins required for proper boot are stored within these registers.

3.4.1.1 BOOTCFG Register Description

The BOOTCFG register (located at address 0x01C4 000A) contains the status values of the BTSEL1, BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pins captured at the rising edge of RESET. The register format is shown in Figure 3-4 and bit field descriptions are shown in Table 3-7 . The captured bits are software readable after reset.

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Figure 3-4. BOOTCFG Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-0000 0000 0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BTSEL DAEAW

R-0000 000 R-L R-LL R-L R-LLLLL

LEGEND: R = Read; W = Write; L = pin state latched at reset rising; - n = value after reset

Table 3-7. BOOTCFG Register Description

NAME DESCRIPTION

BTSEL ARM Boot mode selection pin states (BTSEL1, BTSEL0) captured at the rising edge of RESET.

‘00’ indicates ARM boots from ROM (NAND Flash). ‘01’ indicates that ARM boots from EMIFA (NOR Flash). ‘10’ RESERVED. ‘11’ indicates that ARM boots from ROM (UART).

DSP_BT DSP Boot mode selection pin state captured at the rising edge of RESET.

‘0’ sets ARM boot of C64x+. ‘1’ sets C64x+ self boot.

EM_WIDTH EMIFA data bus width selection pin state captured at the rising edge of RESET.

‘0’ sets EMIFA to 8 bit data bus width ‘1’ sets EMIFA to 16 bit data bus width.

DAEAW EMIFA address bus width selection pin states (AEAW[4:0]) captured at the rising edge of RESET. This configures

EMIFA address pins multiplexed with GPIO. See Table 3-12 ,Table 3-13 , and Table 3-14

DSP_ EM_

BT WIDTH

3.4.1.2 DSPBOOTADDR Register Description

The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register format is shown in Figure 3-5 and bit field descriptions are shown in Table 3-8 . DSPBOOTADDR is readable and writable by software after reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT BOOT ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR

21 20 19 18 17 16 15 14 13 12 11 10 19 8 7 6

R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOT BOOT BOOT BOOT BOOT BOOT ADDR ADDR ADDR ADDR ADDR ADDR RESERVED

5 4 3 2 1 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-00 0000 0000

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

NAME DESCRIPTION

BOOTADDR[21:0] Upper 22 bits of the C64x+ DSP boot address.

Figure 3-5. DSPBOOTADDR Registers

Table 3-8. DSPBOOTADDR Register Description

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3.4.2 ARM Boot

The DM6446 ARM can boot from EMIFA, internal ROM (NAND) or UART as determined by the setting of the BTSEL[1:0] pins. The BTSEL[1:0] pins are read by the ARM ROM Boot Loader (RBL) to further define the ROM boot mode. The ARM boot modes are summarized in Table 3-9 .

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Table 3-9. ARM Boot Modes

BTSEL1 BTSEL0 Boot Mode ARM Reset Brief Description

0 0 ARM NAND RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through NAND with up

0 1 ARM EMIFA External Boot 0x0200 0000 EMIFA EM_CS2 external memory space. 1 0 Reserved 0x0000 4000 Reserved 1 1 ARM UART RBL 0x0000 4000 Up to 14 K-bytes secondary boot loader through UART.

Vector

to 2 K-bytes page sizes.

When the BTSEL[1:0] pins are set to the ARM EMIFA External Boot ("01"), the ARM immediately begins executing code from the EMIFA EM_CS2 memory space (0x0200 0000). When the BTSEL[1:0] pins indicate a condition other than the ARM EMIFA External Boot (!01), the RBL begins execution.

ARM NAND Boot mode has the following features:

• No support for a full firmware boot. Instead, copies a secondary User Boot Loader (UBL) from NAND flash to ARM Internal RAM (AIM) and transfers control to the user software.

• Support for NAND with page sizes up to 2048 bytes.

• Support for error correction when loading UBL

• Support for up to 14KB UBL

• Optional, user selectable, support for use of DMA, I-cache, and PLL enable while loading UBL

ARM UART Boot mode has the following features:

• No support for a full firmware boot. Instead, loads a secondary UBL via UART to AIM and transfers control to the user software.

• Support for up to 14KB UBL

For further details on the ROM Bootloader, refer to the ARM Subsystem Users Guide.

3.4.3 DSP Boot

For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the MPU will be the master of C64x+ and control booting (Host Boot mode). If DSP_BT is high, the C64x+ will boot itself coming out of device reset (Self-Boot mode). Table 3-10 shows a summary of the DSP boot modes.

Table 3-10. DSP Boot Modes

DSP_BT DSP ARM DSPBOOTADDR Brief Description

Boot Mode Boot Mode Register Value

0 Host Boot Internal Boot Programmable ARM sets an internal DSP memory location in DSPBOOTADDR

register where valid DSP code resides and loads code to this internal DSP memory through DMA prior to releasing DSP reset.

0 Host Boot External Boot Programmable ARM sets an external DSP memory location in DSPBOOTADDR

1 Self Boot Any 0x4220 0000 Default EMIFA Base Address

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3.4.3.1 Host-Boot Mode

In host boot mode, the ARM is the master and controls the reset and boot of the C64x+. The C64x+ DSP remains powered-off after device reset. The ARM is responsible for enabling power to the C64x+ and releasing it from reset (PSC MMR bits: MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Prior to releasing the C64x+ reset, the ARM must program the address from which the C64x+ will begin execution in the DSPBOOTADDR register.

3.4.3.2 Self-Boot Mode

In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000) contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache enabled.

3.5 Configurations at Reset

The following sections give information on configuration settings for the device at reset.

3.5.1 Device Configuration at Device Reset

Table 3-11 shows a summary of device inputs required for booting the ARM and DSP, and configuring

EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET input.

Table 3-11. Device Configurations (Input Pins Sampled at Reset)

DEVICE SIGNALS

SAMPLED DESCRIPTION AT RESET

BTSEL[1:0] COUT[1:0] ARM Boot mode selection pins.

DSP_BT COUT3 DSP Boot mode selection pin.

EM_WIDTH COUT2 EMIFA data bus width selection pin.

AEAW[4:0] YOUT[4:0] EMIFA address bus width selection pins for EMIFA address pins multiplexed with GPIO.

DEVICE SIGNAL NAME

AFTER RESET

3.5.2 Peripheral Selection at Device Reset

As briefly mentioned in Table 3-11 , the state of the AEAW[4:0] pins captured at reset configures the number of EMIFA address pins required for device boot. These values are stored in the AEAW field of the PINMUX0 register. At reset, this provides proper addressing for external boot. Unused address pins are available for use as GPIO. The register settings are software programmable after reset. Table 3-12 ,

Table 3-13 , and Table 3-14 show the AEAW[4:0] bit settings and the corresponding multiplexing for

EMIFA address and GPIO pins.

‘00’ indicates ARM boots from ROM (NAND Flash). ‘01’ indicates that ARM boots from EMIFA (NOR Flash). ‘10’ Reserved. ‘11’ indicates that ARM boots from ROM (UART).

‘0’ sets ARM boot of C64x+. ‘1’ sets C64x+ self boot.

‘0’ sets EMIFA to 8-bit data bus width ‘1’ sets EMIFA to 16-bit data bus width.

See Table 3-12 , Table 3-13 , and Table 3-14 for details.

The number of EMIFA address bits enabled is configurable from 0 to 23. EM_BA[1] and EM_A[21:0] pins that are not assigned to another peripheral and not enabled as address signals become GPIO pins. The enabled address pins are always contiguous from EM_BA[1] upwards and address bits cannot be skipped.

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The exception to this are the EM_A[2:1] pins. EM_A[2:1] are usable as the ALE and CLE signals for the NAND Flash mode of EMIFA and are always enabled as EMIFA pins. If an address width of 0 is selected, this still allows a NAND Flash to be accessed. Also, selecting an address width of 2, 3, or 4 (AEAW[4:0] = 00010, 00011, or 00100) always results in 4 address outputs. For these and other address bit enable settings, see Table 3-12 , Table 3-13 , and Table 3-14 .

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Table 3-12. GPIO and EMIFA Multiplexing (Part 1)

Pin Mux Register AEAW[4:0] Bit Settings 00000 00001 00010 00011 00100 00101 00111 00111

(default)

GPIO[52] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] GPIO[53] GPIO[53] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[28] GPIO[28] GPIO[28] GPIO[28] GPIO[28] EM_A[3] EM_A[3] EM_A[3] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] EM_A[4] EM_A[4] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] EM_A[5] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10]

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Table 3-13. GPIO and EMIFA Multiplexing (Part 2)

Pin Mux Register AEAW[4:0] Bit Settings 01000 01001 01010 01011 01100 01101 01110 01111

EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] GPIO[24] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] GPIO[23] GPIO[23] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] GPIO[22] GPIO[22] GPIO[22] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] GPIO[21] GPIO[21] GPIO[21] GPIO[21] EM_A[10] EM_A[10] EM_A[10] EM_A[10] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] EM_A[11] EM_A[11] EM_A[11] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] EM_A[12] EM_A[12] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] EM_A[13] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10]

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Table 3-14. GPIO and EMIFA Multiplexing (Part 3)

Pin Mux Register AEAW[4:0] Bit Settings 10000 10001 10010 10011 10100 10101 10110 Others

EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] GPIO[16] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] GPIO[15] GPIO[15] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] GPIO[14] GPIO[14] GPIO[14] EM_A[17] EM_A[17] EM_A[17] EM_A[17] EM_A[17] GPIO[13] GPIO[13] GPIO[13] GPIO[13] EM_A[18] EM_A[18] EM_A[18] EM_A[18] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] EM_A[19] EM_A[19] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] EM_A[20] EM_A[20] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] EM_A[21]

3.6 Configurations After Reset

The following sections give the details on configuring the device after reset.

3.6.1 Switched Central Resource (SCR) Bus Priorities

Prioritization within the switched central resource (SCR) is selected to be either fixed or dynamic. Dynamic prioritization is based on the incoming epriority signals from each master. On DM6446, only the C64x+, VPSS, and EDMA masters actually generate epriority values. For all other masters, the value is programmed in the chip-level MSTPRI0/1 registers. The register bit fields and default priority levels for DM6446 bus masters are shown in Table 3-15 . The priority levels should be tuned to obtain the best system performance for a particular application. Details on the MSTPRI0/1 registers are given in

Figure 3-6 and Figure 3-7 .

Priority Bit Field Bus Master Default Priority Level

VPSSP VPSS 0 (VPSS PCR Register) EDMATC0P EDMATC0 0 (EDMACC QUEPRI Register) EDMATC1P EDMATC1 0 (EDMACC QUEPRI Register) ARM_DMAP ARM (DMA) 1 ARM_CFGP ARM (CFG) 1 C64X+_DMAP C64X+ (DMA) 7 (C64X+ MDMAARBE.PRI Register bit field) C64X+_CFGP C64X+ (CFG) 1

Table 3-15. DM6446 Default Bus Master Priorities

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Table 3-15. DM6446 Default Bus Master Priorities (continued)

Priority Bit Field Bus Master Default Priority Level

EMACP EMAC 4 USBP USB 4 ATAP ATA/CF 4 VLYNQP VLYNQ 4 VICPP VICP 5

Figure 3-6. MSTPRI0 Register

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED VICPP

R-0000 0000 0000 0 R/W-101

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSV C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP

R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001

LEGEND: R = Read; W = Write; - n = value after reset

(1) The VICPP bit field is configured by the Third-Party software. When modifying the MSTPRI0 register a read/modify/write must be

performed to preserve the configuration set by the Third-Party software.

Figure 3-7. MSTPRI1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED RESERVED RSV VLYNQP

R-0000 0000 0 R-100 R-0 R/W-100

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSV ATAP RSV USBP RSV RESERVED RSV EMACP

R-0 R/W-100 R-0 R/W-100 R-0 R-100 R-0 R/W-100

LEGEND: R = Read; W = Write; - n = value after reset

(1)

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3.6.2 Multiplexed Pin Configurations

There are numerous multiplexed pins that are shared by more than one peripheral. Some of these pins are configured by external pullup/pulldown resistors only at reset, and others are configured by software. As described in detail in Section 3.5.1 and Section 3.5.2 , hardware configurable multiplexed pins are programmed by external pullup/pulldown resistors at reset to set the initial functionality of pins for use by a single peripheral. After reset, software configurable multiplexed pins are programmable through Memory Mapped Registers (MMR) to allow the switching of pin functionalities during run-time. See Section 3.6.3 for more details on the register settings.

A summary of the pin multiplexing is shown in Table 3-16 . The EMAC peripheral shares pins with the 3.3V GPIO pins. The VLYNQ pins overlap upper EMIFA address pins resulting in a reduced EMIFA address range as the VLYNQ width is increased. The ATA peripheral shares data lines and some control signals with EMIFA. The ATA DMA pins are multiplexed with UART1. The ASP, UART0/1/2, SPI, I2C, and PWM0/1/2 all default to GPIO pins when not enabled. The VPBE function of the VPSS requires additional pins to implement the RGB888 mode. These are multiplexed with GPIOs.

Table 3-16. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls

MULTIPLEXED SECONDARY PERIPHERALS FUNCTION FUNCTION

EMIFA, ATA (CF) EMIFA: ATA (CF): PinMux0:ATAEN

EMIFA (NAND), EMIFA (NAND): ATA (CF): PinMux0:ATAEN ATA (CF) R/ W, EM_WAIT INTRQ, IORDY,

VPBE LCD, GPIO GPIO:GPIO[0] VPBE: LCD_OE PinMux0:LOEEN VPFE CCD, GPIO GPIO:GPIO[1] VPFE: C_WE PinMux0:CWEN VPBE RGB888, GPIO:GPIO[2] VPBE: PinMux0:RGB888

GPIO RGB888 G0 VPBE GPIO:GPIO[3] VPBE: VPBE: PinMux0:RGB888 PinMux0:LFLDEN

LCD/RGB888, GPIO RGB888 B0 LCD_FIELD VPFE CCD, VPBE GPIO:GPIO[4] VPBE: VPFE: PinMux0:RGB888 PinMux0:CFLDEN

RGB888, GPIO RGB888 R0 CCD_FIELD VPBE RGB888, GPIO: VPBE: PinMux0:RGB888

GPIO GPIO[5:6, 38] RGB888 G1, B1,

EMIFA, VLYNQ, GPIO:GPIO[8] EMIFA: VLYNQ: PinMux0:AECS5 PinMux0:VLYNQEN GPIO EM_CS5 VLYNQ_CLOCK

EMIFA, VLYNQ, GPIO:GPIO[9] EMIFA: VLYNQ: PinMux0:AECS4 PinMux0:VLSCREN GPIO EM_CS4 VLYNQ_SCRUN

EMIFA, VLYNQ, GPIO: EMIFA: VLYNQ: PinMux0:AEAW, PinMux0:VLYNQEN, GPIO GPIO[10:17] EM_A[21:14] VLYNQ_TXD[0:3], Pins:DAEAW[4:0] PinMux0:VLYNQWD[1:0]

EMIFA, GPIO GPIO: EMIFA: PinMux0:AEAW,

ASP, GPIO GPIO: ASP: PinMux1:ASP

UART0, GPIO GPIO: UART0: PinMux1:UART0

PRIMARY SECONDARY TERTIARY

(DEFAULT) REGISTER/PIN

FUNCTION CONTROL CONTROL

EM_D[0:15], DD[0:15], DA0 EM_BA[0]

(RDY/ BSY), DIOR(IORD) , EM_OE ( RE), DIOW(IOWR) EM_WE ( WE)

GPIO[18:28] EM_A[13:3] Pins:DAEAW[4:0]

GPIO[29:34] (all pins)

GPIO[35:36] RXD, TXD

(1)

(4)

TERTIARY

VLYNQ_RXD[0:3]

(2)

(3)

(1) When the Secondary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO) and Tertiary functions are

disabled.

(2) When the Tertiary function is enabled, to avoid potential contention, ensure that the Primary (if not GPIO), Secondary, and other Tertiary

functions are disabled. (3) Pin states are sampled at power on reset and written into the register fields. (4) See the Terminal Functions section for pin details.

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Table 3-16. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls (continued)

MULTIPLEXED SECONDARY PERIPHERALS FUNCTION FUNCTION

SPI, GPIO GPIO: SPI: PinMux1:SPI

SPI, ATA, GPIO GPIO:GPIO[42] SPI: SPI_EN1 ATA: HDDIR PinMux1:SPI PinMux0:HDIREN I2C, GPIO GPIO: I2C: SCL, SDA PinMux1:I2C

PWM0, GPIO GPIO:GPIO[45] PWM0 PinMux1:PWM0 PWM1, VPBE GPIO:GPIO[46] VPBE: PWM1: PinMux0:RGB666/ PinMux1:PWM1

(RGB666/RGB888), RGB666/RGB888 PWM1 PinMux0:RGB888 GPIO R2

PWM2, VPBE GPIO:GPIO[47] VPBE: PWM2: PinMux0:RGB666/ PinMux1:PWM2 (RGB666/RGB888), RGB666/RGB888 PWM2 PinMux0:RGB888 GPIO B2

ClockOut0, GPIO GPIO:GPIO[48] CLK_OUT0 PinMux1:CLK0 ClockOut1, TIMER0, GPIO:GPIO[49] CLK_OUT1 TIMER0: PinMux1:CLK1 PinMux1:TIM_IN

GPIO TIM_IN ATA, GPIO GPIO: ATA: PinMux0:ATAEN

EMIFA, GPIO, ATA GPIO:GPIO[52] EMIFA: ATA (CF): PinMux0:AEAW[4:0], PinMux0:ATAEN (CF) EM_BA[1] DA1 Pins:DAEAW[4:0]

EMIFA, ATA (CF), GPIO:GPIO[53] EMIFA: ATA (CF): DA2 PinMux0:AEAW[4:0], PinMux0:ATAEN, GPIO EM_A[0] Pins:DAEAW[4:0] Pins:BTSEL[1:0] = 10

EMAC, GPIO3V GPIO: EMAC: PinMux0:EMACEN

EMAC, MDIO, GPIO: EMAC: PinMux0:EMACEN GPIO3V GPIO3V[14:16] CRS,

UART1, ATA (CF) N/A ATA (CF): UART1: TXD, RXD PinMux0:ATAEN PinMux1:UART1

UART2, VPFE VPFE: UART2: PinMux1:UART2

UART2, VPFE VPFE: UART2: PinMux1:UART2,

PRIMARY SECONDARY TERTIARY

(DEFAULT) REGISTER/PIN

FUNCTION CONTROL CONTROL

GPIO[37, 39:41] SPI_EN0,

GPIO[43:44]

GPIO[50:51] ATA_CS0,

GPIO3V[0:13] (all pins, except

CI[7:6]/ UART_RXD2, CCD_DATA[15:14] UART_TXD2

CI[5:4]/ UART_CTS2, PinMux1:U2FLO CCD_DATA[13:12] UART_RTS2

SPI_CLK, SPI_DI, SPI_DO

ATA_CS1

(4)

CRS)

MDIO:

MDIO, MDCLK

DMACK,DMARQ

(1)

TERTIARY

(2)

(3)

3.6.3 Peripheral Selection After Device Reset

After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing of shared device pins between peripherals, as given in the Terminal Functions section. Section 3.6.4 ,

Section 3.6.5 , and Section 3.6.6 identify the register settings necessary to configure specific multiplexed

functions and show the primary (default) function after reset.

3.6.4 PINMUX0 Register Description

The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, and GPIO peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-17 . More details on the PINMUX0 pin muxing fields are given in Section 3.6.6 . A value of "1" enables the secondary or tertiary pin function.

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Figure 3-8. PINMUX0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

(1)

EMACE CFLDE LFLDE RGB88 RGB66 HDIRE

R/W-0 R/W-0 R/W-D R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0000 R/W-0 R/W-0

VLYNQ VLSCR

R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R-00000 R/W-LLLL

LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; - n = value after reset

(1) For proper DM6446 device operation, always write a value of '0' to RSV bits 30 and 29

RSV RSV RSV CWEN LOEEN RESERVED ATAEN

N N N 8 6 N

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN EN

VLYNQWD AECS5 AECS4 RESERVED AEAW

Table 3-17. PINMUX0 Register Description

Name Description

EMACEN Enable EMAC and MDIO function on default GPIO3V[0:16] pins. CFLDEN Enable CCD C_FIELD function on default GPIO[4] pin CWEN Enable CCD C_WEN function on default GPIO[1] pin LFLDEN Enable LCD_FIELD function on default GPIO[3] pin LOEEN Enable LCD_OE function on default GPIO[0] pin RGB888 Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins RGB666 Enable VPBE RGB666 function on default GPIO[46:47] pins ATAEN Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins HDIREN Enable HDDIR function on default GPIO[42] pin VLYNQEN Enable VLYNQ function on default GPIO[9,10:17] pins VLSCREN Enable VLYNQ SCRUN function on default GPIO[9] pin VLYNQWD VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3] functions on default GPIO[10:17]

AECS5 Enable EMIFA EM_CS5 function on GPIO[8] AECS4 Enable EMIFA EM_CS4 function on GPIO[9] AEAW EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This

pins.

enables EMIF address function on default GPIO[10:28] pins.

3.6.5 PINMUX1 Register Description

The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in

Figure 3-9 and bit field descriptions are given in Table 3-18 . More details on the PINMUX1 pin muxing

fields are given in Section 3.6.6 . A value of "1" enables the secondary or tertiary pin function.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ASP RSV SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0

R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

(1) For proper DM6446 device operation, always write a value of '0' to RSV bit 9.

72 Device Configuration

Figure 3-9. PINMUX1 Register

RESERVED TIMIN CLK1 CLK0

R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0

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Table 3-18. PINMUX1 Register Description

Name Description

TIMIN Enable TIM_IN function on default GPIO[49] pin CLK1 Enable CLK_OUT1 function on default GPIO[49] pin CLK0 Enable CLK_OUT0 function on default GPIO[48] pin ASP Enable ASP function on default GPIO[29:34] pins SPI Enable SPI function on default GPIO[37,39:42] pins I2C Enable I2C function on default GPIO[43:44] pins PWM2 Enable PWM2 function on default GPIO[47] pin PWM1 Enable PWM1 function on default GPIO[46] pin PWM0 Enable PWM0 function on default GPIO[45] pin U2FLO Enable UART2 flow control function on default VPFE CI[5:4]/CCD_DATA[13:12] pins UART2 Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14] pins UART1 Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins UART0 Enable UART0 function on default GPIO[35:36] pins

3.6.6 Pin Multiplexing Register Field Details

The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are described in the following sections.

3.6.6.1 EMAC and GPIO3V Pin Multiplexing

The EMAC pin functions are selected as shown in Table 3-19 . The functionality for each of the individual pins affected by the PINMUX0 field settings is given in Table 3-20 .

Table 3-19. EMAC and GPIO3V Pin Multiplexing Control

EMACEN PIN FUNCTIONALITY SELECTED

0 GPIO3V 1 EMAC

Table 3-20. EMAC and GPIO3V Multiplexed Pins

GPIO EMAC

GPIO3V[0] TXEN GPIO3V[1] TXCLK GPIO3V[2] COL GPIO3V[3] TXD[0] GPIO3V[4] TXD[1] GPIO3V[5] TXD[2] GPIO3V[6] TXD[3] GPIO3V[7] RXD[0] GPIO3V[8] RXD[1] GPIO3V[9] RXD[2] GPIO3V[10] RXD[3] GPIO3V[11] RXCLK GPIO3V[12] RXDV GPIO3V[13] RXER GPIO3V[14] CRS

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Table 3-20. EMAC and GPIO3V Multiplexed Pins

GPIO3V[15] MDIO GPIO3V[16] MDCLK

3.6.6.2 VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing

The CCD and LCD controllers in the VPSS require multiplex control bit settings for certain modes of operation. Bits within the PinMux0 register, which select between the CCD or LCD control signal function and GPIO, are summarized in Table 3-21 .

Table 3-21. VPFE (CCD), VPBE (LCD), and GPIO Pin Multiplexing

PINMUX0 REGISTER FIELDS MULTIPLEXED PINS

CFLDE LFLDE CWEN LOEEN C_FIELD/ LCD_FIELD/ C_WEN/ LCD_OE/ N N R0/ B0/ GPIO[1] GPIO[0]

- - - 0 - - - GPIO[0]

- - - 1 - - - LCD_OE

- - 0 - - - GPIO[1] -

- - 1 - - - C_WEN -

- 0 - - - B0/GPIO[3]

- 1 - - - LCD_FIELD - 0 - - - R0/GPIO[4] 1 - - - C_FIELD - - -

(1) Depends on RGB888 bit setting, see Table 3-22

3.6.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing

(continued)

GPIO EMAC

GPIO[4] GPIO[3]

(1)

- - -

(1)

- -

Use of the RGB666 and RGB888 modes of the VPBE requires enabling RGB pins as shown in Table 3-22 and Table 3-23 . Enabling PWM2, PWM1, CCD, and LCD functionality overrides the the RGB modes. RGB666 interface pin functionality requires setting the RGB666 PINMUX0 Register bit field to ‘1’ and PINMUX1 Register bit fields PWM2 and PWM1 to ‘0’. Proper RGB888 interface operation requires setting PINMUX0 Register bit field RGB888 to ‘1’ and bit fields PWM2, PWM1, CFLDEN, and LFLDEN must be set to ‘0’.

Table 3-22. VPBE (RGB666, RGB888, and LCD), VPFE (CCD), and GPIO Pin

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS RGB8 RGB6 PWM CFLDE LFLDE

88 66 1 N N

0 0 0 0 0 0 GPIO[47] GPIO[46] GPIO[4] GPIO[3]

- - - - - 1 - - - LCD_FIELD

- - - - 1 - - - C_FIELD -

- - - 1 - - - PWM1 - -

- - 1 - - - PWM2 - - 0 1 0 0 0 0 B2 R2 GPIO[4] GPIO[3] 1 - 0 0 0 0 B2 R2 R0 B0

Multiplexing

PWM2/ PWM1/ C_FIELD/ LCD_FIELD/

PWM2 B2/ R2/ R0/ B0/

GPIO[47] GPIO[46] GPIO[4] GPIO[3]

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Table 3-23. VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

RGB888 PWM2 PWM1 CFLDEN LFLDEN

0 0 0 0 0 GPIO[38] GPIO[6] GPIO[5] GPIO[2] 1 0 0 0 0 R1 B1 G1 G0

3.6.6.4 ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

The ATA peripheral shares pins with the EMIFA and UART1 as seen in Table 3-24 . If ATA pin functionality is enabled by setting the ATAEN bit field, the ATA module will drive the EMIFA data and control pins. Enabling UART1 disables the use of the ATA DMARQ and DMACK signals and thus only allows the ATA module to use PIO mode. The ATA HDDIR buffer direction control bit field works in conjunction with the HDIREN enable bit field to allow the ATA pins to still be used as a GPIO or SPI_EN1 if the buffer is not being used (i.e. for Compact Flash). This multiplexing is shown in Table 3-25 . When ATAEN=0 and HDIREN=1 it indicates that the ATA interface has been disabled so that the EMIFA can be used, but the ATA buffers are still present. HDDIR is driven low in this situation to ensure that the ATA buffers drive away from DM644X and don’t cause bus contention with the EMIFA. Note that switching between EMIFA and ATA (clearing or setting ATAEN) must be carefully performed to prevent bus contention. Since the ATA device can be a bus master, software must ensure that all outstanding DMA requests have completed before clearing the ATAEN bit.

R1/ B1/ G1/ G0/ GPIO[38] GPIO[6] GPIO[5] GPIO[2]

TMS320DM6446

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Table 3-24. ATA, EMIFA, and GPIO Pin Multiplexing Control

PINMUX0

BIT FIELD

ATAEN GPIO[52]/ GPIO[53]/ DD[15:0]

0 1 ATA_CS0 ATA_CS1 INTRQ ATA0 EM_WAIT DIOR DIOW ATA1 ATA2 DD[15:0]

(1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-12 .

GPIO[50]/ GPIO[51]/ EM_R/ W EM_BA[0]/ RDY/ BSY/ DIOR/ DIOW/ ATA_CS0 ATA_CS1 INTRQ ATA0 EM_WAIT EM_OE EM_WE

GPIO[50] GPIO[51] EM_R/ W EM_BA[0] RDY/ BSY EM_OE EM_WE EM_BA[1]/ EM_A[0]/ EM_D[15:0]

EM_BA[1]/ EM_A[0]/ EM_D[15:0]/ ATA1 ATA2

GPIO[52]

Table 3-25. ATA, EMIFA, UART1, SPI, and GPIO Pin Multiplexing

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

ATAEN UART1 HDIREN SPI DMACK DMARQ HDDIR/

0 0 0 0 DMACK DMARQ GPIO[42] 0 0 0 1 DMACK DMARQ SPI_EN1 0 0 1 - DMACK DMARQ Driven Low 0 1 0 0 UART_TXD1 UART_RXD1 GPIO[42] 0 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1 0 1 1 - UART_TXD1 UART_RXD1 Driven Low 1 0 0 0 DMACK DMARQ GPIO[42]x 1 0 0 1 DMACK DMARQ SPI_EN1x 1 0 1 - DMACK DMARQ HDDIR 1 1 0 0 UART_TXD1 UART_RXD1 GPIO[42]x 1 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1x 1 1 1 - UART_TXD1 UART_RXD1 HDDIR

UART_TXD1/ UART_RXD1/ SPI_EN1/

(1)

GPIO[42]

(1)

GPIO[53]

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3.6.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing

Table 3-26 and Table 3-27 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled

(VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] / EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address based on the AEAW value.

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Table 3-26. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing

PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS

VLYNQEN AECS5 AECS4 GPIO[8]/ GPIO[9]/

0 - 0 0 GPIO[8] GPIO[9] 0 - 0 1 GPIO[8] EM_CS4 0 - 1 0 EM_CS5 GPIO[9] 0 - 1 1 EM_CS5 EM_CS4 1 0 - 0 VLYNQ_CLOCK GPIO[9] 1 0 - 1 VLYNQ_CLOCK EM_CS4 1 1 - - VLYNQ_CLOCK VLYNQ_SCRUN

PINMUX0

BIT FIELDS

VLYNQE VLYNQ

N WD

0 -

1 00

1 01

1 10 1 11 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 VL_TXD3 VLRXD3

(1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-12 .

3.6.6.6 Timer0 Input, CLKOUT1, and GPIO Pin Multiplexing

VLSCREN EM_CS5/ EM_CS4/

VLYNQ_CLOCK VLYNQ_SCRUN

Table 3-27. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing

EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/ GPIO[10]/ GPIO[11]/ GPIO[12]/ GPIO[13]/ GPIO[14]/ GPIO[15]/ GPIO[16]/ GPIO[17]/ VL_TXD0 VL_RXD0 VL_TXD1 VL_RXD1 VL_TXD2 VL_RXD2 VL_TXD3 VL_RXD3

EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

(1)

GPIO[10] VL_TXD0 VLRXD0 EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/

VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 EM_A[15]/ EM_A[14]/

(1)

GPIO[11]

(1)

GPIO[12]

GPIO[13]

(1)

GPIO[13]

(1)

GPIO[14]

(1)

GPIO[14]

(1)

GPIO[14]

(1)

GPIO[15]

(1)

GPIO[15]

(1)

GPIO[15]

TMS320DM6446

SPRS283 – DECEMBER 2005

(1)

GPIO[16]

(1)

GPIO[16]

(1)

GPIO[16]

(1)

GPIO[16]

(1)

GPIO[17]

(1)

GPIO[17]

(1)

GPIO[17]

(1)

GPIO[17]

The multiplexing of the CLKOUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-28 .

3.6.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing

When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as seen in Table 3-29 , Table 3-30 , and Table 3-31 . The SPI_EN1 pin can also function as the HDDIR buffer control when ATAEN is selected and the HDIREN bit is set.

Table 3-28. Timer0 Input, CLKOUT1, and GPIO Pin

Multiplexing

PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

CLKOUT1/

TIMIN CLK1 TIM_IN/

GPIO[49]

0 0 GPIO[49] 0 1 CLKOUT1 1 - TIM_IN

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Table 3-29. ASP and GPIO Pin Multiplexing

PINMUX1 REGISTER BIT FIELD MULTIPLEXED PINS

ASP

0 GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] 1 CLKX CLKR FSX FSR DX DR

PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

SPI ATAEN HDIREN HDDIR/ GPIO[41] GPIO[40] GPIO[39] GPIO[37]

0 0 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 0 1 Driven Low GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 1 HDDIR GPIO[41] GPIO[40] GPIO[39] GPIO[37] 1 0 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 0 1 Driven Low SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 1 HDDIR SPI_DO SPI_DI SPI_CLK SPI_EN0

CLKX/ CLKR/ FSX/ FSR/ DX/ DR/ GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34]

Table 3-30. SPI and GPIO Pin Multiplexing

SP_EN1/ SPI_DO/ SPI_DI/ SPI_CLK/ SPI_EN0/ GPIO[42]

3.6.6.8 PWM, RGB888, and GPIO Pin Multiplexing

Table 3-32 shows the PWM0/1/2 pin multiplexing. Each PWM output is independently controlled by its

own enable bit. The PWM function has priority over RGB888 muxing (see Section 3.6.6.3 ).

PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS

PWM2 PWM1 PWM0 RGB888 B2/ R2/ GPIO[45]

0 0 0 0 GPIO[47] GPIO[46] GPIO[45] 0 0 0 1 B2 R2 GPIO[45]

- - 1 - - - PWM0

- 1 - - - PWM1 -

1 - - - PWM2 - -

Table 3-31. I2C and GPIO Pin Multiplexing

PINMUX1 REGISTER

BIT FIELD

I2C

0 GPIO[43] GPIO[44] 1 I2C_CLK I2C_DATA

I2C_CLK/ I2C_DATA/ GPIO[43] GPIO[44]

MULTIPLEXED PINS

Table 3-32. PWM0/1/2, RGB888, and GPIO Pin Multiplexing

PWM2/ PWM1/ PWM0/ GPIO[47] GPIO[46]

3.6.6.9 UART, VPFE, ATA, and GPIO Pin Multiplexing

Each UART has independent pin multiplexing control bits in the PINMUX1 register. The UART2 peripheral may be used with or without the flow control signals. Table 3-33 shows how UART2 selection reduces the width of the VPFE interface.

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Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However, ATA PIO mode is still supported with UART1 enabled. This is shown in Table 3-34 . If the ATA module is not enabled, the pins are always configured for use by UART1.

Table 3-33. UART2, VPFE, and GPIO Pin Multiplexing

PINMUX1 REGISTER

BIT FIELDS

UART2 U2FLO CI[7]/ CI[6]/ CI[5]/ CI[4]/

0 -

1 0 1 1 UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2

(1) Functionality set by VPFE operating mode.

CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/ UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2

CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/

(1)

CI[7] UART_RXD2 UART_TXD2 CCD[13]/ CCD[12]/

CI[6]

MULTIPLEXED PINS

(1)

CI[5]

(1)

CI[5]

(1)

CI[4]

(1)

CI[4]

Table 3-34. UART1 and ATA Pin Multiplexing

PINMUX0 AND PINMUX1

ATAEN UART1

0 - UART_TXD1 UART_RXD1 1 0 DMACK DMARQ 1 1 UART_TXD1 UART_RXD1

UART_TXD1/ UART_RXD1/ DMACK DMARQ

MULTIPLEXED PINS

As Table 3-35 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO.

3.7 Emulation Control

The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. This allows peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register indicates the emulation suspend source for those peripherals which support emulation suspend. The SUSPSRC register format is shown in Figure 3-10 . Brief details on the peripherals which correspond to the register bits is given in Table 3-36 . When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator.

Table 3-35. UART0 and GPIO Pin Multiplexing

PINMUX1

FIELD

UART0

0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0

UART_TXD0/ UART_RXD0/ GPIO[36] GPIO[35]

Device Configuration 79

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Figure 3-10. Emulation Suspend Source Register (SUSPSRC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VICP VICP TIMR2 TIMR1 TIMR0 GPIO PWM2 PWM1 PWM0 SPI UART2 UART1 UART0 I2C ASP SRC EN SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSV RSV RSV RSV RESERVED

R-000 R/W-0 R-00 R/W-0 R-000 R/W-0 R-0 0000

LEGEND: R = Read, W = Write, n = value at reset

Name Description

VICPSRC Video Imaging Coprocessor emulation suspend source

VICPEN Video Imaging Coprocessor emulation suspend enable

TIMR2SRC Timer2 (WD Timer) emulation suspend source

TIMR1SRC Timer1 emulation suspend source

TIMR0SRC Timer0 emulation suspend source

GPIOSRC GPIO emulation suspend source

PWM2SRC PWM2 emulation suspend source

PWM1SRC PWM1 emulation suspend source

PWM0 SRC PWM0 emulation suspend source

SPISRC SPI emulation suspend source

UART2SRC UART2 emulation suspend source

UART1SRC UART1 emulation suspend source

UART0SRC UART0 emulation suspend source

I2CSRC I2C emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

0 = Emulation suspend ignored by VICP 1 = VICP emulation suspend enabled

0 = ARM emulation suspend 1 = DSP emulation suspend

RSV

USB EMAC SRC SRC

Table 3-36. SUSPSRC Register Description

80 Device Configuration

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Table 3-36. SUSPSRC Register Description (continued)

Name Description

ASPSRC ASP emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

USBSRC USB emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

EMACSRC Ethernet MAC emulation suspend source

0 = ARM emulation suspend 1 = DSP emulation suspend

3.8 Debugging Considerations

TBD external connections, internal pullup/pulldown resistors For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.

3.9 Configuration Examples

TBD

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Device Configuration 81

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TMS320DM6446 Digital Media System on-Chip

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4 Device Operating Conditions

4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Supply voltage ranges

Input voltage ranges

Output voltage ranges

Operating case temperature ranges, T Storage temperature range, T

stg

(1)

Core (CV I/O, 3.3V (DV I/O, 1.8V (DV

USB_V

, APLLREFV, V

DD33 DD18

, MXV

DD1P8

DDA_1P1V

, USB_DV , DV

, DDR_V

DDR2

, M24V

, USB_V

)

DDA_3P3

DDDLL

(3)

)

DDA1P2LDO

(3)

, PLLV

(2)

, CV

, V

DD18

DDA_1P8V

(3)

)

DDDSP

, -0.3 V to 2.4 V

VII/O, 3.3V -0.3 V to 4 V VII/O, 1.8V -0.3 V to 2.4 V VOI/O, 3.3V -0.3 V to 4 V VOI/O, 1.8V -0.3 V to 2.4 V (default) 0 ° C to 85 ° C

(default) -65 ° C to 150 ° C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This pin is an internal LDO output and connected via 1 µF capacitor to USB_V (3) All voltage values are with respect to V

SS.

SSA1P2LDO

-0.3 V to 1.8 V

-0.3 V to 4 V

Device Operating Conditions82

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

4.2 Recommended Operating Conditions

MIN NOM MAX UNIT

Supply voltage, Core (CV USB_V

DDA1P2LDO

(1)

Supply voltage, I/O, 3.3V (DV

Supply voltage, I/O, 1.8V (DV PLLV

Supply ground (V USB_V MXV

, V

DD18

DDA_1P8V

, USB_V

SSREF

(3)

, M24V

(3)

DDR_VREF DDR2 reference voltage DDR_ZP DDR2 impedance control, connected via 200 Ω resistor to V DDR_ZN DDR2 impedance control, connected via 200 Ω resistor to DV DAC_VREF DAC reference voltage input 0.5 V DAC_RBIAS DAC biasing, connected via 4 k Ω resistor to V USB_VBUS USB external charge pump input 5 V

USB_R1

USB reference current output, connected via 10 k Ω +/- 1% resistor USB_V to USB_V

SSREF EF

High-level input voltage, I/O, 3.3V 2 V

High-level input voltage, non-DDR I/O, 1.8V 0.65DV High-level input voltage, DDR I/O, 1.8V V Low-level input voltage, I/O, 3.3V 0.8 V

Low-level input voltage, non-DDR I/O, 1.8V 0.35DV Low-level input voltage, DDR I/O, 1.8V V

Operating case temperature Default 0 85 ° C

(1) This pin is an internal LDO output and connected via 1 µF capacitor to USB_V (2) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin

configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC

devices. (3) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. (4) DDR_VREF is expected to equal 0.5DV

, CV

, USB_V

, V

SS1P8

)

DDDSP

SSA_1P8V

(4)

DDR2

, APLLREFV, V

) (-594 devices)

, USB_DV

DD33

, DV

DD18

, MXV

DD1P8

, V

SSA_1P1V

, USB_V

SSA3P3

DDA_1P1V

, DDR_V

DDR2

, DDR_V

, USB_V

(2)

) 3.14 3.3 3.46 V

DDA3P3

DDDLL

, M24V

)

SSDLL

SSA1P2LDO

, 0 0 0 V

0.49DV

DDR2

SSA_1P8V

DDR_VREF

SSA1P2LDO

of the transmitting device and to track variations in the DV

1.14 1.2 1.26 V

1.71 1.8 1.89 V

0.5DV

DDR2

SSA_1P8V

0.51DV

DDR2

SSR

DDR2

+ 0.25

DDR_VREF

- 0.25

DDR2

V V V

Device Operating Conditions 83

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PRODUCT PREVIEW

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Case Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS

High-level output voltage (3.3V I/O) DV

High-level output voltage (1.8V I/O) DV

High-level output voltage (1.8V I/O DDR_VREF DDR2) + 0.643

Low-level output voltage (3.3V I/O) DV

Low-level output voltage (1.8V I/O) DV

Low-level output voltage (1.8V I/O DDR_VREF DDR2) - 0.643

Input current TBD µA

= MIN, IOH= MAX DV

DD33

= MIN, IOH= MAX DV

DD18

= MIN, IOH= MAX V

DDR

= MIN, IOL= MAX 0.2 V

DD33

= MIN, IOL= MAX 0.45 V

DD18

= MIN, IOL= MAX V

DDR

VI= V internal resistor

VI= V pullup resistor

VI= V pulldown resistor

to DV

(2)

without opposing

with opposing internal

(2)

VCLK, GPIO[48]/CLK_OUT0, GPIO[8]/EM_CS5/VLYNQ_CLK, 8 mA

High-level output current

EM_A[21:14]/VLYNQ_(TX/RX)D[3:0] DDR2 -13.4 mA All other peripherals 4 mA VCLK, GPIO[48]/CLK_OUT0,

GPIO[8]/EM_CS5/VLYNQ_CLK, 8 mA

Low-level output current

EM_A[21:14]/VLYNQ_(TX/RX)D[3:0] DDR2 13.4 mA All other peripherals 4 mA

C C

I/O Off-state output current VO= DV

Core (CV V

CDD

DDD

DDA1P2LDO

current

3.3V I/O (DV supply current

1.8V I/O (DV DDR_V

DDD

USB_V supply current

Input capacitance 10 pF

Output capacitance 10 pF

, APLLREFV, V

(3)

(4)

DD33

DD18

, PLLV

DDDLL

, MXVDD, M24VDD)

DD1P8

, CV

DDDSP

, USB_DV

(4)

, DV

(4)

DDA_1P1V

) supply CV

DDA3P3

DDR2

, V

DD18

DDA_1P8V

)

or V

= 1.2 V, DSP clock = 594 MHz TBD mA

= 3.3 V, DSP clock = 594 MHz TBD mA

= 1.8 V, DSP clock = 594 MHz TBD mA

(1)

MIN TYP MAX UNIT

- 0.2 V

- 0.45 V

1 µA

TBD µA

± 20 µA

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. (2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. (3) This pin is an internal LDO output and connected via 1 µF capacitor to USB_V (4) Measured with average activity (50% high/50% low power) at 25 ° C case temperature and TBD-MHz EMIFA for -594 speed. This model

represents a device performing high-MPU/DSP-activity operations 50% of the time, and the remainder performing low-MPU/DSP-activity

operations. The high/low-MPU/DSP-activity models are defined as follows:

• High-MPU/DSP-Activity Model: – MPU: TBD – DSP: TBD

• Low-MPU/DSP-Activity Model: – MPU: TBD – DSP: TBD

The actual current draw is highly application-dependent. For more details on core and I/O activity, see the DM644xPower Consumption Summary application report (literature number SPRATBD).

84 Device Operating Conditions

SSA1P2LDO

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5 Peripheral and Electrical Specifications

Transmission Line

4.0 pF 1.85 pF

Z0 = 50 Ω (see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output Under Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.

42 Ω 3.5 nH

Device Pin (see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

ref

= VIL MAX (or VOL MAX)

ref

= VIH MIN (or VOH MIN)

5.1 Parameter Information

5.1.1 Parameter Information Device-Specific Information

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

5.1.1.1 Signal Transition Levels

All input and output timing parameters are referenced to V V

= 1.5 V. For 1.8 V I/O, V

ref

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V V

MAX and V

Figure 5-1. Test Load Circuit for AC Timing Measurements

for both "0" and "1" logic levels. For 3.3 V I/O,

= 0.9 V.

ref

MIN for output clocks.

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

ref

MAX and V

MIN for input clocks,

Peripheral and Electrical Specifications 85

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TMS320DM6446 Digital Media System on-Chip

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5.1.1.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

5.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between V monotonic manner.

5.3 Power Supplies

For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower .

5.3.1 Power-Supply Sequencing

Note: This power sequencing information is preliminary and subject to change. Currently, DM6446 devices do not require specific power sequencing between the core supply and the I/O

supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time(>1 second) if the other supply is below the proper operating voltage.

5.3.1.1 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the DM6446 device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

5.3.1.2 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to DM6446. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6446 power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior".

and V

(or between V

and V

) in a

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 µ F) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered.

Peripheral and Electrical Specifications86

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5.3.1.3 DM6446 Power and Clock Domains

DM6446 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the V The majority of the DM6446's modules lie within the "Always On" power domain. A separate domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain is not always on. The "DSP" power domain is powered by the CV

pins of the DM6446. Table 5-1 provides a listing of the DM6446 power

DDDSP

and clock domains. Two primary reference clocks are required for the DM6446 device. These can either be crystal input or

driven by external oscillators. A 27-MHz crystal is recommended for the system PLLs, which generate the internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3. The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For further description of the DM6446 clock domains, see Table 5-2 and Figure 5-4 .

Table 5-1. DM6446 Power and Clock Domains

Power Domain Clock Domain Peripheral/Module

Always On CLKIN UART0 Always On CLKIN UART1 Always On CLKIN UART2 Always On CLKIN I2C Always On CLKIN Timer0 Always On CLKIN Timer1 Always On CLKIN Timer2 Always On CLKIN PWM0 Always On CLKIN PWM1 Always On CLKIN PWM2 Always On CLKDIV2 ARM Subsystem Always On CLKDIV3 DDR2 Always On CLKDIV3 VPSS Always On CLKDIV3 EDMA Always On CLKDIV3 SCR Always On CLKDIV6 GPSC Always On CLKDIV6 LPSCs Always On CLKDIV6 Ice Pick Always On CLKDIV6 EMIFA Always On CLKDIV6 USB Always On CLKDIV6 VLYNQ Always On CLKDIV6 EMAC Always On CLKDIV6 ATA/CF Always On CLKDIV6 MMC/SD Always On CLKDIV6 SPI Always On CLKDIV6 ASP Always On CLKDIV6 GPIO DSP CLKDIV1 C64x+ CPU DSP CLKDIV2 VICP DSP CLKDIV4 VICP DSP CLKDIV6 VICP

Digital Media System on-Chip

TMS320DM6446

SPRS283 – DECEMBER 2005

pins of the DM6446.

Peripheral and Electrical Specifications 87

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Peripheral and Electrical Specifications88

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DSP Subsystem

ARM Subsystem

VICP

SYSCLK1

SYSCLK2

SYSCLK5

SCR

EDMA

VPFE

VPBE

DACs

DDR2 PHY DDR2 VTP

DDR2 Mem Ctlr

PLLDIV1 (/1)

PLLDIV2 (/2)

BPDIV

PLL Controller 2

PLL Controller 1

PLLDIV3 (/3)

PLLDIV5 (/6)

PLLDIV2 (/2)

PLLDIV1 (/1)

SYSCLK3

Bypass Clock

UARTs (x3)

I2C

Timers (x3)

PWMs (x3)

A TA/CF

EMIF/NAND

EMAC

VLYNQ

MMC/SD

SPI

GPIO

ASP

ARM INTC

USB 2.0

USB PHY

60 MHz

24 MHz

27 MHz

PCLK

VPBECLK

PLLDIV4 (/4)

Table 5-2. DM6446 Clock Domains

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

(1)

Subsystem Fixed Ratio vs. PLL1

PLL1 – 27 MHz 594 MHz DSP 1:1 27 MHz 594 MHz ARM 1:2 13.5 MHz 297 MHz IMX/LCD 1:2 13.5 MHz 297 MHz Sequencer 1:4 6.75 MHz 148.5 MHz EDMA3/VPSS 1:3 9 MHz 198 MHz Peripherals 1:6 4.5 MHz 99 MHz

(1) These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 22.

PLL Bypass PLL Enabled

Clock Modes (Frequency)

Figure 5-4. PLL1 and PLL2 Clock Domain Block Diagram

For further detail on PLL1 and PLL2, see the structure block diagrams Figure 5-5 and Figure 5-6 , respectively.

Peripheral and Electrical Specifications 89

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PRODUCT PREVIEW

PLLDIV1 (/1)

PLLDIV2 (/2)

PLLDIV4 (/4)

PLLDIV3 (/3)

PLLDIV5 (/6)

SYSCLK1

SYSCLK2

SYSCLK4

SYSCLK3

SYSCLK5

Post−DIV

PLLM

PLL

BPDIV

CLKMODE

CLKIN

OSCIN

PLLEN

AUXCLK SYSCLKBP

PLLDIV1 (/1)

PLLDIV2 (/2)

Post−DIV

PLLM

PLL

BPDIV

CLKMODE

CLKIN

OSCIN

PLLEN

PLL2_SYSCLK1 (VPSS−VPBE)

PLL2_SYSCLK2 (DDR2 PHY)

PLL2_SYSCLKBP (DDR2 VTP)

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Figure 5-5. PLL1 Structure Block Diagram

5.3.1.4 Power and Sleep Controller (PSC)

The Power and Sleep Controller (PSC) controls DM6446 device power by turning off unused power domains or gating off clocks to individual peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, power domain control, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The GPSC controls all of DM6446’s LPSCs. The ARM Subsystem does not have an LPSC module. ARM sleep mode is accomplished through the wait for interrupt instruction. The LPSCs for DM6446 are shown in Table 5-3 . The PSC Register memory map is given in Table 5-4 . For more details on the PSC, see the Documentation Support section for the ARM Subsystem User's Guide.

LPSC Peripheral/Module LPSC Peripheral/Module LPSC Peripheral/Module Number Number Number

0 VPSS DMA 14 EMIFA 28 TIMER1 1 VPSS MMR 15 MMC/SD 29 Reserved 2 EDMACC 16 Reserved 30 Reserved 3 EDMATC0 17 ASP 31 Reserved 4 EDMATC1 18 I2C 32 Reserved

90 Peripheral and Electrical Specifications

Figure 5-6. PLL2 Structure Block Diagram

Table 5-3. DM6446 LPSC Assignments

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Digital Media System on-Chip

Table 5-3. DM6446 LPSC Assignments (continued)

LPSC Peripheral/Module LPSC Peripheral/Module LPSC Peripheral/Module Number Number Number

5 EMAC 19 UART0 33 Reserved 6 EMAC Memory Controller 20 UART1 34 Reserved 7 MDIO 21 UART2 35 Reserved 8 Reserved 22 SPI 36 Reserved 9 USB 23 PWM0 37 Reserved 10 ATA/CF 24 PWM1 38 Reserved 11 VLYNQ 25 PWM2 39 C64x+ CPU 12 Reserved 26 GPIO 40 VICP 13 DDR2 Memory Controller 27 TIMER0

Table 5-4. PSC Register Memory Map

TMS320DM6446

SPRS283 – DECEMBER 2005

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1000 PID Peripheral Revision and Class Information Register 0x01C4 1003 - 0x01C4 101F - Reserved 0x01C4 1010 GBLCTL Global Control Register 0x01C4 1014 - Reserved 0x01C4 1018 INTEVAL Interrupt Evaluation Register 0x01C4 101C - 0x01C4 103F - Reserved 0x01C4 1040 MERRPR0 Module Error Pending 0 (mod 0 - 31) Register 0x01C4 1044 MERRPR1 Module Error Pending 1 (mod 32- 63) Register 0x01C4 1048 - 0x01C4 104F - Reserved 0x01C4 1050 MERRCR0 Module Error Clear 0 (mod 0 - 31) Register 0x01C4 1054 MERRCR1 Module Error Clear 1 (mod 32 - 63) Register 0x01C4 1058 - 0x01C4 105F - Reserved 0x01C4 1060 PERRPR Power Error Pending Register 0x01C4 1064 - 0x01C4 1067 - Reserved 0x01C4 1068 PERRCR Power Error Clear Register 0x01C4 106C - 0x01C4 106F - Reserved 0x01C4 1070 EPCPR External Power Error Pending Register 0x01C4 1074 - 0x01C4 1077 - Reserved 0x01C4 1078 EPCCR External Power Control Clear Register 0x01C4 107C - 0x01C4 10FF - Reserved 0x01C4 1100 RAILSTAT Power Rail Status Register 0x01C4 1104 RAILCTL Power Rail Control Register 0x01C4 1108 RAILSEL Power Rail Counter Select Register 0x01C4 110C - 0x01C4 111F - Reserved 0x01C4 1120 PTCMD Power Domain Transition Command Register 0x01C4 1124 - 0x01C4 1127 - Reserved 0x01C4 1128 PTSTAT Power Domain Transition Status Register 0x01C4 112C - 0x01C4 11FF - Reserved 0x01C4 1200 PDSTAT0 Power Domain Status 0 Register (Always On) 0x01C4 1204 PDSTAT1 Power Domain Status 1 Register (DSP) 0x01C4 1208 - 0x01C4 12FF - Reserved 0x01C4 1300 PDCTL0 Power Domain Control 0 Register (Always On)

Peripheral and Electrical Specifications 91

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SPRS283 – DECEMBER 2005

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1304 PDCTL1 Power Domain Control 1 Register (DSP) 0x01C4 1308 - 0x01C4 14FF - Reserved 0x01C4 1500 Reserved 0x01C4 1504 Reserved 0x01C4 1508 0x1C4 150F - Reserved 0x01C4 1510 MCKOUT0 Module Clock Output Status (mod 0-31) Register 0x01C4 1514 MCKOUT1 Module Clock Output Status (mod 32-63) Register 0x01C4 1518 - 0x01C4 15FF - Reserved 0x01C4 1600 MDCFG0 Module Configuration 0 Register (VPSS DMA) 0x01C4 1604 MDCFG1 Module Configuration 1 Register (VPSS MMR) 0x01C4 1608 MDCFG2 Module Configuration 2 Register (EDMACC) 0x01C4 160C MDCFG3 Module Configuration 3 Register (EDMATC0) 0x01C4 1610 MDCFG4 Module Configuration 4 Register (EDMATC1) 0x01C4 1614 MDCFG5 Module Configuration 5 Register (EMAC) 0x01C4 1618 MDCFG6 Module Configuration 6 Register (EMAC Memory Controller) 0x01C4 161C MDCFG7 Module Configuration 7 Register (MDIO) 0x01C4 1620 Reserved 0x01C4 1624 MDCFG9 Module Configuration 9 Register (USB) 0x01C4 1628 MDCFG10 Module Configuration 10 Register (ATA/CF) 0x01C4 162C MDCFG11 Module Configuration 11 Register (VLYNQ) 0x01C4 1630 Reserved 0x01C4 1634 MDCFG13 Module Configuration 13 Register (DDR2) 0x01C4 1638 MDCFG14 Module Configuration 14 Register (EMIFA) 0x01C4 163C MDCFG15 Module Configuration 15 Register (MMC/SD) 0x01C4 1640 Reserved 0x01C4 1644 MDCFG17 Module Configuration 17 Register (ASP) 0x01C4 1648 MDCFG18 Module Configuration 18 Register (I2C) 0x01C4 164C MDCFG19 Module Configuration 19 Register (UART0) 0x01C4 1650 MDCFG20 Module Configuration 20 Register (UART1) 0x01C4 1654 MDCFG21 Module Configuration 21 Register (UART2) 0x01C4 1658 MDCFG22 Module Configuration 22 Register (SPI) 0x01C4 165C MDCFG23 Module Configuration 23 Register (PWM0) 0x01C4 1660 MDCFG24 Module Configuration 24 Register (PWM1) 0x01C4 1664 MDCFG25 Module Configuration 25 Register (PWM2) 0x01C4 1668 MDCFG26 Module Configuration 26 Register (GPIO) 0x01C4 166C MDCFG27 Module Configuration 27 Register (TIMER0) 0x01C4 1670 MDCFG28 Module Configuration 28 Register (TIMER1) 0x01C4 1674 - 0x01C4 169B - Reserved 0x01C4 169C MDCFG39 Module Configuration 39 Register (C64x+ CPU) 0x01C4 16A0 MDCFG40 Module Configuration 40 Register (VICP) 0x01C4 16A4 - 0x01C4 17FF - Reserved 0x01C4 1800 MDSTAT0 Module Status 0 Register (VPSS DMA) 0x01C4 1804 MDSTAT1 Module Status 1 Register (VPSS MMR) 0x01C4 1808 MDSTAT2 Module Status 2 Register (EDMACC) 0x01C4 180C MDSTAT3 Module Status 3 Register (EDMATC0) 0x01C4 1810 MDSTAT4 Module Status 4 Register (EDMATC1)

PSC Register Memory Map (continued)

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PSC Register Memory Map (continued)

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1814 MDSTAT5 Module Status 5 Register (EMAC) 0x01C4 1818 MDSTAT6 Module Status 6 Register (EMAC Memory Controller) 0x01C4 181C MDSTAT7 Module Status 7 Register (MDIO) 0x01C4 1820 Reserved 0x01C4 1824 MDSTAT9 Module Status 9 Register (USB) 0x01C4 1828 MDSTAT10 Module Status 10 Register (ATA/CF) 0x01C4 182C MDSTAT11 Module Status 11 Register (VLYNQ) 0x01C4 1830 Reserved 0x01C4 1834 MDSTAT13 Module Status 13 Register (DDR2) 0x01C4 1838 MDSTAT14 Module Status 14 Register (EMIFA) 0x01C4 183C MDSTAT15 Module Status 15 Register (MMC/SD) 0x01C4 1840 Reserved 0x01C4 1844 MDSTAT17 Module Status 17 Register (ASP) 0x01C4 1848 MDSTAT18 Module Status 18 Register (I2C) 0x01C4 184C MDSTAT19 Module Status 19 Register (UART0) 0x01C4 1850 MDSTAT20 Module Status 20 Register (UART1) 0x01C4 1854 MDSTAT21 Module Status 21 Register (UART2) 0x01C4 1858 MDSTAT22 Module Status 22 Register (SPI) 0x01C4 185C MDSTAT23 Module Status 23 Register (PWM0) 0x01C4 1860 MDSTAT24 Module Status 24 Register (PWM1) 0x01C4 1864 MDSTAT25 Module Status 25 Register (PWM2) 0x01C4 1868 MDSTAT26 Module Status 26 Register (GPIO) 0x01C4 186C MDSTAT27 Module Status 27 Register (TIMER0) 0x01C4 1870 MDSTAT28 Module Status 28 Register (TIMER1) 0x01C4 1874 - 0x01C4 189B - Reserved 0x01C4 189C MDSTAT39 Module Status 39 Register (C64x+ CPU) 0x01C4 18A0 MDSTAT40 Module Status 40 Register (VICP) 0x01C4 18A4 - 0x01C4 19FF - Reserved 0x01C4 1A00 MDCTL0 Module Control 0 Register (VPSS DMA) 0x01C4 1A04 MDCTL1 Module Control 1 Register (VPSS MMR) 0x01C4 1A08 MDCTL2 Module Control 2 Register (EDMACC) 0x01C4 1A0C MDCTL3 Module Control 3 Register (EDMATC0) 0x01C4 1A10 MDCTL4 Module Control 4 Register (EDMATC1) 0x01C4 1A14 MDCTL5 Module Control 5 Register (EMAC) 0x01C4 1A18 MDCTL6 Module Control 6 Register (EMAC Memory Controller) 0x01C4 1A1C MDCTL7 Module Control 7 Register (MDIO) 0x01C4 1A20 Reserved 0x01C4 1A24 MDCTL9 Module Control 9 Register (USB) 0x01C4 1A28 MDCTL10 Module Control 10 Register (ATA/CF) 0x01C4 1A2C MDCTL11 Module Control 11 Register (VLYNQ) 0x01C4 1A30 Reserved 0x01C4 1A34 MDCTL13 Module Control 13 Register (DDR2) 0x01C4 1A38 MDCTL14 Module Control 14 Register (EMIFA) 0x01C4 1A3C MDCTL15 Module Control 15 Register (MMC/SD) 0x01C4 1A40 Reserved 0x01C4 1A44 MDCTL17 Module Control 17 Register (ASP)

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Peripheral and Electrical Specifications 93

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TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

PSC Register Memory Map (continued)

HEX ADDRESS RANGE DESCRIPTION

0x01C4 1A48 MDCTL18 Module Control 18 Register (I2C) 0x01C4 1A4C MDCTL19 Module Control 19 Register (UART0) 0x01C4 1A50 MDCTL20 Module Control 20 Register (UART1) 0x01C4 1A54 MDCTL21 Module Control 21 Register (UART2) 0x01C4 1A58 MDCTL22 Module Control 22 Register (SPI) 0x01C4 1A5C MDCTL23 Module Control 23 Register (PWM0) 0x01C4 1A60 MDCTL24 Module Control 24 Register (PWM1) 0x01C4 1A64 MDCTL25 Module Control 25 Register (PWM2) 0x01C4 1A68 MDCTL26 Module Control 26 Register (GPIO) 0x01C4 1A6C MDCTL27 Module Control 27 Register (TIMER0) 0x01C4 1A70 MDCTL28 Module Control 28 Register (TIMER1) 0x01C4 1A74 - 0x01C4 1A9B - Reserved 0x01C4 1A9C MDCTL39 Module Control 39 Register (C64x+ CPU) 0x01C4 1AA0 MDCTL40 Module Control 40 Register (VICP) 0x01C4 1AA4 - 0x01C4 1FFF - Reserved 0x01C4 1000 MPFAR Memory Protection Fault Address Register 0x01C4 1004 MPFSR Memory Protection Fault Status Register 0x01C4 1008 MPFCR Memory Protection Fault Command Register 0x01C4 100C MPAA Memory Protection Page Attribute Register 0x01C4 1010 - 0x01C4 1FFF - Reserved

5.3.1.5 Triggering, Wake-up, and Effects

Table 5-5 summarizes the DM6446 power-down modes, trigger, wake-up method, and effect on the

DM6446. For more details, see the Documentation Support section for the ARM Subsystem User's Guide.

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 5-5. Characteristics of the Power-Down Modes

POWER-

DOWN TRIGGER/ENTRY WAKE-UP METHOD EFFECT ON CHIP'S OPERATION

MODE

Standby PSC, System Module, PLLC1/2, Interrupts This mode consumes the lowest power,

Low Power PSC, System Module, PLLC1/2, Interrupts This mode is for ARM to sustain some

Preview PSC, System Module, PLLC1/2 Interrupts This mode is for Digital Still Camera

Active PSC, System Module, PLLC1/2 N/A The entire chip is powered. All modules

DDR2 Memory Controller, ARM with the minimum set of modules kept

Wait For Interrupt instruction alive that are required to wake up the

chip to a higher power mode. DSP and coprocessor subsystems are not powered. The rest of the chip is powered and clocks are suspended, except for GPIO (interrupts), UARTs, I2C (in slave mode), and Ethernet MAC. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. DDR2 clock is suspended and DDR2 is put into self-refresh mode.

DDR2 Memory Controller basic control functions. DSP and

coprocessor subsystems are not powered. The rest of the chip is powered, but most clocks are suspended, except for ARM, GPIO, UARTs, SPI, I2C, PWMs, and Timers. PLLs are operating in bypass mode. 27-MHz clock is the only clock available to the system. ARM runs at 13.5 MHz, and handles all peripherals by direct access. DDR2 clock is suspended and DDR2 is put into self-refresh mode. ARM will not have access to DDR2 and its caches are either frozen or inaccessible.

(DSC) preview. DSP and coprocessor subsystems are not powered. The rest of the chip is powered, and the PLLs are operating to support the activities needed for preview processing and data flow. ARM and DDR2 EMIF operate at nominal frequencies.

operate at nominal clock frequency. Unused peripherals have their clocks suspended. Active peripherals have their clocks suspended when unneeded.

5.3.1.6 DM6446 Power-Down Mode with an Emulator

TBD

5.4 Reset

DM6446 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset, C64x+ local reset, and module reset are summarized in Table 5-6 .

Table 5-6. DM6446 Resets

Type Initiator Description

Power-on-reset (POR) RESET pin active low while TRST is low. Global chip reset (Cold reset). Activates the POR signal

on chip, which is used to reset test and emulation logic.

Warm reset RESET pin active low while TRST is high. Resets everything except for test and emulation logic.

ARM emulator stays alive during warm reset, but the C64x+ emulator does not.

Maximum reset Emulator, WD Timer Same as Warm reset, except for initiators.

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Table 5-6. DM6446 Resets (continued)

Type Initiator Description

System reset Software (register bit) This is a soft reset that maintains memory contents and

C64x+ Local reset Software (register bit) MMR controls the C64x+ reset input. This is used for

Power-on-reset (POR) is the global chip reset and it affects test, emulation, and other circuitry. It is invoked by driving the RESET pin active low while TRST is held low. A POR is required to place DM6446 into a known good initial state. POR can be asserted prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be asserted (held low) during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and if an external 27 MHz oscillator is used on the MXI/CLKIN pin, the external clock should also be running at the correct frequency.

Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a C64x+ emulator session will not.

Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the maximum reset initiators can be masked by the ARM emulator.

does not affect clocks or power states.

control of C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive when in local reset.

System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test, emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets.

The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be accessible, including access to the VICP memory through the L2 port (UMAP port).

Refer to the ARM Subsystem User's Guide for details on reset control/status registers. For information on peripheral selection at the rising edge of RESET, see the Device Configuration section

of this data manual.

5.4.1 Reset Electrical Data/Timing

Table 5-7. Timing Requirements for Reset

NO. UNIT

1 t

w(RESET)

2 t

su(BOOT)

3 t

h(BOOT)

(1) For proper RESET operation, the RSV5 pin must be driven low or tied directly to Vssat all times and the user must not switch values

throughout device operation. (2) BTSEL[1:0], DSP_BT, and AEAW[4:0] are the boot configuration pins during device reset. (3) C = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37. 037 ns.

Active low width of the RESET pulse 12C ns Setup time, boot configuration bits valid before RESET rising edge 1 µs Hold time, boot configuration bits valid after RESET rising edge 1 µs

(1) (2) (3)

(see Figure 5-7 )

-594

MIN MAX

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TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Table 5-8. Switching Characteristics Over Recommended Operating Conditions During Reset (see

Figure 5-7 )

NO. PARAMETER UNIT

4 t

d(PLL_LOCK)

Delay time, RESET rising edge to PLL1 locked internally 500 µs

-594

MIN MAX

Figure 5-7. Reset Timing TBD

Peripheral and Electrical Specifications 97

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PRODUCT PREVIEW

MXI/CLKIN MXO

C1 C2

Crystal

MXV

27 MHz

1.8 V

MXV



1C2

(C1 C2)

TMS320DM6446 Digital Media System on-Chip

SPRS283 – DECEMBER 2005

5.5 Oscillators

DM6446 has two oscillator input/output pairs (MXI/MXO and M24XI/M24XO) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 27 MHz (MXI/MXO) and 24 MHz (M24XI/M24XO). Optionally, the oscillator inputs are configurable for use with external oscillators.

5.5.1 27-MHz System Oscillator

The 27-MHz oscillator provides the reference clock for all DM6446 subsystems and peripherals, with the exception of USB. The on-chip oscillator requires an external 27-MHz crystal connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 5-8 . The external crystal load capacitors must be connected only to the 27-MHz oscillator ground pin (MXV ground (V

). Do not connect to board

The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (MXI and MXO) and to the MXV

Table 5-9. Switching Characteristics Over Recommended Operating Conditions for 27-MHz System

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start-up time (from power up until oscillating at stable frequency of 27 MHz)

, active current consumption TBD µ A

DDA

Oscillaton frequency 27 MHz

5.5.2 24-MHz USB Oscillator

The 24-MHz oscillator provides the reference clock for the DM6446 USB peripheral. The on-chip oscillator requires an external 24-MHz crystal connected across the M24XI and M24XO pins, along with two load capacitors, as shown in Figure 5-9 .The external crystal load capacitors must be connected only to the 24-MHz oscillator ground pin (M24V

Figure 5-8. 27-MHz System Oscillator

Oscillator

C1 = C2 = TBD pF, CV

). Do not connect to board ground (V

pin.

= TBD V TBD TBD ms

98 Peripheral and Electrical Specifications

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M24XI M24XO

C1 C2

Crystal

M24V

24 MHz

1.8 V

M24V



1C2

(C1 C2)

TMS320DM6446

Digital Media System on-Chip

SPRS283 – DECEMBER 2005

Figure 5-9. 24-MHz USB Oscillator

pin.

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Table 5-10. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System

Oscillator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start-up time (from power up until oscillating at stable frequency of 24 MHz)

, active current consumption TBD µ A

DDA

Oscillaton frequency 24 MHz

C1 = C2 = TBD pF, CV

= TBD V TBD TBD ms

Peripheral and Electrical Specifications100

Texas Instruments TMX 320 DM 6446 INSTALLATION INSTRUCTIONS

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

1.2 Description

1.3 Functional Block Diagram

2 Device Overview

2.1 Device Characteristics

2.2 Device Compatibility

2.3 ARM Subsystem

2.3.1 ARM926EJ-S RISC MPU

2.3.2 CP15

2.3.3 MMU

2.3.4 Caches and Write Buffer

2.3.5 Tightly Coupled Memory (TCM)

2.3.6 Advanced High-performance Bus (AHB)

2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

2.3.8 ARM Memory Mapping

2.3.9 Peripherals

2.3.10 PLL Controller (PLLC)

2.3.11 Power and Sleep Controller (PSC)

2.3.12 ARM Interrupt Controller (AINTC)

2.3.13 System Module

2.3.14 Power Management

2.4 DSP Subsystem

2.4.1 C64X+ DSP CPU Description

2.4.2 DSP Memory Mapping

2.4.3 Peripherals

2.4.4 DSP Interrupt Controller

2.5 Memory Map Summary

2.6 Pin Assignments

2.6.1 Pin Map (Bottom View)

2.6.2 Signal Groups Description

2.7 Terminal Functions

2.8 Device Support

2.8.1 Development Support

2.8.2 Device and Development-Support Tool Nomenclature

2.8.3 Documentation Support

3 Device Configuration

3.1 System Module Registers

3.2 Power Considerations

3.2.1 Power Configurations at Reset

3.2.2 Power Configurations after Reset

3.3 Clocks Considerations

3.3.1 Clock Configurations at Reset

3.3.2 Clock Configurations after Power-On/Hard Reset

3.4 Bootmode

3.4.1 Bootmode Registers

3.4.2 ARM Boot

3.4.3 DSP Boot

3.5 Configurations at Reset

3.5.1 Device Configuration at Device Reset

3.5.2 Peripheral Selection at Device Reset

3.6 Configurations After Reset

3.6.1 Switched Central Resource (SCR) Bus Priorities

3.6.2 Multiplexed Pin Configurations

3.6.3 Peripheral Selection After Device Reset

3.6.4 PINMUX0 Register Description

3.6.5 PINMUX1 Register Description

3.6.6 Pin Multiplexing Register Field Details

3.7 Emulation Control

3.8 Debugging Considerations

3.9 Configuration Examples

4 Device Operating Conditions

4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

4.2 Recommended Operating Conditions

5 Peripheral and Electrical Specifications

5.1 Parameter Information

5.1.1 Parameter Information Device-Specific Information

5.2 Recommended Clock and Control Signal Transition Behavior

5.3 Power Supplies

5.3.1 Power-Supply Sequencing

5.4 Reset

5.4.1 Reset Electrical Data/Timing

5.5 Oscillators

5.5.1 27-MHz System Oscillator

5.5.2 24-MHz USB Oscillator