Texas Instruments TMS370C156AFNT, TMS370C150AFNT, TMS370C758AFNT, TMS370C756ANMT, TMS370C756AFNT Datasheet

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

D

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 4K to 48K Bytes – EPROM: 16K to 48K Bytes

– ROM-less – Data EEPROM: 256 or 512 Bytes – Static RAM: 256 to 3.5K Bytes – External Memory/Peripheral Wait States – Precoded External Chip-Select Outputs

in Microcomputer Mode

D

Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive

T emperature Ranges – Clock Options

– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

– Divide-by-1 (2 MHz – 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Supply Voltage (V

CC

): 5 V ± 10%

D

Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1)

D

Two 16-Bit General-Purpose Timers

D

On-Chip 24-Bit Watchdog Timer

D

Two Communication Modules – Serial Communications Interface 1 (SCI1) – Serial Peripheral Interface (SPI)

D

Flexible Interrupt Handling

D

TMS370 Series Compatibility

D

CMOS/Package/TTL-Compatible I/O Pins – 64-Pin Plastic and Ceramic Shrink

Dual-In-Line Packages/44 Bidirectional,

9 Input Pins – 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages/46 Bidirectional,

9 Input Pins – All Peripheral Function Pins Are

Software Configurable for Digital I/O

D

Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FN/FZ PACKAGE

(TOP VIEW)

V

SS1

B7

C2C1MC

C0

B6

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

XTAL2/CLKIN

XTAL1

C3 C4 C5 C6 C7

SPISOMI

SPICLK

SPISIMO

T1IC/CR T1PWM T1EVT

9876543

10 11 12 13 14 15 16

B5B0B4B3B2

B1

D0/CSE2/OCF

V

CC2VSS2VCC1

2 1 686766 65 64 63 62 61

27 28 29 30 31 32 3334 35 36 37 38 39 4041 42 43

V

CC3

V

SS3

V

CC1

17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54

53 52 51 50 49 48 47 46 45 44

V

CC2

V

SS2

A0 A1 A2 A3 A4 A5 A6 A7

T2AEVT

T2AIC2/PWM

INT1 INT2 INT3

D1/CSH3 D2/CSH2 D3/SYSCLK

D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

JN/NM PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

B5 B6 B7 C0

MC

C1 C2

V

SS1

C3 C4 C5 C6 C7

AN0

A0 A1 A2 A3 A4 A5 A6 A7

T2AEVT

T2AIC2/PWM

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

XTAL2/ CLKIN

XTAL1

V

CC1

V

CC3

B4 B3 B2 B1 B0 D0/CSE2

/OCF

V

SS1

V

CC1

D1/CSH3 D3/SYSCLK D4/R/W D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM AN7 T1EVT V

SS1

AN6 AN5 AN4 AN3

AN1

AN2

V

SS3

TMS370Cx5x 8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions

ÁÁ

NAME

ALTERNATE

FUNCTION

SDIP

(64)

LCC

(68)

I/O

†

DESCRIPTION

‡

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

A0 A1 A2 A3 A4 A5 A6 A7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7

Á

15 16 17 18 19 20 21 22

Á

17 18 19 20 21 22 23 24

Á

I/O

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0–DATA7).

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

B0 B1 B2 B3 B4 B5 B6 B7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7

Á

60 61 62 63 64

1 2 3

Á

65 66 67 68

1 2 3 4

Á

I/O

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0–ADDR7).

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

C0 C1 C2 C3 C4 C5 C6 C7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ADDR8

ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15

Á

4 6 7

9 10 11 12 13

Á

5 7

8 10 11 12 13 14

Á

I/O

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8–ADDR15).

ÁÁÁ

Á

ÁÁÁ

Á

INT1 INT2 INT3

ÁÁÁÁ

Á

ÁÁÁÁ

Á

NMI

— —

Á

50 49 48

Á

52 51 50

Á

I I/O I/O

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

E0 E1 E2 E3 E4 E5 E6 E7

Á

14 34 35 36 37 38 39 42

Á

36 37 38 39 40 41 42 43

Á

I

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ББББББББББББББББББ

Á

ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7) Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input.

ÁÁÁ

Á

V

CC3

V

SS3

ÁÁÁÁÁÁ

Á

32 33

Á

34 35

ÁÁББББББББББББББББББ

Á

ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin

ÁÁÁ

Á

RESET

ÁÁÁÁÁÁ

Á

51

Á

53

Á

I/O

ББББББББББББББББББ

Á

System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET

indicates an internal failure was detected by the

watchdog or oscillator fault circuit.

ÁÁÁ

Á

MC

ÁÁÁÁÁÁ

Á

5

Á

6

Á

I

ББББББББББББББББББ

Á

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP.

ÁÁÁ

Á

XTAL2/CLKIN XTAL1

ÁÁÁÁÁÁ

Á

29 30

Á

31 32

Á

I

O

ББББББББББББББББББ

Á

Internal oscillator crystal input/external clock source input Internal oscillator output for crystal

V

CC1

31, 57

33,

61

Positive supply voltage

V

CC2

—

15,63

Positive supply voltage

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions (Continued)

ÁÁÁ

Á

NAME

ÁÁÁÁ

Á

ALTERNATE

FUNCTION

Á

SDIP

(64)

Á

LCC

(68)

I/O

†

БББББББББББББББББ

Á

DESCRIPTION

‡

V

SS1

8,

58,40

9

Ground reference for digital logic

V

SS2

—

16,62

Ground reference for digital I/O logic

ÁÁÁÁÁÁÁÁ

Á

FUNCTION

ÁÁÁ

Á

БББББББББББББББББ

Á

Single-chip mode: Port D is a general-purpose bidirectional I/O port. Each of the port D pins can be individually configured as a general-purpose I/O pin, p

ÁÁÁÁÁ

Á

A

ÁÁ

Á

B

ÁÁÁ

Á

БББББББББББББББББ

Á

primary memory control signal (function A), or secondary memory control

signal (function B). All chip selects are independent and can be used for memory bank switching. Refer to Table 1 for function A memory accesses.

D0

CSE2

OCF

59

64

I/O pin A: Chip select eighth output 2 goes low during memory accesses I/O pin B: Opcode fetch goes low during the opcode fetch memory cycle.

ÁÁÁ

Á

D1

Á

CSH3

ÁÁ

Á

—

Á

56

Á

60

БББББББББББББББББ

Á

I/O pin A: Chip select half output 3 goes low during memory accesses. I/O pin B: Reserved

ÁÁÁ

Á

D2

Á

CSH2

ÁÁ

Á

—

Á

—

Á

59

БББББББББББББББББ

Á

I/O pin A: Chip select half output 2 goes low during memory accesses. I/O pin B: Reserved

D3

SYSCLK

55

58

I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency.

D4

R/W

54

57

I/O

I/O pin A, B: Read/write output pin

ÁÁÁ

Á

D5

Á

CSPF

ÁÁ

Á

—

Á

—

Á

56

I/O

БББББББББББББББББ

Á

I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses. I/O pin B: Reserved

ÁÁÁ

Á

ÁÁÁ

Á

D6

Á

CSH1

ÁÁ

Á

ÁÁ

Á

EDS

Á

53

Á

55

БББББББББББББББББ

Á

БББББББББББББББББ

Á

I/O pin A: Chip select half output 1 goes low during memory accesses. I/O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects.

D7

CSE1

WAIT

52

54

I/O pin A: Chip select eighth output goes low during memory accesses. I/O pin B: Wait input pin extends bus signals.

ÁÁÁ

Á

SCITXD SCIRXD SCICLK

ÁÁÁÁ

Á

SCIIO1 SCIIO2 SCIIO3

Á

28 27 26

Á

30 29 28

I/O

БББББББББББББББББ

Á

SCI transmit data output pin/general-purpose bidirectional pin (see Note 1) SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

T1IC/CR T1PWM T1EVT

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T1IO1 T1IO2 T1IO3

Á

44 43 41

Á

46 45 44

I/O

БББББББББББББББББ

Á

БББББББББББББББББ

Á

БББББББББББББББББ

Á

Timer1 input capture/counter reset input pin/general-purpose bidirectional pin Timer1 pulse-width-modulation (PWM) output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

T2AIC1/CR T2AIC2/PWM T2AEVT

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T2AIO1 T2AIO2 T2AIO3

Á

25 24 23

Á

27 26 25

I/O

БББББББББББББББББ

Á

БББББББББББББББББ

Á

Timer2A input capture 1/counter reset input pin/general-purpose bidirectional pin Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer2A external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

SPISOMI SPISIMO SPICLK

ÁÁÁÁ

Á

SPIIO1 SPIIO2 SPIIO3

Á

47 46 45

Á

49 48 47

I/O

БББББББББББББББББ

Á

SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.

NOTE 1: The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A: Memory Accesses Locations for ‘x5x Devices

FUNCTION A

‘X50, ‘X52, ‘X53, AND ‘X56

‘X58

‘X59

CSEx

2000h – 3FFFh (8K bytes)

A000h – BFFFh (8K bytes)

E000h – EFFFh (4K bytes)

CSHx

8000h – FFFFh (32K bytes)

C000h – FFFFh (16K bytes)

F000h – FFFFh (4K bytes)

CSPF

10C0h – 10FFh (64 bytes)

TMS370Cx5x 8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Program Memory

ROM: 4K, 8K, 12K, 16K,

32K, or 48K Bytes

EPROM: 16K, 32K, or

48K Bytes

V

SS1

V

CC1

RESET

MCXTAL2/

CLKIN

XTAL1INT3INT2INT1

E0–E7

or

AN0–AN7

V

CC2

V

SS2

Data EEPROM

0, 256, or 512 Bytes

RAM

256, 512, 1K, 1.5K, or

3.5K Bytes

CPU

Port D

†

Port C

Port B

Watchdog

Timer 1

Timer 2A

Serial

Communications

Interface 1

Serial

Peripheral

Interface

Analog-to-Digital

Converter 1

System Control

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

T1PWM

T1EVT

T1IC/CR

T2AIC2/PWM

T2AEVT

T2AIC1/CR

SCICLK

SCITXD

SCIRXD

SPICLK

SPISIMO

SPISOMI

V

SS3

V

CC3

Port A

Interrupts

8/6888

Memory Expansion

Data

Address LSbyte

Address MSbyte

Control

†

For the 64-pin devices, there are only six pins for port D.

description

The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families: the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x.

The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory configuration overview of the TMS370Cx5x devices.

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

Table 2. Memory Configurations

DEVICE

PROGRAM

MEMORY

(BYTES)

OFF-CHIP

MEMORY

DATA MEMORY

(BYTES)

OPERATING

MODES

PACKAGES

68 PIN PLCC/CLCC, OR

ROM EPROM

EXP. (BYTES)

RAM EEPROM µC†µP

†

64 PIN PSDIP/CSDIP

TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350

TMS370C050A

4K

—

112K

256

√

FN – PLCC / NM –PSDIP

TMS370C150A

—

56K

256

—

√

FN – PLCC

TMS370C250A

—

56K

256

—

√

FN – PLCC

TMS370C350A

4K

—

112K

256

—

√

FN – PLCC / NM –PSDIP

TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452

TMS370C052A

8K

—

112K

256

√

FN – PLCC / NM –PSDIP

TMS370C352A

8K

—

112K

256

—

√

FN – PLCC / NM –PSDIP

TMS370C452A

‡

8K

—

112K

256

√

FN – PLCC

TMS370Cx53: TMS370C353

TMS370C353A

12K

—

112K

1.5K

—

√

FN – PLCC

TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756

TMS370C056A

16K

—

112K

512

√

FN – PLCC / NM –PSDIP

TMS370C156A

—

56K

512

—

√

FN – PLCC

TMS370C256A

—

56K

512

—

√

FN – PLCC

TMS370C356A

16K

—

112K

512

—

√

FN – PLCC / NM –PSDIP

TMS370C456A

‡

16K

—

112K

512

√

FN – PLCC

TMS370C756A

—

16K

112K

512

√

FN – PLCC / NM –PSDIP

TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758

TMS370C058A

32K

—

64K

1K

256

√

FN – PLCC / NM –PSDIP

TMS370C358A

32K

—

64K

1K

—

√

FN – PLCC / NM –PSDIP

ББББББ

Á

TMS370C758A, TMS370C758B

Á

—

ÁÁ

Á

32K

ÁÁÁ

Á

64K

Á

1K

ÁÁ

Á

256

Á

√

Á

√

ББББББ

Á

FN – PLCC / NM –PSDIP

TMS370Cx59: TMS370C059 AND TMS370C759

TMS370C059A

§

48K

—

20K

3.5K

256

√

FN – PLCC

TMS370C759A

§

—

48K

20K

3.5K

256

√

FN – PLCC

EPROM DEVICE: SE370C756, SE370C758, and SE370C759

SE370C756A

¶

—

16K

112K

512

√

FZ – CLCC / JN –CSDIP

ББББББ

SE370C758A¶, SE370C758B

¶

Á—ÁÁ

32K

ÁÁÁ

64K

Á1KÁÁ

256

Á√Á√ББББББ

FZ – CLCC / JN –CSDIP

SE370C759A

§¶

—

48K

20K

3.5K

256

√

FZ – CLCC

†

µC – Microcomputer mode µP – Microprocessor mode

‡

TMS370C45x support ROM memory security. Refer to the program ROM section.

§

Only operate up to 3 MHz SYSCLK

¶

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

TMS370Cx5x 8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 3. Suffix Letter Configuration

DEVICE

†

WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (Standard oscillator) Enabled EPROM B Hard Divide-by-1 (PLL) Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled

Simple

ROM-less A Standard Divide-by-4 Enabled

†

Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x refer to the individual devices listed in T able 2 and described in this data sheet. All TMS370Cx5x devices contain the following on-chip peripheral modules:

D

Eight-channel, 8-bit analog-to-digital converter 1 (ADC1)

D

Serial communications interface 1 (SCI1)

D

Serial peripheral interface (SPI)

D

One 24-bit general-purpose watchdog timer

D

Two 16-bit general-purpose timers (one with an 8-bit prescaler)

TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available in plastic packages. This microcomputer is effective to use for immediate production updates for other members of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost mask ROM devices is not practical.

The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of the program EPROM memory during the development/prototyping phase of design. The SE370C75x devices allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family.

The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1 allows standard RS-232-C communications interface between other common data transmission equipment, while the SPI gives high-speed communications between simpler shift-register type devices, such as display drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.

TMS370Cx5x

8-BIT MICROCONTROLLER

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description (continued)

For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I/O) pins when operating in the microcomputer mode.

The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDS) and compact development tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family XDS development tools communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

modes

The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET

goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list.

D

Microcomputer single chip mode: – Operates as a self-contained microcomputer with all memory and peripherals on-chip. – Maximizes the general-purpose I/O capability for real-time control applications.

D

Microcomputer with external expansion mode: – Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active.

– Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows: – Port A: 8-bit data memory – Port B and C: 16-bit address memory – Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O)

– Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually.

– Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed).

XDS and CDT are trademarks of Texas Instruments Incorporated.

TMS370Cx5x 8-BIT MICROCONTROLLER

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modes (continued)

– Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions.

– Function A maps up to 112K bytes of external memory into the address space by using CSE1 , CSE2,

CSH1

, CSH2, and CSH3 as memory-bank selects under software control.

– Function B maps up to 40K bytes of external memory into the address space by using EDS

under

software control.

D

Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

D

Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external

bus interface. – Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

register accomplishes this.)

memory/peripheral wait operation

The TMS370Cx5x enhances interface flexibility by providing WAIT -state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT

-input pin. The CPU continues to wait as

long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller.

Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions and memory and peripheral accesses automatically, thus making every external access a minimum of three system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states

can be used in conjunction with the external WAIT pin. In applications where the external device

read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost.

TMS370Cx5x

8-BIT MICROCONTROLLER

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CPU

The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The ’x5x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers and memory blocks.

0000h

0200h 0400h

1000h 10C0h 1100h

1F00h

Interrupts and Reset Vectors;

Trap Vectors

0600h

FFFFh

0

RAM (Includes 256-Byte Registers File)

015

Program Counter

7

Legend:

Z=Zero

IE1=Level1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level2 interrupts Enable

IE1IE2ZNC

01234567

V

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R3

R127

0000h 0001h

0002h

007Fh

R255

0003h

R2

00FFh

Reserved

†

16K-Byte ROM/EPROM (4000h–7FFFh)

1E00h

0100h

0E00h

12K-Byte ROM (5000h–7FFFh)

8K-Byte ROM (6000h–7FFFh)

32K-Byte ROM/EPROM (2000h–9FFFh)

48K-Byte ROM/EPROM (2000h–DFFFh)

Memory Expansion

2000h 4000h 5000h 6000h 7000h

7FC0h

8000h

A000h

E000h

256-Byte RAM (0000h–00FFh)

512-Byte RAM (0000h–01FFh)

1K-Byte RAM (0000h–03FFh)

1.5K-Byte RAM (0000h–05FFh)

3.5K-Byte RAM (0000h–0DFFh)

Peripheral File

Peripheral Exp

Reserved

†

512-Byte (1E00h–1FFFh)

Data EEPROM

256-Byte (1F00h–1FFFh)

4K-Byte ROM (7000h–7FFFh)

†

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

TMS370Cx5x 8-BIT MICROCONTROLLER

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CPU (continued)

The ’x5x CPU architecture provides the following components:

D

CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits – A program counter (PC) that points to the memory location of the next instruction to be executed

D

A memory map that includes : – 256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage,

program instructions, general-purpose register, or the stack (can be located only in the first 256 bytes) – A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control – 256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in

power-off conditions – 4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory . T ypically the stack is used to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits:

D

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use these status bits to determine program flow.

D

The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

7

6

5

4

3

2

1

0

C

N

Z

V

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

TMS370Cx5x

8-BIT MICROCONTROLLER

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CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Memory

Program Counter (PC)

60 00

PCH PCL

60 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. In the expansion mode, external memory peripherals are also memory-mapped into this common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM, EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh.

TMS370Cx5x 8-BIT MICROCONTROLLER

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memory map (continued)

Reset

7FFEh–7FFFh

Interrupt 1

7FFCh–7FFDh

Interrupt 2

7FFAh–7FFBh

Interrupt 3

7FF8h–7FF9h

Serial Peripheral I/F

7FF6h–7FF7h

Timer 1

7FF4h–7FF5h

Serial Comm I/F RX

7FF2h–7FF3h

Serial Comm I/F TX

7FF0h–7FF1h

Timer 2A

7FEEh–7FEFh

ADC1

7FECh–7FEDh

7FE0h–7FFBh

Reserved

†

7FC0h–7FDFh

Trap 15–0

Vectors

Peripheral File Control

Registers

Reserved

†

1080h–108Fh

ADC1 Peripheral

Control

1070h–107Fh

Timer 2A Peripheral

Control

1060h–106Fh

SCI1 Peripheral

Control

1050h–105Fh

Timer 1 Peripheral

Control

1040h–104Fh

SPI Peripheral

Control

1030h–103Fh

Digital Port Control

1020h–102Fh

System Control

1010h–101Fh

1000h–100Fh

Reserved

†

External

Reserved

†

10C0h

7FC0h

Memory Expansion

48K-Byte ROM

(2000h–DFFFh)

32K-Byte ROM (2000h–9FFFh)

Interrupts and

Reset Vectors;

Trap Vectors

4K-Byte ROM

(7000h–7FFFh)

8K-Byte ROM

(6000h–7FFFh)

12K-Byte ROM (5000h–7FFFh)

16K-Byte ROM

(4000h–7FFFh)

256-Byte Data

EEPROM

(1F00h–1FFFh)

512K-Byte Data

EEPROM

(1E00h–1FFFh)

Reserved

†

Peripheral Expansion

Peripheral File

Reserved

†

3.5K-Byte RAM (0000h–0DFFh)

1.5K-Byte RAM (0000h–05FFh)

1K-Byte RAM

(0000h–03FFh)

512-Byte RAM

(0000h–01FFh)

256-Byte RAM

(0000h–00FFh)

(Register File/Stack)

0000h

0100h

0200h

0400h

0E00h

1000h

1100h

1E00h

1F00h

2000h

4000h

6000h

7000h

8000h

A000h

E000h

FFFFh

0600h

5000h

’X50

Microprocessor Mode

¶

’X52

’X53

’X56

’X58

’X59

Reserved

†

External

Reserved

†

’X50

Microprocessor With

Internal Program

Memory

’X52

’X53

’X56

’X58

’X59

Reserved

†

External

Reserved

†

Reserved

†

Reserved

†

’X59

’X58

’X56

’X53

’X52

Microcomputer

Mode With External

Expansion

’X50

5000h

’X50

0600h

Microcomputer

Single Chip Mode

FFFFh

E000h

A000h

8000h

7000h

6000h

4000h

2000h

1F00h

1E00h

1100h

10C0h

1000h

0E00h

0400h

0200h

0100h

0000h

’X52

’X53

’X56

’X58

’X59

Not Available

‡

Not Avail-

able

‡

(N/A)

Reserved

†

On-Chip For TMS370Cx59 Devices On-Chip For TMS370Cx58 Devices

On-Chip For TMS370Cx56 Devices On-Chip For TMS370Cx53 Devices

On-Chip For TMS370Cx52 Devices On-Chip For TMS370Cx50 Devices

N/A

‡

N/A

‡

N/A

‡

External

§

External

§

External

§

†

Reserved = the address space is reserved for future expansion.

‡

Not available (N/A) = address space unavailable in the mode illustrated.

§

Precoded chip select outputs available on external expansion bus.

¶

Microprocessor mode is designed for ROM-less devices (’x50 and ’x56). ROM and EPROM devices can also be used in this mode but all on-chip memory is ignored.

Figure 3. TMS370Cx5x Memory Map

TMS370Cx5x

8-BIT MICROCONTROLLER

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RAM/register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in Table 5 along with other ’x5x devices.

Table 5. RAM Memory Map

‘x50 and ‘x52

‘x56

‘x58

‘x53

‘x59

RAM Size

256 Bytes

512 Bytes

1K Bytes

1.5K Bytes

3.5K Bytes

Memory Mapped

0000h – 00FFh

0000h – 01FFh

0000h – 03FFh

0000h – 05FFh

0000h – 0DFFh

The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two registers, R0 and R1, are also called register A and B, respectively . Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6 shows the TMS370Cx5x peripheral files.

T able 6. TMS370Cx5x Peripheral File Address map

БББББ

Á

ADDRESS RANGE

БББББ

Á

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

Á

DESCRIPTION

1000h–100Fh

P000–P00F

Reserved for factory test

1010h–101Fh

P010–P01F

System and EEPROM/EPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

P030–P03F

Serial peripheral interface registers

1040h–104Fh

P040–P04F

Timer 1 registers

1050h–105Fh

P050–P05F

Serial communication interface 1 registers

1060h–106Fh

P060–P06F

Timer 2A registers

1070h–107Fh

P070–P07F

Analog-to-digital converter 1 registers

1080h–10BFh

P080–P0BF

Reserved

10C0h–10FFh

P0C0–P0FF

External peripheral control

data EEPROM

The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices.

T able 7. Data-EEPROM Memory Map

‘x50, ‘x52, ‘x58, and ‘x59

‘x56

‘X53

Data-EEPROM Size

256 Bytes

512 Bytes

None

Memory Mapped

1F00h–1FFFh

1E00h–1FFFh

None

TMS370Cx5x 8-BIT MICROCONTROLLER

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data EEPROM (continued)

Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s

Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B). The

data EEPROM features include the following:

D

Programming: – Bit, byte, and block write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A. – In-circuit programming capability: There is no need to remove the device to program it.

D

Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

D

Write protection can be overridden by applying 12 V to MC.

Table 8 shows the memory map of the control registers.

T able 8. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

SYMBOL

БББББББББББББББББББ

NAME

P014

EPCTLH

БББББББББББББББББББ

Program EPROM control register – high array

P015–P016

БББББББББББББББББББ

Reserved

P017

INT1

БББББББББББББББББББ

External interrupt 1 control register

P018

INT2

БББББББББББББББББББ

External interrupt 2 control register

P019

INT3

БББББББББББББББББББ

External interrupt 3 control register

P01A

DEECTL

Data EEPROM control register

P01B

БББББББББББББББББББ

Reserved

P01C

EPCTLM

БББББББББББББББББББ

Program EPROM control register – middle array

P01D

БББББББББББББББББББ

Reserved

P01E

EPCTLL

БББББББББББББББББББ

Program EPROM control register – low array

For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device, the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory is controlled by P014, P01C, and P01E.

program EPROM

The ‘370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The ‘370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located at address locations 2000h through 5FFFh, and the second 16K byte array is located at address locations 6000h through 9FFFh. The ’370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h through DFFFh (see Figure 3).

TMS370Cx5x

8-BIT MICROCONTROLLER

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program EPROM (continued)

The EPROM memory map in Table 9 expresses the following:

D

The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at address 101Ch (P01C).

D

For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C).

D

For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is controlled by EPCTLH, located at 1014h (P014).

T able 9. EPROM Memory Map

’756

’758

’759

EPROM size

16K Bytes

32K Bytes

48K Bytes

Memory Mapped

16K

4000h–7FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

Third 16K

A000h–DFFFh

ÁÁÁ

Á

Contol Registers

ÁÁÁÁ

Á

EPCTLM

P01C

ÁÁÁ

Á

EPCTLL

P01E

ÁÁÁÁ

Á

EPCTLM

P01C

ÁÁÁÁ

Á

EPCTLL

P01E

ÁÁÁÁ

Á

EPCTLM

P01C

ÁÁÁ

Á

EPCTLH

P014

Reading the program-EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPCTL. The program EPROM modules’ features include:

D

Programming – In-circuit programming capability if VPP is applied to MC – Control register: Program EPROM programming is controlled by the program EPROM control registers

(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8.

– Programming one EPROM module while executing the other

D

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC

program ROM

The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. ROM security is a feature of the ‘45x devices, which inhibits reading of the data using the programmer.

Table 10. ROM Memory Map

†

‘x50

‘x52

‘x53

‘x56

‘x58

‘x59

ROM Size

4K Bytes

8K Bytes

12K Bytes

16K Bytes

32K Bytes

48K Bytes

Memory Mapped

7000h – 7FFFh

6000h – 7FFFh

5000h – 7FFFh

4000h – 7FFFh

3000h – 9FFFh

2000h – DFFFh

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh.

TI is a trademark of Texas Instruments Incorporated.

TMS370Cx5x 8-BIT MICROCONTROLLER

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system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows:

D

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 User’s

Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B)

for more information.

D

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the

TMS370 User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature

number SPNS014B) for more information.

D

External RESET Pin. A low-level signal can trigger an external reset. T o ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number

SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x5x device to reset external system components. Additionally , if a cold-start condition (V

CC

is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low , then the

reset logic holds the device in a reset state for as long as these actions are active. After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD ST ART , SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 11 lists the reset sources.

Table 11. Reset Sources

REGISTER

ADDRESS

PF

BIT NO.

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

7

COLD START

Cold (power-up)

SCCR0

1010h

P010

4

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

5

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).

2. Registers A and B initialize to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. During RESET

, the two basic operating modes which are the microcomputer and microprocessor modes can be selected by applying the desired voltage level to the dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description).

TMS370Cx5x

8-BIT MICROCONTROLLER

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the status register.

Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx5x has nine hardware system interrupts (plus RESET

) as shown in Table 12. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF . Each interrupt source FLAG bit is individually readable for software polling or determining which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4.

TMS370Cx5x 8-BIT MICROCONTROLLER

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interrupts (continued)

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

T2A PRI

Priority

Overflow

Compare1 Ext Edge

Compare2 Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

SPI INT SPI PRI

SPI

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A/D

TIMER 1

T1 PRI

Overflow

Compare1 Ext Edge

Compare2 Input Capture 1

Watchdog

SCI INT

RX

BRKDT

RXRDY

TX

TXRDY

TXPRI

RXPRI

Figure 4. Interrupt Control

On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources, corresponding addresses, and hardware priorities.

TMS370Cx5x

8-BIT MICROCONTROLLER

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interrupts (continued)

T able 12. Hardware System Interrupts

ББББББББ

Á

INTERRUPT SOURCE

БББББББ

Á

INTERRUPT FLAG

ÁÁÁÁ

Á

SYSTEM

INTERRUPT

БББББ

Á

VECTOR

ADDRESS

ÁÁÁ

Á

PRIORITY

†

ББББББББ

Á

External RESET Watchdog overflow Oscillator fault detect

БББББББ

Á

COLD START WD OVRFL INT FLAG OSC FLT FLAG

ÁÁÁÁ

Á

RESET

‡

БББББ

Á

7FFEh, 7FFFh

ÁÁÁ

Á

1

External INT1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

2

External INT2

INT2 FLAG

INT2

‡

7FFAh, 7FFBh

3

External INT3

INT3 FLAG

INT3

‡

7FF8h, 7FF9h

4

SPI RX/TX complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

5

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow

БББББББ

Á

БББББББ

Á

БББББББ

Á

T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T1INT

§

БББББ

Á

БББББ

Á

БББББ

Á

7FF4h, 7FF5h

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

6

SCI RX data register full SCI RX break detect

RXRDY FLAG BRKDT FLAG

RXINT

‡

7FF2h,7FF3h

7

SCI TX data register empty

TXRDY FLAG

TXINT

7FF0h, 7FF1h

8

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2

БББББББ

Á

БББББББ

Á

БББББББ

Á

T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T2AINT

БББББ

Á

БББББ

Á

БББББ

Á

7FEEh, 7FEFh

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

9

A/D conversion complete

AD INT FLAG

ADINT

7FECh, 7FEDh

10

†

Relative priority within an interrupt level

‡

Releases microcontroller from STANDBY and HALT low-power modes.

§

Releases microcontroller from STANDBY low-power mode.

privileged operation and EEPROM write-protection override

The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the peripheral file. T able 13 displays the system configuration bits that are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

TMS370Cx5x 8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

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privileged operation and EEPROM write-protection override (continued)

Table 13. Privileged Bits

REGISTER

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

SCCRO

ÁÁÁ

Á

P010.5 P010.6

БББББББББ

Á

PF AUTOWAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

БББББББББ

Á

БББББББББ

Á

БББББББББ

Á

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

ÁÁÁ

SPIPRI

ÁÁÁ

Á

ÁÁÁ

Á

P03F.5 P03F.6 P03F.7

БББББББББ

Á

БББББББББ

Á

SPI ESPEN SPI PRIORITY SPI STEST

ÁÁÁ

SCIPRI

ÁÁÁ

Á

P05F.4 P05F.5 P05F.6 P05F.7

БББББББББ

Á

SCI ESPEN SCIRX PRIORITY SCITX PRIORITY SCI STEST

ÁÁÁ

T1PRI

ÁÁÁ

Á

P04F.6 P04F.7

БББББББББ

Á

T1 PRIORITY T1 STEST

ÁÁÁ

T2APRI

ÁÁÁ

Á

P06F.6 P06F.7

БББББББББ

Á

T2A PRIORITY T2A STEST

ÁÁÁ

ADPRI

ÁÁÁ

Á

P07F.5 P07F.6 P07F.7

БББББББББ

Á

AD ESPEN AD PRIORITY AD STEST

†

The privileged bits are shown in a bold typeface in Table 15.

The write-protect override (WPO) mode provides an external hardware method for overriding the write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured.

The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

In the ST ANDBY mode (HAL T/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET

, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial

communications interface 1) is detected.

TMS370Cx5x

8-BIT MICROCONTROLLER

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low-power and IDLE modes (continued)

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET , external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are summarized in Table 14.

Table 14. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

ÁÁÁ

Á

PWRDWN/IDLE

(SCCR2.6)

ÁÁÁÁ

Á

HALT/STANDBY

(SCCR2.7)

БББББББ

Á

MODE SELECTED

1

0

STANDBY

1

HALT

0

X

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ‘x5x ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ‘75xA EPROM has only the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four . The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows

Divide-by-4 option : SYSCLK

+

external resonator frequency

4

+

CLKIN

4

Divide-by-1 option : SYSCLK

+

external resonator frequency 4

4

+

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.

TMS370Cx5x 8-BIT MICROCONTROLLER

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system configuration registers

Table 15 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface and shaded.

Table 15. Peripheral File Frame 1: System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Á

P010

ÁÁÁ

Á

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁ

Á

OSC FLT

FLAG

ÁÁ

Á

MC PIN

WPO

ÁÁÁ

Á

MC PIN

DATA

ÁÁ

Á

—

ÁÁÁ

Á

µP/µC MODE

ÁÁ

Á

SCCR0

P011

—

AUTOWAIT

DISABLE

—

MEMORY DISABLE

—

SCCR1

Á

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁÁ

Á

—

BUS

STEST

CPU

STEST

ÁÁÁ

Á

—

INT1

NMI

PRIVILEGE

DISABLE

ÁÁ

Á

SCCR2

P013 Reserved P014

BUSY

VPPS

—

W0

EXE

EPCTLH

Á

P015

to

P016

Reserved

ÁÁ

Á

P017

INT1

FLAG

INT1

PIN DATA

—

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

INT1

Á

P018

ÁÁÁ

Á

INT2

FLAG

ÁÁ

Á

INT2

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

INT2

DATA DIR

ÁÁ

Á

INT2

DATA OUT

ÁÁÁ

Á

INT2

POLARITY

ÁÁ

Á

INT2

PRIORITY

ÁÁÁ

Á

INT2

ENABLE

ÁÁ

Á

INT2

Á

P019

ÁÁÁ

Á

INT3

FLAG

ÁÁ

Á

INT3

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

INT3

DATA DIR

ÁÁ

Á

INT3

DATA OUT

ÁÁÁ

Á

INT3

POLARITY

ÁÁ

Á

INT3

PRIORITY

ÁÁÁ

Á

INT3

ENABLE

ÁÁ

Á

INT3

P01A

BUSY

—

AP

W1W0

EXE

DEECTL P01B Reserved P01C

BUSY

VPPS

—

W0

EXE

EPCTLM P01D Reserved P01E

BUSY

VPPS

—

W0

EXE

EPCTLL

P01F Reserved

TMS370Cx5x

8-BIT MICROCONTROLLER

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. T able 16 lists the specific addresses, registers, and control bits within this peripheral file frame.

Table 16. Peripheral File Frame 2: Digital Port Control Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P020

Reserved

APORT1

P021

Port A Control Register 2

APORT2

P022

Port A Data

ADATA

P023

Port A Direction

ADIR

P024

Reserved

BPORT1

P025

Port B Control Register 2

BPORT2

P026

Port B Data

BDATA

P027

Port B Direction

BDIR

P028

Reserved

CPORT1

P029

Port C Control Register 2

CPORT2

P02A

Port C Data

CDATA

P02B

Port C Direction

CDIR

P02C

Port D Control Register 1

DPORT1

P02D

Port D Control Register 2

†

DPORT2

P02E

Port D Data

DDATA

P02F

Port D Direction

DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

TMS370Cx5x 8-BIT MICROCONTROLLER

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digital port control registers (continued)

Table 17. Port Configuration Register Setup

INPUT OUTPUT FUNCTION A

FUNCTION B

(µP MODE)

PORT PIN

XPORT1 = 0

†

XPORT2 = 0

XDATA = y

XDIR = 0

XPORT1 = 0

†

XPORT2 = 0

XDATA = q

XDIR = 1

XPORT1 = 0

†

XPORT2 = 1

XDATA = x

XDIR = x

XPORT1 = 1

†

XPORT2 = 1

XDATA = x

XDIR = x A 0–7 Data In y Data Out q Data Bus Reserved B 0–7 Data In y Data Out q Low ADDR Reserved C 0–7 Data In y Data Out q Hi ADDR Reserved

D

0 1 2 3 4 5 6 7

Data In y Data Out q

CSE2 CSH3 CSH2

SYSCLK

R/W CSPF CSH1 CSE1

OCF

— —

SYSCLK

R/W

—

EDS

WAIT

XPORT1 = 1

XPORT2 =0

XDATA = x

XDIR = x

Not defined

†

DPORT only

timer 1 module

The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer resources required to perform realtime system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The T1 module includes three external device pins that can be used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is shown in Figure 5.

Texas Instruments TMS370C156AFNT, TMS370C150AFNT, TMS370C758AFNT, TMS370C756ANMT, TMS370C756AFNT Datasheet

Specifications and Main Features

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User Manual