Texas Instruments TMS370C736AFNT Datasheet

TMS370Cx36

8-BIT MICROCONTROLLER

SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable-EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 16K Bytes

– EPROM: 16K Bytes – Data EEPROM: 256 Bytes – Static RAM: 256 Bytes Usable as

Registers – Standby RAM With Separate Power

Supply Pin: 256 Bytes

Flexible Operating Features – Low-Power Modes: STANDBY and HAL T – Commercial, Industrial, and Automotive

T emperature Ranges – Clock Options

– Divide-by-1 (2 MHz–5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Divide-by-4 (0.5 MHz–5 MHz SYSCLK) – Supply Voltage (V

) 5 V ±10%

Programmable Acquisition and Control Timer (PACT) Module – Input Capture on up to Six Pins, Four of

Which Can Have a Programmable

Prescaler – One Input Capture Pin Can Drive an 8-Bit

Event Counter – Up to Eight Timer-Driven Outputs – Interaction Between Event Counter and

Timer Activity – 18 Independent Interrupt Vectors – Watchdog With Selectable Time-Out

Period – Asynchronous Mini Serial

Communication Interface (Mini SCI)

Flexible Interrupt Handling – Two Software-Programmable Interrupt

Levels – Global- and Individual-Interrupt Masking – Programmable Rising- or Falling-Edge

Detect – Individual-Interrupt Vectors

Serial Peripheral Interface (SPI) – Variable-Length High-Speed Shift

– Synchronous Master/Slave Operation

Eight Channel 8-Bit Analog-to-Digital Converter 1 (ADC1)

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/TTL Compatible I/O Pins/Packages – All Peripheral Function Pins Software

Configurable for Digital I/O – 16 Bidirectional Pins, Nine Input Pins – 44-Pin Plastic and Ceramic Leaded Chip

Carrier (LCC) Packages

Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Multi-Window User Interface – Microcontroller Programmer

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

XTAL2/CLKIN

A5 A4 A3 A2 A1 A0 MC RESET SPICLK SPISOMI SPISIMO

39 38 37 36 35 34 33 32 31 30 29

18 19

7 8 9 10 11 12 13 14 15 16 17

AN3 AN4 AN5 AN6

AN7 D6/CP6 D7/CP5 D4/CP4 D5/CP1

OP1/CP3 OP2/CP2

20 21 22 23

FZ AND FN PACKAGES

(TOP VIEW)

VA7A6

54321644

AN2

AN1

AN0VV

XTAL1

OP7

OP8

INT1

SS1

SCIRXD

SCITXD

OP3

OP4

OP5

OP6

42 41 4043

24 25 26 27 28

CC3

SS3

CC1

CCSTBY

TMS370Cx36 8-BIT MICROCONTROLLER

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Pin Descriptions

44 PINS

NAME

NO.

I/O

†

DESCRIPTION

ÁÁÁ

A0 A1 A2 A3 A4 A5 A6 A7

ÁÁ

34 35 36 37 38 39 40 41

I/O

ББББББББББББББББББББББББ

Port A is a general-purpose bidirectional I/O port.

ÁÁÁ

D3 D4/CP4 D5/CP1 D6/CP6 D7/CP5

ÁÁ

27 14 15 12 13

I/O

ББББББББББББББББББББББББ

Port D is a general-purpose bidirectional port. Also configurable as SYSCLK (see Note 1) PACT input capture 4 (see Note 2) PACT input capture 1 (see Note 2) PACT input capture 6 (see Note 2) PACT input capture 5 (see Note 2)

ÁÁÁ

AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7

ÁÁ

4 5 6 7 8

9 10 11

ББББББББББББББББББББББББ

ADC1 analog input pins (AN0–AN7)/port E digital input pins (E0–E7)

Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog input or positive reference input.

INT1

External interrupt (non-maskable or maskable)/general-purpose input pin

ÁÁÁ

OP1/CP3 OP2/CP2 OP3 OP4 OP5 OP6 OP7 OP8

ÁÁ

16 17 21 22 23 24 25 26

ББББББББББББББББББББББББ

PACT PWM output 1/input capture 3 (see Note 3) PACT output pin 2/input capture 2 (see Note 3) PACT PWM output 3 PACT PWM output 4 PACT PWM output 5 PACT PWM output 6 PACT PWM output 7 PACT PWM output 8

ÁÁÁ

SCIRXD SCITXD

ÁÁ

19 20

ББББББББББББББББББББББББ

PACT mini SCI data receive input pin PACT mini SCI data transmit output pin

ÁÁÁ

SPISOMI SPISIMO SPICLK

ÁÁ

30 29 31

I/O

ББББББББББББББББББББББББ

SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin

RESET

I/O

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET

indicates that an internal failure was detected by watchdog or oscillator fault circuit.

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM V

ÁÁÁ

XTAL2/CLKIN XTAL1

ÁÁ

43 44

ББББББББББББББББББББББББ

Internal oscillator crystal input/External clock source input Internal oscillator output for crystal

ÁÁÁ

CC1

SS1

CC3

SS3

CCSTBY

ÁÁ

1 18

3 42

ББББББББББББББББББББББББ

Positive supply voltage for digital logic and digital I/O pins Ground reference for digital logic and digital I/O pins ADC1 positive supply voltage and optional positive reference input ADC1 ground supply and low reference input pin Positive supply voltage pin for standby RAM

†

I = input, O = output

NOTES: 1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers.

2. These digital I/O buffers are connected internally to some of the PACT module’s input capture pins. This allows the microcontroller to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry.

3. CP2 and CP3 are connected internally to OP2 and OP1. CP2 and CP3 can be used only to capture OP2 and OP1, respectively and not as external capture inputs.

TMS370Cx36

8-BIT MICROCONTROLLER

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functional block diagram

Interrupts

CP1

SCITXD SCIRXD

System Control

Clock Options:

Divide-By-4 or

Divide-By-1 (PLL)

Standby RAM

256 Bytes

Port A Port D

PACT

Watchdog

INT1

E0-E7

AN0-AN7

XTAL1

XTAL2/

CLKIN

SPISOMI SPISIMO SPICLK

Serial

Peripheral

Interface

RESET

SS1

CC1

Program Memory

ROM: 16K Bytes

EPROM: 16K Bytes

Data EEPROM

256 Bytes

A-to-D

Converter 1

CC3

SS3

Mini SCI

CPU

CCSTBY

RAM

256 Bytes

128 BYTES

Dual Port

RAM

CP6 OP1

OP8

. .

description

The TMS370C036, TMS370C736, and SE370C736 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx36 refers to these devices. The TMS370 family provides cost-effective real-time system control through advanced peripheral-function modules and various on-chip memory configurations.

The TMS370Cx36 family of devices uses high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low operating power, wide operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx36 devices attractive for system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications.

All TMS370Cx36 devices contain the following on-chip peripheral modules:

Programmable acquisition and control timer (PACT) – Asynchronous mini SCI – PACT watchdog timer

Serial peripheral interface (SPI)

Eight channel, 8-bit analog-to-digital converter 1 (ADC1)

TMS370Cx36 8-BIT MICROCONTROLLER

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description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx36 devices.

Table 1. Memory Configurations

DEVICE

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

44 PIN PACKAGES

ROM

EPROM

RAM

EEPROM

TMS370C036A

16K

—

512

256

FN – PLCC

TMS370C736A

—

16K

512

256

FN – PLCC

SE370C736A

†

—

16K

512

256

FZ – CLCC

†

System evaluators and development are for use only in prototype environment, and their reliability has not been characterized.

The suffix letter A appended to the device names in Table 1 indicates the configuration of the devices. ROM or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE

‡

CLOCK LOW-POWER MODE

EPROM A Divide-by-4 (Standard oscillator) Enabled

ROM A

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

‡

Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering.

The 16K bytes of mask-programmable ROM in the associated TMS370Cx36 devices are replaced in the TMS370C736 with 16K bytes of EPROM. All other available memory and on-chip peripherals are identical. The OTP (TMS370C736) and reprogrammable (SE370C736) devices are available.

The TMS370C736 OTP device is available in a plastic package. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx36 family or for low-volume production runs when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C736 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development/prototyping phase of design. The SE370C736 device allows quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx36 family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator, the PACT counter, and PACT’s first command / definition entry remain active. This allows the P ACT module to bring the device out of ST ANDBY mode. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx36 features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx36 family is fully instruction-set-compatible, providing easy transition between members of the family.

The TMS370Cx36 has a P ACT module that acts as a timer coprocessor by gathering timing information on input signals and controlling output signals with little or no intervention by the CPU. The coprocessor nature of this module allows for levels of flexibility and power not found in traditional microcontroller timers.

TMS370Cx36

8-BIT MICROCONTROLLER

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description (continued)

The TMS370Cx36 family provides the system designer with an economical, efficient solution to real-time control applications. The PACT compact development tool (CDT) meets the challenge of efficiently developing the software and hardware required to design the TMS370Cx36 into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle.

The TMS370Cx36 family together with the TMS370 PACT CDT370, BP programmer, software tools, SE370C736 reprogrammable devices, comprehensive product documentation, and customer support provides a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU on the TMS370Cx36 device is the high-performance 8-bit TMS370 CPU module. The ’x36 implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x36 instruction map is shown in Table 16.

The ’370Cx36 CPU architecture provides the following components: CPU registers:

A stack pointer (SP) that points to the last entry in the memory stack

A status register (ST) that monitors the operation of the instructions and contains the global interrupt-enable bits

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions, general purpose register, or the stack

256-byte general-purpose standby RAM, which is powered through a separate V

CCSTBY

pin to protect the

memory against power failures on the main V

CC1

pins

128-byte dual-port RAM that contains the capture registers, the circular buffer , and a command/definition area

A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control

256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off conditions

16K-byte ROM or 16K-byte EPROM

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx36 8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

Figure 1 Illustrates the CPU registers and memory blocks.

Reserved

†

Peripheral File

01FFh 0200h

1000h 10BFh 10C0h 1EFFh

1F00h

3FFFh 4000h

Interrupts and Reset Vectors;

Trap Vectors

02FFh 0300h

0FFFh

Reserved

†

7FFFh

RAM (Includes up to 256-Byte Registers File)

015

Program Counter

Legend:

Z=Zero

IE1=Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 interrupts Enable

IE1IE2ZNC

01234567

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R127

0000h 0001h

0002h

007Fh

R255

0003h

00FFh

256-Byte Standby RAM

1FFFh 2000h

7F9Ch

7F9Bh

256-Byte RAM

00FFh 0100h

017Fh 0180h

128-Byte PACT Dual-Port RAM

0000h

Reserved

†

256-Byte Data EEPROM

Reserved

†

16K-Byte ROM/EPROM

Reserved

†

FFFFh

8000h

†

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. T ypically, the stack is used to store the return address on subroutine calls as well as the ST contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits.

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

TMS370Cx36

8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

The ST, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers

IE2

IE1 Reserved Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 4000h as the contents of the reset vector.

Memory

Program Counter (PC)

40 00

PCH PCL

40 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx36 architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx36 provides memory-mapped RAM, ROM, EPROM, data EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file is located between 1000h to 107Fh and is divided logically into eight peripheral file frames of 16 bytes each. The eight PF frames consist of five control frames and three reserved frames.Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information are passed.

TMS370Cx36 8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

256-Byte RAM

Reserved

†

Peripheral File

Reserved

†

128-Byte PACT Dual-Port RAM

7FC0h–7FDFh

PACT Interrupt 1-18

7FEEh–7FF5h

Reserved

†

7FECh–7FEDh

Interrupt 1

Reset

1020h–102Fh

Digital Port Control

Vectors

ADC1

Serial Peripheral Interface

7FFCh–7FFDh 7FFEh–7FFFh

0000h

0100h

00FFh

0200h 02FFh

0300h

0FFFh

1000h

10BFh 10C0h

1EFFh

1F00h

1FFFh

2000h

3FFFh

4000h

FFFFh

01FFh

Interrupts and Reset Vectors;

Trap and PACT Vectors

7F9Bh 7F9Ch

7FFFh

8000h

7FF6h–7FF7h 7FF8h–7FFBh

Peripheral File Control Registers

0180h

017Fh

1010h–101Fh

1050h–105Fh

System Control

1030h–103Fh 1040h–104Fh

ADC1 Peripheral Control

Trap 15–0

Reserved

†

256-Byte PACT Standby RAM

Reserved

†

256-Byte Data EEPROM

Reserved

†

16K-Byte ROM/EPROM

Reserved

†

Reserved

†

7F9Ch–7FBFh

7FE0h–7FEBh

1000h–100Fh

1060h–106Fh 1070h–107Fh

Reserved

†

SPI Peripheral Control

PACT Peripheral Control

Reserved

†

Reserved

†

Reserved means that the address space is reserved for future expansion.

Figure 3. TMS370Cx36 Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx36 devices contain 256 bytes of internal RAM, memory-mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

dual-port RAM

The upper 128 bytes of the register files can be used by the P ACT module to contain commands and definitions as well as timer values. Any RAM not used by PACT can be used as an additional CPU register or as general-purpose memory.

TMS370Cx36

8-BIT MICROCONTROLLER

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standby RAM module

The 256 byte standby RAM is general-purpose and powered through a separate V

CCSTBY

pin. The data stored

in this memory is protected against power failures on the main V

CC1

pins.

The standby RAM data is saved if the power failure on the main V

CC1

pins is detected externally and an external

reset is generated when V

CC1

falls below 4.3 V (see Figure 4). The external reset must remain low during the entire power failures. The falling edge of the reset signal is internally detected to set the standby RAM in low-power HAL T mode. After the next power up, the RESET pin must be pulled high to get out of the HALT mode of the standby RAM. In halt mode, the standby RAM consumes only leakage current.

4.3 Volt

CC1

RESET

Standby RAM Locked in Halt Mode

Figure 4. Standby RAM Locked in Halt Mode

peripheral file (PF)

The TMS370Cx36 control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 lists the TMS370Cx36 PF address map.

Table 4. TMS370Cx36 Peripheral File Address Map

БББББ

ADDRESS RANGE

БББББББ

БББББ

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

DESCRIPTION

1000h–100Fh

БББББББ

P000–P00F Reserved

1010h–101Fh

БББББББ

P010–P01F

System and EPROM/EEPROM control registers

1020h–102Fh

БББББББ

P020–P02F

Digital I/O port control registers

1030h–103Fh

P030–P03F

SPI registers

1040h–104Fh

БББББББ

P040–P04F

PACT registers

1050h–106Fh

БББББББ

P050–P06F Reserved

1070h–107Fh

БББББББ

P070–P07F

Analog-to-digital converter 1 registers

1080h–10FFh

БББББББ

P080–P0FF

Reserved

TMS370Cx36 8-BIT MICROCONTROLLER

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data EEPROM

The TMS370Cx36 devices, containing 256 bytes of data EEPROM, have a memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B). The data EEPROM features include the following:

Programming: – Bit-, byte-, and block-write/erase modes. – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A. See Table 5.

– In-circuit programming capability. There is no need to remove the device to program.

Write protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write protection active. There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

T able 5. Data EEPROM and PROGRAM EPROM Control Registers Memory Map

ADDRESS

SYMBOL

NAME

P01A

DEECTL

Data EEPROM Control Register

P01B

— Reserved

P01C

EPCTLL

Program EPROM Control Register – Low Array

program EPROM

†

The TMS370C736 device contains 16K bytes of EPROM mapped, beginning at location 4000h and continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the EPROM control register (EPCTLL). The program EPROM module features include:

Programming – In-circuit programming capability if VPP is applied to MC – Control register: EPROM programming is controlled by the EPROM control register (EPCTLL) located

in the peripheral file (PF) frame at location P01C as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted – Low-power modes – 13 V not applied to MC

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. TI is a trademark of Texas Instruments Incorporated.

TMS370Cx36

8-BIT MICROCONTROLLER

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program ROM

†

The program ROM consists of 16K bytes of mask programmable read-only memory . The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx36 CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are generated internally , while one (RESET pin) is controlled externally. These actions are as follows:

P ACT watchdog (WD) timer . A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370

User’s Guide

(literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide

(literature number SPNU127) for more information.

Once a reset source is activated, the external RESET

pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x36 device to reset external system components. Additionally , if a cold start (V

is off for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FL T FLAG, SCCR0.4) and the cold-start flag (COLD ST ART, SCCR0.7) to determine the source of the reset. A reset does not clear these flags.Table 6 lists the reset sources. If none of the sources indicated in T able 6 caused the reset, then the RESET pin was pulled low by the external hardware or the PACT module’s watchdog.

Table 6. Reset Sources

ADDRESS

BIT NO.

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

COLD START

Cold (power-up)

SCCR0

1010h

P010

OSC FLT FLAG

Oscillator out of range

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh.

TMS370Cx36 8-BIT MICROCONTROLLER

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interrupts

The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 5. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the ST.

GROUP 2

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

PACT 3 PRI

Priority

Cmd/Def Entry 7 Cmd/Def Entry 6 Cmd/Def Entry 5 Cmd/Def Entry 4

Cmd/Def Entry 3 Cmd/Def Entry 2

AD INT

AD PRI

ADC1

STATUS REG

EXT INT1

INT1 PRI

INT1

SPI INT

SPI PRI

SPI

Cmd/Def Entry 1 Cmd/Def Entry 0

GROUP 3

PACT 1 PRI

Overflow CP1 Edge CP2 Edge CP3 Edge

CP4 Edge CP5 Edge CP6 Edge

Circular Buffer

GROUP 1

PACT 2 PRI

SCI TXINT SCI RXINT

PACT

Default Timer

Figure 5. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high- or low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

TMS370Cx36

8-BIT MICROCONTROLLER

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx36 has 21 hardware system interrupts (plus RESET

) as shown in T able 7. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt.

Twenty of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is supported. Software configuration of the external interrupts is performed through the INT1 control register in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individualor global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupt INT1 can be software configured as a general-purpose input pin if the interrupt function is not required.

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interrupts (continued)

T able 7. Hardware System Interrupts

ÁÁÁÁ

INTERRUPT

SOURCE

БББББББ

INTERRUPT

FLAG

ÁÁÁÁ

OSC FLT FLG

ÁÁÁ

SYSTEM

INTERRUPT

ÁÁÁÁ

VECTOR

ADDRESS

ÁÁ

MODULE

PRIORITY

†

ÁÁ

PRIORITY

GROUP

ÁÁÁÁ

RESET

БББББББ

External RESET Watchdog Overflow Oscillator Fault

ÁÁÁÁ

COLD START (No Flag) OSC FLT FLAG

ÁÁÁ

RESET

†

ÁÁÁÁ

7FFEh, 7FFFh

ÁÁ

INT1

External Interrupt 1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

SPI

SPI RX/TX Complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

ÁÁÁÁÁБББББББ

PACT Circular Buf fer

ÁÁÁÁ

Buffer Half/Full Interrupt Flag

ÁÁÁ

BUFINT

ÁÁÁÁ

7FB0h, 7FB1h

ÁÁÁÁÁ

PACT CP6 Event

CP6 INT FLAG

CP6INT

7FB2h, 7FB3h

PACT CP5 Event

CP5 INT FLAG

CP5INT

7FB4h, 7FB5h

PACT CP4 Event

CP4 INT FLAG

CP4INT

7FB6h, 7FB7h

PACT (Group 1)

PACT CP3 Event

CP3 INT FLAG

CP3INT

7FB8h, 7FB9h

PACT CP2 Event

CP2 INT FLAG

CP2INT

7FBAh, 7FBBh

PACT CP1 Event

CP1 INT FLAG

CP1INT

7FBCh, 7FBDh

ÁÁÁÁÁБББББББ

Default Timer Overflow

ÁÁÁÁ

DEFTIM OVRFL INT FLAG

ÁÁÁ

POVRL

INT

ÁÁÁÁ

7FBEh, 7FBFh

ÁÁÁÁÁ

PACT SCI Rx Int

PACT RX RDY

PRXINT

7F9Eh, 7F9Fh

PACT (Group 2)

PACT SCI Tx Int

PACT TX RDY

PTXINT

7F9Ch, 7F9Dh

PACT Cmd/Def Entry 0

CMD/DEF INT 0 FLAG

CDINT 0

7FA0h, 7FA1h

PACT Cmd/Def Entry 1

CMD/DEF INT 1 FLAG

CDINT 1

7FA2h, 7FA3h

PACT Cmd/Def Entry 2

CMD/DEF INT 2 FLAG

CDINT 2

7FA4h, 7FA5h

PACT Cmd/Def Entry 3

CMD/DEF INT 3 FLAG

CDINT 3

7FA6h, 7FA7h

PACT (Group 3)

PACT Cmd/Def Entry 4

CMD/DEF INT 4 FLAG

CDINT 4

7FA8h, 7FA9h

PACT Cmd/Def Entry 5

CMD/DEF INT 5 FLAG

CDINT 5

7FAAh, 7FABh

PACT Cmd/Def Entry 6

CMD/DEF INT 6 FLAG

CDINT 6

7FACh, 7FADh

PACT Cmd/Def Entry 7

CMD/DEF INT 7 FLAG

CDINT 7

7FAEh, 7FAFh

ADC1

ADC1 Conversion Complete

AD INT FLAG

ADINT

7FECh, 7FEDh

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes

privileged operation and EEPROM write protection override

The TMS370Cx36 family is designed with significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx36 operates in the privileged mode, where all peripheral file registers have unrestricted read / write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within the PF . Table 8 lists the control bits shown in the table which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write protection override (continued)

Table 8. Privilege Bits

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

SCCRO

ÁÁÁ

P010.5 P010.6

ББББББББ

PF AUTO WAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

ББББББББ

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

ÁÁÁ

SPIPRI

ÁÁÁ

P03F.5 P03F.6 P03F.7

ББББББББ

SPI ESPEN SPI PRIORITY SPI STEST

ÁÁÁ

PACTSCR

ÁÁÁ

P040.0 P040.1 P040.2 P040.3 P040.4

ББББББББ

PACT PRESCALE SELECT 0 PACT PRESCALE SELECT 1 PACT PRESCALE SELECT 2 PACT PRESCALE SELECT 3 FAST MODE SELECT

ÁÁÁ

PACTPRI

ÁÁÁ

P04F.0 P04F.1 P04F.2 P04F.3 P04F.4 P04F.5 P04F.7

ББББББББ

PACT WD PRESCALE SELECT 0 PACT WD PRESCALE SELECT 1 PACT MODE SELECT PACT GROUP 3 PRIORITY PACT GROUP 2 PRIORITY PACT GROUP 1 PRIORITY PACT STEST

ÁÁÁ

ADPRI

ÁÁÁ

P07F.5 P07F.6 P07F.7

ББББББББ

AD ESPEN AD PRIORITY AD STEST

†

The privilege bits are shown in a bold typeface and shaded areas in the system configuration registers section of Table 10.

low-power and IDLE modes

The TMS370Cx36 devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the ST ANDBY mode (HAL T/ST ANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, the PACT counter, and the first PACT command entry remain active in all modules. System processing is suspended until a qualified interrupt (hardware RESET

or external interrupt

on INT1) is detected. In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx36 is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET or external interrupt on the INT1) is detected. The power-down mode-selection bits are summarized in Table 9.

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