Texas Instruments TMS370C702FNT Datasheet

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 8K Bytes

– EPROM: 8K Bytes – Data EEPROM: 256 Bytes – Static RAM: 256 Bytes Usable as

Registers

Flexible Operating Features – Low-Power Modes: STANDBY and HAL T – Commercial, Industrial, and Automotive

T emperature Ranges – Clock Options

– Divide-by-4 (0.5 to 5 MHz SYSCLK)

– Divide-by-1 (2 to 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Supply Voltage (V

16-Bit General-Purpose Timer

) 5 V ±10%

– Software Configurable as

a 16-Bit Event Counter, or

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

Two Compare Registers, or a

Self-Contained Pulse-Width-Modulation

(PWM) Function – Software Programmable Input Polarity – Eight-Bit Prescaler, Providing a 24-Bit

Real-Time Timer

On-Chip 24-Bit Watchdog Timer – EPROM/OTP Devices: Standard

Watchdog – Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Flexible Interrupt Handling – Two Software-Programmable Interrupt

Levels – Global- and Individual-Interrupt Masking – Programmable Rising or Falling Edge

Detect – Individual Interrupt Vectors

FZ AND FN PACKAGES

(TOP VIEW)

VA7D7D6D3

3212827

426

A6 A5 A4 A3 A2

5 6 7 8 9 10 11

12 13

14 15 16 1718

XTAL2/CLKIN

XTAL1

Serial Communications Interface 1 (SCI1)

INT1

RESET

25 24 23 22 21 20 19

INT2

INT3

SCITXD SCICLK SCIRXD T1IC/CR T1PWM T1EVT MC

– Asynchronous Mode: 156K bps

Maximum at 5 MHz SYSCLK

– Isosynchronous Mode: 25M bps

Maximum at 5 MHz SYSCLK

– Full Duplex, Double-Buffered Receiver

(RX) and Transmitter (TX)

– Two Multiprocessor Communication

Formats

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/TTL Compatible I/O Pins/Packages – All Peripheral Function Pins Software

Configurable for Digital I/O – 21 Bidirectional Pins, 1 Input Pin – 28-Pin Plastic and Ceramic Leaded Chip

Carrier Packages

Workstation/Personal Computed-Based Development System – C Compiler and C Source Debugger – Real-time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Multi-Window User Interface – Microcontroller Programmer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS370Cx0x

†

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

28 PINS

LCC

NAME

A0 A1

ÁÁÁ

A3 A4

ÁÁÁ

A6 A7

ÁÁÁ

D3 D4 D5

ÁÁÁ

D7 INT1

INT2

ÁÁÁ

INT3 T1IC/CR

ÁÁÁ

T1PWM T1EVT

SCITXD

ÁÁÁ

SCIRXD SCICLK

ÁÁÁ

RESET MC

NO.

14 13

ÁÁ

28 26 15

ÁÁ

16 17

ÁÁ

18 22

ÁÁ

21 20

ÁÁ

23 24

ÁÁ

27 19

XTAL2/CLKIN XTAL1

ÁÁÁ

†

I = input, O = output

‡

The three-pin SCI configuration is referred to as SCI1.

ÁÁ

I/O

9 8 7 3

1 2

I/O

ББББББББББББББББББББББББ

Port A is a general-purpose bidirectional I/O port.

ББББББББББББББББББББББББ

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

ББББББББББББББББББББББББ

External interrupt (non-maskable or maskable)/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin

ББББББББББББББББББББББББ

External maskable interrupt input/general-purpose bidirectional pin Timer1 input capture/counter reset input pin /general-purpose bidirectional pin

I/O

ББББББББББББББББББББББББ

Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

SCI transmit data output pin, general-purpose bidirectional pin

I/O

5 6

ББББББББББББББББББББББББ

SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

ББББББББББББББББББББББББ

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET

indicates that an internal failure was detected by watchdog or oscillator fault circuit.

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM V

Internal oscillator crystal input/External clock source input

Internal oscillator output for crystal

ББББББББББББББББББББББББ

Positive supply voltage Ground reference

Pin Descriptions

DESCRIPTION

‡

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functional block diagram

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

INT1

INT2 INT3 XTAL1

Clock Options:

Interrupts

CPU

Program Memory

ROM: 8K Bytes

EPROM: 8K Bytes

Port A Port D

Divide-By-4 Or

Divide-By-1 (PLL)

XTAL2/

CLKIN

Data EEPROM 0 or 256 Bytes

System Control

RAM

256 Bytes

RESET

Serial

Communications

Interface 1

Timer 1

Watchdog

SCIRXD SCITXD SCICLK

T1IC/CR T1EVT T1PWM

description

The TMS370C002, TMS370C302, TMS370C702, and SE370C702 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx0x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations.

The TMS370Cx0x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx0x devices attractive in system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications.

All TMS370Cx0x devices contain the following on-chip peripheral modules:

Serial communications interface 1 (SCI1)

One 16-bit general-purpose timer with an 8-bit prescaler

One 24-bit general-purpose watchdog timer

Table 1 provides a memory configuration overview of the TMS370Cx0x devices.

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TMS370Cx0x

Divide-by-1 (PLL)

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

Table 1. Memory Configurations

БББББ

DEVICE

TMS370C002A TMS370C302A TMS370C702 SE370C702

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

†

PROGRAM MEMORY

ББББББББ

ROM

8K 8K

— —

(BYTES)

EPROM

—

— 8K 8K

DATA MEMORY

БББББББ

RAM

256 256 256 256

(BYTES)

EEPROM

256

— 256 256

БББББББББ

28-PIN PACKAGE

FN – PLCC FN – PLCC FN – PLCC FZ – CLCC

The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM without A Standard Divide-by-4 (standard oscillator) Enabled

ROM A

Standard

Hard

Simple

Divide-by-4 or

Enabled or disabled

The 8K bytes of mask-programmable ROM in the associated TMS370Cx0x devices are replaced in the TMS370C702 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the TMS370C302 devices. The one-time programmable (OTP) (TMS370C702) device and reprogrammable device (SE370C702) are available.

TMS370C702 OTP devices are available in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx0x family or for low-volume production runs when the mask charge or cycle time for low-cost mask ROM devices is not practical.

The SE370C702 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development-prototyping phase of design. The SE370C702 devices allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx0x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx0x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx0x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family.

The TMS370Cx0x devices have two operational modes of serial communications provided by the SCI1 module. The SCI1 allows standard RS-232-C communications with other common data transmission equipment.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

The TMS370Cx0x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx0x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through extensive menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx0x family together with the TMS370 family CDT370, design kit, starter kit, software tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU used on the TMS370Cx0x device is the high-performance 8-bit TMS370 CPU module. The ’x0x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x0x instruction map is shown in T able 15 in the TMS370Cx0x instruction set overview section.

The ’370Cx0x CPU architecture provides the following components: CPU registers:

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global interrupt enable bits

A program counter (PC) that points to the memory location of the next instruction to be executed

Figure 1 illustrates the CPU registers and memory blocks.

CDT is a trademark of Texas Instruments Incorporated.

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TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

RAM (Includes 256-Byte Registers File)

0000h

0001h 0002h 0003h

007Fh

Stack Pointer (SP)

Status Register (ST)

R0(A) R1(B)

R2 R3

R127

Program Counter

IE1IE2ZNC

015

01234567

Legend:

C=Carry N=Negative

Z=Zero

V=Overflow

IE2=Level 2 interrupts Enable IE1=Level 1 interrupts Enable

256-Byte RAM (0000h - 00FFh)

256-Byte Data EEPROM

8K-Byte ROM/EPROM (6000h–7FFFh)

Reserved

Peripheral File

Reserved

Not Available

†

0000h 00FFh 0100h 100Fh

1010h 105Fh

1060h

1EFFh 1F00h

‡

1FFFh 2000h 5FFFh 6000h

00FFh

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

R255

Interrupts and Reset Vectors;

Trap Vectors

Figure 1. Programmer’s Model

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions, general-purpose register, or the stack

A peripheral file that provides access to all internal peripheral modules, system-wide control functions and EEPROM/EPROM programming control

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off conditions

8K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used typically to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM memory.

7FBFh 7FC0h

7FFFh

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TMS370Cx0x

8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST register includes four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional jump instructions) use the status bits to determine program flow.

The two interrupt enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers (ST)

RW-0

R = read, W = write, 0 = value after reset

RW-0

5 Z

RW-0

4 V

RW-0

IE2

RW-0

IE1 Reserved Reserved

RW-0

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most significant byte and least significant byte of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector.

Program Counter (PC)

0000h

7FFEh 7FFFh

Memory

60 00

PCH PCL

60 00

Figure 2. Program Counter After Reset

memory map

The TMS370Cx0x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx0x provides memory-mapped RAM, ROM, Data EEPROM, input/output pins, peripheral functions, and system interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file is located between 1010h to 105Fh and is divided logically into five peripheral-file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed.

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TMS370Cx0x 8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

0000h

00FFh

0100h

100Fh 1010h

105Fh

1060h

1EFFh

1F00h

1FFFh

2000h

5FFFh

6000h

6FFFh

7000h

77FFh

7800h

7FBFh 7FC0h

7FFFh

8000h

FFFFh

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

256-Byte RAM

(Register File/Stack)

Reserved

Peripheral File

Reserved

256-Byte Data EEPROM

Not Available

8K-Byte ROM/EPROM

(6000h–7FFFh)

Interrupts and Reset Vectors;

Trap Vectors

Not Available

†

‡

Peripheral File Control Registers

System Control

Digital Port Control

Reserved

Timer 1 Peripheral Control

SCI1 Peripheral Control 1050h–105Fh

Vectors

Trap 15–0

Reserved

Serial Communications Interface TX 7FF0h–7FF1h

Serial Communications Interface RX

Timer 1 7FF4h–7FF5h Reserved Interrupt 3 7FF8h–7FF9h Interrupt 2 7FFAh–7FFBh Interrupt 1 7FFCh–7FFDh

†

Reset 7FFEh–7FFFh

1010h–101Fh 1020h–102Fh 1030h–103Fh 1040h–104Fh

7FC0h–7FDFh 7FE0h–7FEFh

7FF2h–7FF3h

7FF6h–7FF7h

Figure 3. TMS370Cx0x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx0x devices contain 256 bytes of internal memory-mapped RAM beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx0x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 shows the TMS370Cx0x PF address map.

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БББББББ

peripheral file (PF) (continued)

Table 4. TMS370Cx0x Peripheral File Address Map

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

ADDRESS RANGE

БББББ

1000h–100Fh 1010h–101Fh 1020h–102Fh 1030h–103Fh 1040h–104Fh 1050h–105Fh 1060h–10FFh

PERIPHERAL FILE

DESIGNAT OR

БББББ

БББББББББББББББББББ

P000–P00F Reserved P010–P01F P020–P02F P030–P03F P040–P04F

System and EPROM/EEPROM control registers Digital I/O port control registers Reserved

Timer 1 registers P050–P05F Serial communications interface registers P060–P0FF

Reserved

DESCRIPTION

data EEPROM

The TMS370Cx0x devices, containing 256 bytes of data EEPROM, have their memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

Family Data Manual

Programming:

(literature number SPNS014B). The data EEPROM features include the following:

– Bit-, byte-, and block-write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A. See Table 5.

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370

– In-circuit programming capability. There is no need to remove the device to program.

Write protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write protection active. There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

P01A P01B P01C

SYMBOL

DEECTL

Data EEPROM control register

— Reserved

EPCTL

Program EPROM control register

NAME

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SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

program EPROM

The TMS370C702 device contains 8K bytes of EPROM, mapped, at location 6000h and continuing through location 7FFFh as shown in Figure 3. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include:

Programming – In-circuit programming capability if VPP is applied to MC – Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset halts all programming to the EPROM module. – Low-power modes – 13 V not applied to MC

program ROM

The program read-only memory (ROM) consists of 8K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system reset operation ensures an orderly start-up sequence for the TMS370Cx0x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET pin) is controlled externally. These actions are as follows:

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer times out . See the

Family User’s Guide

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the

TMS370 Family User’s Guide

Once a reset source is activated, the external RESET cycles. This allows the ’x0x device to reset external system components. Additionally , if a cold start (V for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.

(literature number SPNU127) for more information.

pin is driven (active) low for a minimum of eight SYSCLK

TMS370

is off

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD ST ART , SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

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system reset (continued)

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 6. Reset Sources

SCCR0 SCCR0

T1CTL2

ADDRESS

1010h 1010h

104Ah

P010 P010 P04A

BIT NO.

7 4 5

CONTROL BIT

COLD START

OSC FLT FLAG

WD OVRFL INT FLAG

SOURCE OF RESET

Cold (power-up)

Oscillator out of range

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.

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interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of the status register.

EXT INT 3

INT 3

EXT INT 2

INT 2

SCI INT

TX TXRDY

TXPRI

TIMER1

Overflow

Compare1

Ext Edge

Compare2 Input Capture Watchdog

RXPRI

BRKDT

T1 PRI

INT3 PRI

INT1

EXT INT1

INT1 PRI

INT2 PRI

STATUS REG

IE1

IE2

Enable

CPU

NMI

Priority

Logic

Level 1 INT Level 2 INT

RXRDY

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx0x has six hardware system interrupts (plus RESET

) as shown in T able 7. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt.

Three of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- or global-enable-mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin).

Table 7. Hardware System Interrupts

INTERRUPT SOURCE

External RESET Watchdog Overflow

БББББББББ

Oscillator Fault Detect External INT1 External INT2 External INT3 Timer 1 Overflow

Timer 1 Compare 1

БББББББББ

Timer 1 Compare 2

БББББББББ

Timer 1 External Edge Timer 1 Input Capture 1

БББББББББ

Watchdog Overflow SCI RX Data Register Full

SCI RX Break Detect

БББББББББ

SCI TX Data Register Empty

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes.

Release microcontroller from STANDBY low-power mode.

INTERRUPT FLAG

COLD START WD OVRFL INT FLAG

БББББББ

OSC FLT FLAG INT1 FLAG INT2 FLAG INT3 FLAG T1 OVRFL INT FLAG

T1C1 INT FLAG

БББББББ

T1C2 INT FLAG

БББББББ

T1EDGE INT FLAG T1IC1 INT FLAG

БББББББ

WD OVRFL INT FLAG RXRDY FLAG

BRKDT FLAG

БББББББ

TXRDY FLAG

SYSTEM

INTERRUPT

‡

RESET

ÁÁÁÁ

‡

INT1

‡

INT2

‡

INT3

ÁÁÁÁ

T1INT

RXINT

‡

TXINT

VECTOR

ADDRESS

7FFEh, 7FFFh

БББББ

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

БББББ

7FF4h, 7FF5h

БББББ

7FF2h, 7FF3h

БББББ

7FF0h, 7FF1h

PRIORITY

ÁÁ

2 3 4

ÁÁ

†

privileged operation and EEPROM write protection override

The TMS370Cx0x family has significant flexibility to enable the designer to software configure the system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx0x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the

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privileged operation and EEPROM WPO (continued)

nonprivileged mode, thus disabling write operations to specific configuration control bits within the peripheral file. T able 8 lists the system configuration bits which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

Table 8. Privileged Bits

NAME

SCCR0

SCCR1

ÁÁÁ

SCCR2

ÁÁÁ

SCIPRI

ÁÁÁ

T1PRI

†

The privileged bits are shown in a bold typeface in Table 10.

†

LOCATION

P010.5 P010.6

P011.2

ÁÁÁ

P011.4 P012.0

P012.1

ÁÁÁ

P012.3

ÁÁÁ

P012.4 P012.6

ÁÁÁ

P012.7 P05F.4

P05F.5

ÁÁÁ

P05F.6

ÁÁÁ

P05F.7 P04F.6

P04F.7

PF AUTO WAIT OSC POWER

MEMORY DISABLE

БББББББ

AUTOWAIT DISABLE PRIVILEGE DISABLE

INT1 NMI

БББББББ

CPU STEST

БББББББ

BUS STEST PWRDWN/IDLE

БББББББ

HALT/STANDBY SCI ESPEN

SCIRX PRIORITY

БББББББ

SCITX PRIORITY

БББББББ

SCI STEST T1 PRIORITY

T1 STEST

The write protect override (WPO) mode is an external hardware method of overriding the write protection registers (WPR) of data EEPROM on the TMS370Cx0x. WPO mode is entered by applying a 12-V input to the MC pin after the RESET pin input goes high (logic 1). The high voltage (+ 12 V) on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the content of data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx0x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops; however, the oscillator, internal clocks, timer 1 and the receive-start bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET detected.

, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is

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low-power and IDLE modes (continued)

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx0x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET on the receive pin of the SCI1) is detected. The power-down mode selection bits are summarized in Table 9.

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

1 1 0

†

Don’t care

HALT/STANDBY

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6-7 bits are ignored. In addition, if an idle instruction executes when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

, external interrupt on the INT1, INT2, INT3, or low level

MODE SELECTED

(SCCR2.7)

0 1

†

STANDBY HALT IDLE

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing stops during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ’x0x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ’x0x ROM-masked devices of fer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’702A EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency , whereas the divide-by-4 option produces a SYSCLK which is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

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clock modules (continued)

These are formulated as follows:

Divide-by-4 : SYSCLK

Divide-by-1 : SYSCLK

external resonator frequency

external resonator frequency 4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a steeper decay of emissions produced by the oscillator.

system configuration registers

Table 10 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface and shaded areas.

Table 10. Peripheral File Frame 1: System Configuration Registers

BIT 7

P010

ÁÁ

P011

ÁÁ

P012

COLD

START

ÁÁ

—

ÁÁ

HALT/

STANDBY

P013

ÁÁ

P016 P017

ÁÁ

P018

ÁÁ

P019

P01A

INT1

ÁÁ

FLAG

INT2

FLAG

ÁÁ

INT3

FLAG

BUSY P01B Reserved P01C

BUSY P01D

P01E

ÁÁ

P01F

BIT 6

OSC

POWER

—

ÁÁ

PWRDWN/

IDLE

INT1

ÁÁ

PIN DATA

INT2

PIN DATA

ÁÁ

INT3

PIN DATA

—

VPPS

BIT 5

PF AUTO

WAIT

—

ÁÁÁ

—

ÁÁÁ

—

ÁÁÁ

— —

—

BIT 4

OSC FLT

FLAG

ÁÁ

AUTO

WAIT

DISABLE

BUS

STEST

—

ÁÁ

INT2

DATA DIR

ÁÁ

INT3

DATA DIR

—

MC PIN

ÁÁÁ

STEST

Reserved

ÁÁÁ

DATA OUT

ÁÁÁ

DATA OUT

Reserved

BIT 3

WPO

—

CPU

—

INT2

INT3

—

BIT 2

MC PIN

DATA

ÁÁ

MEMORY DISABLE

—

INT1

ÁÁ

POLARITY

INT2

POLARITY

ÁÁ

INT3

POLARITY

—

BIT 1

—

ÁÁ

—

ÁÁ

INT1

NMI

INT1

ÁÁ

PRIORITY

INT2

PRIORITY

ÁÁ

INT3

PRIORITY

W1W0

BIT 0

µP/µC

MODE

ÁÁÁ

—

ÁÁÁ

PRIVILEGE

DISABLE

INT1

ÁÁÁ

ENABLE

INT2

ENABLE

ÁÁÁ

INT3

ENABLE

EXE

REG

SCCR0

ÁÁ

SCCR1

ÁÁ

SCCR2

ÁÁ

INT1

ÁÁ

INT2

ÁÁ

INT3 DEECTL

EPCTL

ÁÁ

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. T able 11 shows the specific addresses, registers, and control bits within this peripheral file frame.

Table 11. Peripheral File Frame 2: Digital Port Control Registers

P020 Reserved P021 P022 P023

BIT 7

BIT 6

BIT 5

BIT 4

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

BIT 3

BIT 2

BIT 1

BIT 0

REG

APORT1 APORT2 ADATA ADIR

P024

P02B P02C P02D P02E

P02F

Port D Control Register 1 (must be 0)

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Reserved

†

— — — —

DPORT1 DPORT2 DDATA DDIR

Table 12. Port Configuration Register Setup

БББББББ

PORT

A D

БББББББ

0 – 7 3 – 7

БББББББ

abcd

00q1 Data OUT q Data OUT q

БББББББ

a = Port x Control Register 1

БББББББББББББББББББББББББББББББ

b = Port x Control Register 2

c = Data

d = Direction

abcd

00y0 Data In y Data In y

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programmable timer 1

The programmable Timer 1 (T1) module of the TMS370Cx0x provides the designer with the enhanced timer resources required to perform real-time system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The timer 1 module includes three external device pins that can be used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. The T1 module block diagram is shown in Figure 5.

T1EVT

T1IC/CR

8-Bit

Prescaler

MUX

Edge

Select

16-Bit

Counter

Watchdog Counter

16-Bit

Capt/Comp

16-Bit

Compare

16-Bit

(Aux. Timer)

PWM

Toggle

Interrupt

Logic

Interrupt

Logic

Figure 5. Timer 1 Block Diagram

Three T1 I/O pins – T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin

T1PWM

– T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin – T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin

Two operation modes: – Dual-compare mode: Provides PWM signal – Capture/compare mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a capture or compare register.

One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer if watchdog feature is not needed.

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

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programmable timer 1 (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC1/CR)

Interrupts that can be generated on the occurrence of: – A capture – A compare equal – A counter overflow – An external edge detection

Sixteen timer 1 module control registers located in the PF frame beginning at address P040.

The T1 module control registers are illustrated in Table 13.

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programmable timer 1 (continued)

Table 13. Timer 1 Module Register Memory Map

BIT 7

Modes: Dual-Compare and Capture/Compare

P040

Bit 15 T1Counter MSbyte Bit 8

P041

Bit 7 T1 Counter LSbyte Bit 0

P042

Bit 15 Compare Register MSbyte Bit 8

P043

Bit 7 Compare Register LSbyte Bit 0

P044

Bit 15 Capture/Compare Register MSbyte Bit 8

P045

Bit 7 Capture/Compare Register LSbyte Bit 0

P046

Bit 15 Watchdog Counter MSbyte Bit 8

P047

Bit 7 Watchdog Counter LSbyte Bit 0

P048

Bit 7 Watchdog Reset Key Bit 0

WD OVRFL

P049

P04A

ÁÁÁ

TAP SEL

WD OVRFL

RST ENA

Mode: Dual-Compare

P04B

P04C

T1EDGE

ÁÁÁ

INT FLAG

MODE=0

Mode: Capture/Compare

P04B

P04C

T1EDGE

ÁÁÁ

INT FLAG

MODE = 1

Modes: Dual-Compare and Capture/Compare

P04D

P04E

P04F T1 STEST

—

ÁÁÁ

T1PWM

DATA IN

ÁÁÁ

†

SELECT2

WD OVRFL

†

BIT 6

WD INPUT

ÁÁ

INT ENA

T1C2

ÁÁ

INT FLAG

T1C1

OUT ENA

—

ÁÁ

T1C1

OUT ENA

—

ÁÁ

T1PWM

DATA OUT

ÁÁ

PRIORITY

WD INPUT

†

ÁÁÁ

SELECT1

WD OVRFL

INT FLAG

ÁÁÁ

INT FLAG

OUT ENA

ÁÁÁ

INT FLAG

ÁÁÁ

FUNCTION

ÁÁÁ

BIT 5

T1C1

T1C2

T1C1

—

T1PWM

—

†

BIT 4

WD INPUT

ÁÁ

SELECT0

T1 OVRFL

INT ENA

—

ÁÁ

T1C1

RST ENA

—

ÁÁ

T1C1

RST ENA

—

ÁÁ

T1PWM

DATA DIR

ÁÁ

—

ÁÁ

†

BIT 3

—

ÁÁ

T1 OVRFL

INT FLAG

—

ÁÁ

T1CR

OUT ENA

—

ÁÁ

—

T1EVT

ÁÁ

DATA IN

T1IC/CR

DATA IN

ÁÁ

—

ÁÁ

BIT 2

T1 INPUT

ÁÁÁ

SELECT2

—

T1EDGE

ÁÁÁ

INT ENA

T1EDGE

POLARITY

T1EDGE

ÁÁÁ

INT ENA

T1EDGE

POLARITY

T1EVT

ÁÁÁ

DATA OUT

T1IC/CR

DATA OUT

ÁÁÁ

—

ÁÁÁ

BIT 1

T1 INPUT

ÁÁ

SELECT1

—

T1C2

ÁÁ

INT ENA

T1CR

RST ENA

—

ÁÁ

—

T1EVT

ÁÁ

FUNCTION

T1IC/CR

FUNCTION

ÁÁ

—

ÁÁ

BIT 0

T1 INPUT

ÁÁÁ

SELECT0

SW RESET

T1C1

ÁÁÁ

INT ENA T1EDGE

DET ENA

T1C1

ÁÁÁ

INT ENA T1EDGE

DET ENA

T1EVT

ÁÁÁ

DATA DIR

T1IC/CR

DATA DIR

ÁÁÁ

—

ÁÁÁ

REG

T1CNTR

T1C

T1CC

WDCNTR

WDRST T1CTL1

ÁÁ

T1CTL2

T1CTL3

ÁÁ

T1CTL4

T1CTL3

ÁÁ

T1CTL4

T1PC1

ÁÁ

T1PC2

ÁÁ

T1PRI

ÁÁ

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.

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programmable timer 1 (continued)

Figure 6 shows the timer 1 capture/compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CC.15-0

T1CNTR.15-0

T1 SW

RESET

T1CTL2.0

LSB

MSB

Prescale

Clock

Source

16-Bit

Counter

Reset

T1C1

RST ENA

T1C.15-0

16-Bit

Capt/Comp

Compare=

16-Bit

Compare

LSB MSB

LSB

MSB

T1C1 INT FLAG

T1CTL3.5

T1CTL3.0

T1C1 INT ENA

T1C1

OUT ENA

T1CTL4.6

T1PC2.7-4

T1PWM

Toggle

T1 PRIORITY

T1PRI.6

Level 1 Int

Level 2 Int

T1CTL4.4

T1PC2.3-0

T1IC/CR

T1EDGE DET ENA

Edge

Select

T1CTL4.0

T1CTL4.2

T1EDGE POLARITY

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.7

T1CTL3.2

T1EDGE INT ENA

Figure 6. Capture/Compare Mode

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programmable timer 1 (continued)

Figure 7 shows the timer 1 dual-compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CC.15-0

T1 SW

RESET

T1CTL2.0

Prescaler

Clock

Source

LSB MSB

T1CNTR.15-0

16-Bit

Counter

Reset

T1C1

RST ENA

T1CTL4.4

Capt/Comp

Compare=

T1C.15-0

16-Bit

Compare

16-Bit

LSB MSB

LSB

MSB

T1C2 INT FLAG

T1CTL3.6

T1CTL3.1

T1C2 INT ENA

T1C1 INT FLAG

T1CTL3.5

T1CTL3.0

T1C1 INT ENA

Output Enable

T1CTL4.5

T1C2 OUT ENA

T1CTL4.6

Toggle

T1C1 OUT ENA

T1CTL4.3

T1CR OUT ENA

T1PC2.7-4

T1PWM

T1PC2.3-0

T1IC/CR

T1CTL4.1

T1CR

RST ENA

Edge

Select

T1EDGE POLARITY

T1CTL4.0

T1EDGE DET ENA

T1CTL4.2

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.7

T1CTL3.2

T1EDGE INT ENA

Figure 7. Dual-Compare Mode

T1 PRIORITY

T1PRI.6

Level 1 Int

Level 2 Int

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programmable timer 1 (continued)

The TMS370Cx0x device includes a 24-bit watchdog (WD) timer, contained in the timer 1 module, which can be programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not used. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be configured as one of three mask options as follows:

Standard watchdog configuration (see Figure 8) – for EPROM and mask-ROM devices: – Watchdog mode

– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

– Non-watchdog mode

Clock

Prescaler

– Watchdog timer can be configured as an event counter, a pulse accumulator, or an interval timer

WDCNTR.15-0

WD OVRFL

16-Bit

WatchdogCounter

Reset

Watchdog Reset Key

WDRST.7-0

INT FLAG

T1CTL2.5

T1CTL1.7

WD OVRFL

TAP SEL

T1CTL2.6

Interrupt

WD OVRFL

INT ENA

T1CTL2.7

System Reset

WD OVRFL

RST ENA

Figure 8. Standard watchdog

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programmable timer 1 (continued)

Hard watchdog configuration (see Figure 9) – for mask-ROM devices: – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows. – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as a nonmaskable interrupt during low-power modes. – A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

WDCNTR.15-0

Watchdog Counter

16-Bit

WD OVRFL

INT FLAG

T1CTL2.5

Reset

Clock

Prescaler

Watchdog Reset Key

WDRST.7-0

T1CTL1.7

WD OVRFL

TAP SEL

Figure 9. Hard Watchdog

Simple counter configuration – for mask-ROM devices only (see Figure 10) – Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

System Reset

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

WDCNTR.15-0

16-Bit

Watchdog Counter

Reset

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

WD OVFL INT FLAG

T1CTL2.5

T1CTL2.6

WD OVRFL

INT ENA

Interrupt

Clock

Prescaler

Watchdog Reset Key

WDRST.7-0

T1CTL1.7

WD OVRFL

TAP SEL

Figure 10. Simple Counter

serial communications interface 1 (SCI1) module

The TMS370Cx0x devices include a serial communications interface 1 (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals and uses the standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full duplex mode. T o ensure data integrity , the SCI1 checks received data for break detection, parity, overrun, and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a 16-bit baud-select register.

Features of the SCI1 module include:

Three external pins: – SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin – SCIRXD: SCI receive-input pin or general-purpose bidirectional I/O pin – SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin

Two communications modes: asynchronous and isosynchronous

Baud rate: 64K different programmable rates – Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK

ASYNCHRONOUS BAUD

– Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK

ISOSYNCHRONOUS BAUD

†

Isosynchronous = Isochronous

(BAUD REG)1) 32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SYSCLK

(BAUD REG)1) 2

†

TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

Data word format: – One start bit – Data word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: Idle-line and address bit

Half or full-duplex operation

Double-buffered receiver and transmitter operations

Transmitter and receiver operations can be accomplished through either interrupt-driven or polled-algorithms with status flags:

– Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (Transmitter shift register is empty) – Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions – Separate enable bits for transmitter and receiver interrupts – NRZ (non return-to-zero) format

Eleven SCI1 module control registers, located in control register frame beginning at address P050h

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

The SCI1 module control registers are illustrated in Table 14.

Table 14. SCI1 Module Control Register Memory Map

BIT 7

P050

STOP BITS

P051

P052

P053

P054

P055

ÁÁ

—

ÁÁ

BAUDF

(MSB)

BAUD7

ÁÁ

TXRDY

ÁÁ

ERROR

P056

P057

RXDT7

P058 P059

P05A

P05B P05C

P05D

P05E

TXDT7

ББББББББББББББББББББББББББ

—

SCITXD

DATA IN

ÁÁ

P05F SCI STEST

BIT 6

EVEN/ODD

ÁÁÁ

PARITY

—

ÁÁÁ

BAUDE

BAUD6

ÁÁÁ

TX EMPTY

RXRDY

ÁÁÁ

RXDT6

TXDT6

—

SCITXD

DATA OUT

ÁÁÁ

SCITX

PRIORITY

BIT 5

PARITY

ÁÁ

ENABLE

SCI SW

RESET

ÁÁ

BAUDD

BAUD5

ÁÁ

—

BRKDT

ÁÁ

RXDT5

TXDT5

—

SCITXD

FUNCTION

ÁÁ

SCIRX

PRIORITY

BIT 4

ASYNC/

ÁÁ

ISOSYNC

CLOCK

ÁÁ

BAUDC

BAUD4

ÁÁ

—

ÁÁ

Reserved

RXDT4

Reserved

TXDT4

Reserved

—

SCITXD

DATA DIR

ÁÁ

SCI

ESPEN

BIT 3

ADDRESS/

ÁÁÁ

IDLE WUP

TXWAKE

ÁÁÁ

BAUDB

BAUD3

ÁÁÁ

—

ÁÁÁ

RXDT3

TXDT3

SCICLK

DATA IN SCIRXD

DATA IN

ÁÁÁ

—

BIT 2

SCI

ÁÁ

CHAR2

SLEEP

ÁÁ

BAUDA

BAUD2

ÁÁ

RXDT2

TXDT2

SCICLK

DATA OUT

SCIRXD

DATA OUT

ÁÁ

TMS370Cx0x

8-BIT MICROCONTROLLER

BIT 1

SCI CHAR1

ÁÁ

TXENA

ÁÁ

BAUD9

BAUD1

ÁÁ

—

RXWAKE

ÁÁ

RXDT1

TXDT1

SCICLK

FUNCTION

SCIRXD

FUNCTION

ÁÁ

—

BIT 0

SCI CHAR0

ÁÁÁ

RXENA

ÁÁÁ

BAUD8 BAUD0

(LSB)

ÁÁÁ

SCI TX

INT ENA

SCI RX

ÁÁÁ

INT ENA

RXDT0

TXDT0

SCICLK

DATA DIR

SCIRXD

DATA DIR

ÁÁÁ

—

REG

SCICCR

ÁÁ

SCICTL

ÁÁ

BAUD MSB

BAUD LSB

ÁÁ

TXCTL

RXCTL

ÁÁ

RXBUF

TXBUF

ÁÁ

SCIPC1

SCIPC2

ÁÁ

SCIPRI

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

The SCI1 module block diagram is illustrated in Figure 11.

Frame Format and Mode

PARITY

EVEN/ODD ENABLE

SCICCR.6 SCICCR.5

BAUD MSB. 7–0

Baud Rate

SYSCLK

RXCTL.7

ERR

MSbyte Reg.

BAUD LSB. 7–0

Baud Rate

LSbyte Reg.

RXWAKE

RXCTL.1

RX ERROR

RXCTL.4–2

FE OE PE

TXWAKE

SCICTL.3

WUT

SCICTL.4

TXBUF.7– 0

Transmit Data

Buffer Reg.

TXSHF Reg.

CLOCK

RXSHF Reg.

SCICTL.0

RXENA

Receive Data

Buffer Reg.

SCI TX Interrupt

TXRDY

TXCTL.7

TX EMPTY

TXCTL.6

TXENA

SCITXD

SCICTL.1

SCIRXD

SCI RX Interrupt

RXRDY

RXCTL.6

BRKDT

RXCTL.5

SCI TX INT ENA

TXCTL.0

SCI RX INT ENA

RXCTL.0

SCITX PRIORITY

SCIPRI.6

SCIPC2.7–4

SCIPC1.3–0

SCIPC2.3–0

SCIRX PRIORITY

SCIPRI.5

Level 1 INT

Level 2 INT

SCITXD

SCICLK

SCIRXD

Level 1 INT

Level 2 INT

RXBUF.7 –0

Figure 11. SCI1 Block Diagram

instruction set overview

Table 15 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx0x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instructions for these two opcode nibbles contain the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 29

Table 15. TMS370 Family Opcode/Instruction Map

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

JMP

#ra

2/7 JN

2/5 JZ

2/5 JC

2/5 JP

2/5

JPZ

L S

2/5

BTJO

JNZ

†

Rs,A,ra

2/5

BTJZ

JNC

Rs.,A,ra

2/5 JV

2/5

JL ra

2/5

JLE

2/5

JHS

2/5

All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ

MOV Rs,A

2/7

AND Rs,A

2/7

Rs,A

2/7

XOR Rs,A

2/7

3/9

ADD Rs,A

2/7

ADC Rs,A

2/7

SUB Rs,A

2/7

SBB Rs,A

2/7

MOV A,Pd

2/8

MOV #n,A

2/6

AND #n,A

2/6 OR

#n,A

2/6

XOR #n,A

2/6

BTJO

#n,A,ra

3/8

BTJZ

#n,A,ra

3/8

ADD #n,A

2/6

ADC #n,A

2/6

SUB #n,A

2/6

SBB

#n,A

2/6

MOV Rs,B

2/7

AND Rs,B

2/7

Rs,B

2/7

XOR Rs,B

2/7

BTJO

Rs,B,ra

3/9

BTJZ

Rs,B,ra

3/9

ADD Rs,B

2/7

ADC Rs,B

2/7

SUB Rs,B

2/7

SBB Rs,B

2/7

MOV

Rs,Rd

3/9

AND

Rs,Rd

3/9

Rs,Rd

3/9

XOR

Rs,Rd

3/9

BTJO

Rs,Rd,ra

4/11

BTJZ

Rs,Rd,ra

4/11

ADD

Rs,Rd

3/9

ADC

Rs,Rd

3/9

SUB

Rs,Rd

3/9

SBB

Rs,Rd

3/9

MOV B,Pd

2/8

MOV

#n,B

2/6

AND

#n,B

2/6 OR

#n,B

2/6

XOR

#n,B

2/6

BTJO

#n,B,ra

3/8

BTJZ

#n,B,ra

3/8

ADD

#n,B

2/6

ADC

#n,B

2/6

SUB

#n,B

2/6

SBB #n,B

2/6

B,A,ra

MOV

B,A 1/8

AND

B,A 1/8

OR B,A 1/8

XOR

B,A 1/8

BTJO

2/10

BTJZ

2/10

ADD

B,A 1/8

ADC

B,A 1/8

SUB

B,A 1/8

SBB

B,A 1/8

INCW

#ra,Rd

3/11

MOV

Rs,Pd

3/10

MOV

#n,Rd

3/8

AND

#n,Rd

3/8

#n,Rd

3/8

XOR

#n,Rd

3/8

BTJO

#n,Rd,ra

4/10

BTJZ

#n,Rd,ra

4/10

ADD

#n,Rd

3/8

ADC

#n,Rd

3/8

SUB

#n,Rd

3/8

SBB

#n,Rd

3/8

MOV

Ps,A

2/8

AND A,Pd

2/9

A,Pd

2/9

XOR A,Pd

2/9

BTJO

A,Pd,ra

3/11

BTJZ

A,Pd,ra

3/10

MOVW #16,Rd

4/13

JMPL

lab 3/9

MOV

& lab,A

3/10

MOV

A, & lab

3/10

MOV

Ps,B

2/7

AND B,Pd

2/9 OR

B,Pd

2/9

XOR B,Pd

2/9

BTJO

B,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

MOVW

Rs,Rd

3/12

JMPL

*Rp

2/8

MOV

*Rp,A

2/9

MOV

A, *Rp

2/9

MOV

Ps,Rd

3/10

AND

#n,Pd

3/10

#n,Pd

3/10

XOR

#n,Pd

3/10

BTJO

#n,Pd,ra

4/11

BTJZ

#n,Pd,ra

4/11

MOVW

#16[B],Rpd

4/15

JMPL

*lab[B]

3/11

MOV

*lab[B],A

3/12

MOV

A,*lab[B]

3/12

†

CLRC /

TST A

1/9

DEC

1/8

INC

1/8

INV

1/8

CLR

1/8

XCHB

1/10

SWAP

1/11

PUSH

1/9

POP

1/9

DJNZ

A,#ra

2/10

COMPL

1/8

MOV

A,B

1/9

DEC

1/8

INC

1/8

INV

1/8

CLR

1/8

XCHB A /

TST B

1/10

SWAP

1/11

PUSH

1/9

POP

1/9

DJNZ B,#ra

2/10

COMPL

1/8

MOV A,Rd

2/7

MOV B,Rd

2/7

DEC

Rd 2/6

INC

Rd 2/6

INV

Rd 2/6

CLR

Rn 2/6

XCHB

Rn 2/8

SWAP

Rn 2/9

PUSH

Rd 2/7

POP

Rd 2/7

DJNZ

Rd,#ra

3/8

COMPL

Rd 2/6

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

LDST

2/6

MOV

#ra[SP],A

2/7

MOV

A,*ra[SP]

2/7

CMP

*n[SP],A

2/8

extend

inst,2

opcodes

IDLE

1/6

MOV

#n,Pd

3/10

SETC

1/7

RTS

1/9 RTI

1/12

PUSH

ST 1/8

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

8-BIT MICROCONTROLLER

instructions have a relative address as the last operand.

TMS370Cx0x

T l

R l

7 11

Ps=Peri heral register containing source byte

Rn Register file

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

Table 15. TMS370 Family Opcode/Instruction Map† (Continued)

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

JNV

MPY

Rs,A

2/5

2/46

JGE

Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix # = immediate operand #16 = immediate 16-bit number lab = 16-label n = immediate 8-bit number Pd = Peripheral register containing destination type Pn = Peripheral register

ra = Relative address Rd = Register containing destination type Rn = Re Rp = Register pair Rpd= Destination register pair Rps = Source Register pair Rs = Register containing source byte

†

CMP

Rs,A

2/5

2/7

DAC

Rs,A

2/5

2/9

JLO

DSB

Rs,A

2/5

2/9

ister file

All conditional jumps (opcodes 01–0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ

#n,A 2/45

CMP #n,A

2/6

DAC #n,A

2/8

DSB #n,A

2/8

MPY Rs,B

2/46

CMP Rs,B

DAC Rs,B

DSB Rs,B

2/7

2/9

MPY

Rs,Rd

3/48 CMP

Rs,Rd

3/9

DAC

Rs,Rd

3/11

DSB

Rs,Rd

3/11

MPY #n,B 2/45

CMP

#n,B

2/6

DAC #n,B

2/8

DSB #n,B

2/8

MPY

B,A

1/47

CMP

B,A

1/8

DAC

B,A

1/10 DSB

B,A

1/10

MPY

#n,Rs

3/47

CMP

#n,Rd

3/8

DAC

#n,Rd

3/10 DSB

#n,Rd

3/10

BR lab 3/9

CMP

& lab,A

3/11

CALL

lab

3/13

CALLR

lab

3/15

*Rp

2/8

CMP

*Rp,A

2/10

CALL

*Rp

2/12

CALLR

*Rp

2/14

Second byte of two-byte instructions (F4xx): F4 8

*lab[B]

3/11

CMP

*lab[B],A

3/13

CALL

*lab[B]

3/15

CALLR

*lab[B]

3/17

1/8

RRC

1/8 RL

1/8

RLC

1/8

RRC

1/8 RL

1/8

RLC

1/8

F4 9

F4 A

F4 B

F4 C

F4 D

F4 E

F4 F

RR Rd 2/6

RRC

Rd 2/6

RL Rd 2/6

RLC

Rd 2/6

TRAP

1/14

TRAP

1/14

TRAP

1/14

TRAP

1/14

MOVW

*n[Rn]

4/15

JMPL *n[Rn]

4/16

MOV

*n[Rn],A

4/17

MOV

A,*n[Rn]

4/16

*n[Rn]

4/16

CMP

*n[Rn],A

4/18

CALL *n[Rn]

4/20

CALLR

*n[Rn]

4/22

POP

1/8

LDSP

1/7

STSP

1/8

NOP

1/7

DIV

Rn.A

3/14-63

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

emp ate

e ease

ate:

– –

TMS370Cx0x

8-BIT MICROCONTROLLER

instructions have a relative address as the last operand.

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, and compact development tool, and an EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Allows high-speed operation – Provides format conversion utilities for popular formats

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3 or Sun-4)

– Generates assembly code for the TMS370 that can be inspected easily – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct reference to the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker

CDT370 (compact development tool) real-time in-circuit emulation – Base (Part Number EDSCDT370 – for PC, requires cable)

– Cable for 28-pin PLCC (Part No. EDSTRG28PLCC02) – Includes EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Allows uploading/downloading program and data memory – Executes programs and software routines – Includes 1024 samples trace buffer – Provides single-step executable instructions – Uses software breakpoints to halt program execution at selected address

Microcontroller programmer – Base (Part No. TMDS3760500A – for PC, requires programmer head)

– Single unit head for 28-pin PLCC (Part No. TMDS3780510A) – Personal computer based, window / function-key-oriented user interface for ease of use and rapid

learning environment

HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support (continued)

Design kit (Part No. TMDS3770110 – for PC) – Includes TMS370 Application Board and TMS370 Assembler diskette and documentation – Supports quick evaluation of TMS370 functionality – Provides capability to upload and download code – Provides capability to execute programs and software routines, and to single-step executable

instructions – Provides software breakpoints to halt program execution at selected addresses – Includes wire-wrap prototype area – Includes reverse assembler

Starter Kit (Part No. TMDS37000 – for PC) – Includes TMS370 Assembler diskette and documentation – Includes TMS370 Simulator – Includes programming adapter board and programming software – Does not include (to be supplied by the user):

– + 5 V power supply

– ZIF sockets

– Nine-pin RS232 cable

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

device numbering conventions

Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx0x family.

TMS

7370 0 2C

AFNT

TMS370Cx0x

Prefix: TMS = Standard prefix for fully qualified devices

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology: C = CMOS

Program Memory Types: 0 = Mask ROM

Device Type: 0 = ’x0x devices containing the following modules:

Memory Size: 2 = 8K bytes

Temperature Ranges: A = –40°Cto 85°C

Packages: FN = Plastic Leaded Chip Carrier

ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured

SE = System evaluator that is used for

prototyping purpose.

3 = Mask ROM, No Data EEPROM 7 = EPROM

— Timer 1 — Serial Communications Interface 1 (SCI1)

L= 0°Cto 70°C T = –40°Cto 105°C

FZ = Ceramic Leaded Chip Carrier

as one of the three different mask options:

– A standard watchdog – A hard watchdog – A simple watchdog

The clock mask option can be either:

– Divide-by-4 clock – Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled – Disabled

NONE = For EPROM device, a standard watchdog, a

divide-by-4 clock, and low-power modes are enabled.

Figure 12. TMS370Cx0x Family Nomenclature

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TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

device part numbers

T able 16 provides all of the ’x0x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. Each device can have only one of the three possible watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

Table 16. Device Part Numbers

DEVICE PART NUMBERS

FOR 28 PINS (LCC)

TMS370C002AFNA

TMS370C002AFNL TMS370C002AFNT

TMS370C302AFNA

TMS370C302AFNL TMS370C302AFNT

TMS370C702FNT

SE370C702FZT

†

System evaluators are for use in prototype environment and their reliability has not been characterized.

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

new code release form

Figure 13 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TMS370 MICROCONTROLLER PRODUCTS

T o release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

TEXAS INSTRUMENTS

DATE:

Company Name: Street Address: Street Address: City: State Zip

Customer Part Number: Customer Application:

TMS370 Device: TI Customer ROM Number:

(provided by T exas Instruments) OSCILLAT OR FREQUENCY

[] External Drive (CLKIN) [] Crystal [] Ceramic Resonator

[] Supply Voltage MIN: MAX: (std range: 4.5V to 5.5V)

TEMPERA TURE RANGE

[] ’L’: 0° to 70°C (standard) [] ’A’: –40° to 85°C [] ’T’: –40° to 105°C

SYMBOLIZA TION BUS EXPANSION

[] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization

(per attached spec, subject to approval)

MIN TYP MAX

Contact Mr./Ms.: Phone: ( ) Ext.:

Customer Purchase Order Number: Customer Print Number *Yes: #

*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM code processing starts.

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

Low Power Modes [] Enabled [] Disabled

NOTE: Non ’A’ version ROM devices of the TMS370 microcontrollers will have the “Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog options. See the

TMS370 Family Data Manual

or the PACKAGE TYPE

[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP [] “NJ” 40-pin PSDIP (formerly known as N2)

[] YES [] NO

No: (Std. spec to be followed)

Watchdog counter [] Standard [] Hard Enabled [] Simple Counter

TMS370 Family User’s Guide

(literature number SPNS014B).

Clock Type [] Standard (/4) [] PLL (/1)

(literature number SPNU127)

NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the TI part number.

RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer.

1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:

Figure 13. Sample New Code Release Form

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation

Table 17 is a collection of all the peripheral file frames used in the ’Cx0x (provided for a quick reference).

BIT 7

P010

ÁÁ

P011

ÁÁ

P012

COLD

STAR T

ÁÁ

—

ÁÁ

HALT/

STANDBY

P013

ÁÁ

P016

P017

ÁÁ

P018

P019

ÁÁ

P01A

INT1

FLAG

ÁÁ

INT2

FLAG

INT3

ÁÁ

FLAG

BUSY P01B Reserved P01C P01D

ÁÁ

P01E

P01F

ÁÁ

BUSY

P020 Reserved P021 P022 P023 P024

ÁÁ

P02B P02C P02D P02E

P02F

Modes: Dual-Compare and Capture/Compare

P040

Bit 15 T1Counter MSbyte Bit 8

P041

Bit 7 T1 Counter LSbyte Bit 0

P042

Bit 15 Compare Register MSbyte Bit 8

P043

Bit 7 Compare Register LSbyte Bit 0

BIT 6

BIT 5

System Configuration Registers

OSC

POWER

ÁÁ

—

ÁÁ

PWRDWN/

IDLE

INT1

PIN DATA

ÁÁ

INT2

PIN DATA

INT3

ÁÁ

PIN DATA

—

VPPS

PF AUTO

WAIT

ÁÁÁ

—

ÁÁÁ

—

ÁÁÁ

—

ÁÁÁ

—

OSC FLT

DISABLE

ÁÁ

DATA DIR

ÁÁ

DATA DIR

Digital Port Control Registers

Port A Control Register 2 (must be 0)

Port D Control Register 1 (must be 0)

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

Timer Module Register Memory Map

BIT 4

FLAG

AUTO

WAIT

BUS

STEST

Reserved

—

INT2

INT3

—

Reserved

Port A Data

Port A Direction

Reserved

†

BIT 3

MC PIN

WPO

ÁÁÁ

—

ÁÁÁ

CPU

STEST

—

ÁÁÁ

INT2

DATA OUT

INT3

ÁÁÁ

DATA OUT

—

BIT 2

MC PIN

DATA

MEMORY DISABLE

—

INT1

POLARITY

ÁÁ

INT2

POLARITY

INT3

ÁÁ

POLARITY

—

— — — —

BIT 1

—

ÁÁ

—

ÁÁ

INT1

NMI

INT1

PRIORITY

ÁÁ

INT2

PRIORITY

INT3

ÁÁ

PRIORITY

W1W0

— — — —

BIT 0

µP/µC MODE

ÁÁÁ

—

ÁÁÁ

PRIVILEGE

DISABLE

INT1

ENABLE

ÁÁÁ

INT2

ENABLE

INT3

ÁÁÁ

ENABLE

EXE

— — — —

REG

SCCR0

ÁÁ

SCCR1

ÁÁ

SCCR2

ÁÁ

INT1

ÁÁ

INT2

INT3

ÁÁ

DEECTL

EPCTL

ÁÁ

APORT1 APORT2 ADATA ADIR

ÁÁ

DPORT1 DPORT2 DDATA DDIR

T1CNTR

T1C

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Modes: Dual-Compare and Capture/Compare (Continued)

P044

Bit 15 Capture/Compare Register MSbyte Bit 8

P045

Bit 7 Capture/Compare Register LSbyte Bit 0

P046

Bit 15 Watchdog Counter MSbyte Bit 8

P047

Bit 7 Watchdog Counter LSbyte Bit 0

P048

Bit 7 Watchdog Reset Key Bit 0

WD OVRFL

P049

ÁÁ

WD OVRFL

P04A

Mode: Dual-Compare

P04B

ÁÁ

P04C

T1 MODE=0

Mode: Capture/Compare

P04B

ÁÁ

P04C

Modes: Dual-Compare and Capture/Compare

P04D

P04E

ÁÁ

P04F T1 STEST

P050

STOP BITS

ÁÁ

P051

P052

ÁÁ

P053 P054

P055

ÁÁ

P056 P057 P058

BIT 7

TAP SEL

RST ENA

T1EDGE

INT FLAG

T1EDGE

INT FLAG

MODE = 1

—

T1PWM DATA IN

—

BAUDF

(MSB)

BAUD7

TXRDY

ERROR

RXDT7

WD INPUT

†

SELECT2

ÁÁÁ

WD OVRFL

†

INT ENA

INT FLAG

ÁÁÁ

OUT ENA

ÁÁÁ

OUT ENA

T1PWM

ÁÁÁ

DATA OUT

PRIORITY

EVEN/ODD

ÁÁÁ

PARITY

ÁÁÁ

TX EMPTY

RXRDY

ÁÁÁ

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation (Continued)

BIT 6

T1C2

T1C1

—

T1C1

—

BAUDE BAUD6

RXDT6

†

BIT 5

WD INPUT SELECT1

ÁÁ

WD OVRFL

INT FLAG

T1C1

INT FLAG

ÁÁ

T1C2

OUT ENA

T1C1

INT FLAG

ÁÁ

—

T1PWM

ÁÁ

FUNCTION

—

PARITY

ÁÁ

ENABLE

SCI SW

RESET

BAUDD

ÁÁ

BAUD5

—

BRKDT

ÁÁ

RXDT5

WD INPUT

†

SELECT0

ÁÁÁ

T1 OVRFL

INT ENA

ÁÁÁ

RST ENA

ÁÁÁ

RST ENA

ÁÁÁ

DATA DIR

BIT 4

—

T1C1

—

T1C1

—

T1PWM

—

†

BIT 3

—

ÁÁ

T1 OVRFL

INT FLAG

—

ÁÁ

T1CR

OUT ENA

—

ÁÁ

—

T1EVT

DATA IN T1IC/CR

ÁÁ

DATA IN

—

SCI1 Module Control Memory Map

ASYNC/

ÁÁÁ

ISOSYNC

CLOCK

BAUDC

ÁÁÁ

BAUD4

—

ÁÁÁ

ADDRESS/

ÁÁ

IDLE WUP

TXWAKE

BAUDB

ÁÁ

BAUD3

—

ÁÁ

Reserved

RXDT4

RXDT3

Reserved

BIT 2

T1 INPUT SELECT2

ÁÁ

—

T1EDGE

INT ENA

ÁÁ

T1EDGE

POLARITY

T1EDGE

INT ENA

ÁÁ

T1EDGE

POLARITY

T1EVT

DATA OUT

T1IC/CR

ÁÁ

DATA OUT

—

SCI CHAR2

ÁÁ

SLEEP

BAUDA

ÁÁ

BAUD2

—

ÁÁ

RXDT2

TMS370Cx0x

8-BIT MICROCONTROLLER

BIT 1

T1 INPUT SELECT1

ÁÁÁ

—

T1C2

INT ENA

ÁÁÁ

T1CR

RST ENA

—

ÁÁÁ

—

T1EVT

FUNCTION

T1IC/CR

ÁÁÁ

FUNCTION

—

SCI CHAR1

ÁÁÁ

TXENA

BAUD9

ÁÁÁ

BAUD1

—

RXWAKE

ÁÁÁ

RXDT1

BIT 0

T1 INPUT SELECT0

ÁÁ

SW RESET

T1C1

INT ENA

ÁÁ

T1EDGE

DET ENA

T1C1

INT ENA

ÁÁ

T1EDGE

DET ENA

T1EVT

DATA DIR

T1IC/CR DATA

ÁÁ

DIR

—

SCI CHAR0

ÁÁ

RXENA

BAUD8

ÁÁ

BAUD0 (LSB)

SCI TX

INT ENA

SCI RX

INT ENA

ÁÁ

RXDT0

REG

T1CC

WDCNTR

WDRST T1CTL1

ÁÁÁ

T1CTL2

T1CTL3

ÁÁÁ

T1CTL4

T1CTL3

ÁÁÁ

T1CTL4

T1PC1

T1PC2

ÁÁÁ

T1PRI

SCICCR

ÁÁÁ

SCICTL

BAUD MSB

ÁÁÁ

BAUD LSB TXCTL

RXCTL

ÁÁÁ

RXBUF

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation (Continued)

P059

P05A P05B

ÁÁ

P05C

ББББББББББББББББББББББББББ

P05D

P05E

ÁÁ

DATA IN

P05F SCI STEST

BIT 7

TXDT7

—

SCITXD

BIT 6

TXDT6

—

SCITXD

ÁÁ

DATA OUT

SCITX

PRIORITY

BIT 5

SCI1 Module Control Memory Map (Continued)

TXDT5

—

SCITXD

ÁÁÁ

FUNCTION

SCIRX

PRIORITY

BIT 4

TXDT4

—

SCITXD

ÁÁ

DATA DIR

SCI

ESPEN

Reserved

DATA IN SCIRXD

ÁÁÁ

DATA IN

BIT 3

TXDT3

SCICLK

—

BIT 2

TXDT2

SCICLK

DATA OUT

SCIRXD

ÁÁ

DATA OUT

—

BIT 1

TXDT1

SCICLK

FUNCTION

SCIRXD

ÁÁ

FUNCTION

—

BIT 0

TXDT0

SCICLK DATA

DIR

SCIRXD DATA

ÁÁÁ

DIR

—

REG

TXBUF

ÁÁ

SCIPC1

SCIPC2

ÁÁ

SCIPRI

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range,VCC (see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current per buffer, I Maximum I Maximum I

current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA:L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.

2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers.

< 0 or V

> V

CC)

(VO = 0 to V

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

) (see Note 2) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . .

CC)

A version – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T version – 40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

VILLow-level input voltage

recommended operating conditions

Supply voltage (see Note 1) 4.5 5 5.5 V

RAM data-retention supply voltage (see Note 3) 3 5.5 V

High-level input voltage

MC (mode control) voltage

Operating free-air temperature

NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS.

3. RESET

must be activated externally when VCC or SYSCLK is not within the recommended operating range.

All pins except MC V MC, normal operation V All pins except MC, XTAL2/CLKIN, and

RESET XTAL2/CLKIN RESET 0.7 V EEPROM write protect override (WPO) 11.7 12 13 EPROM programming voltage (VPP) Microcomputer V L version 0 70 A version T version – 40 105

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MIN NOM MAX UNIT

SS SS

2 V

0.8 V

CC CC

13 13.2 13.5

– 40 85

0.8

0.3

°C

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

VOHHigh-level output voltage

MC IOHHigh-level output current

y( )

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

NOTES: 4. Input current IPP is a maximum of 50 mA only when programming EPROM.

Low-level output voltage IOL = 1.4 mA 0.4 V

Input current

I/O pins 0 V ≤ VI ≤ V

Low-level output current VOL = 0.4 V 1.4 mA

Supply current (operating mode) OSC POWER bit = 0 (see Note 7)

Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 8)

Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 9)

Supply current (HALT mode)

5. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2 V.

6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF).

7. Maximum operating current = 5.6 (SYSCLK) + 8 mA.

8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz of SYSCLK).

IOH = –50 µA 0.9 V IOH = –2 mA 2.4 0 V ≤ VI ≤ 0.3 V 10

0.3 V < VI ≤ 13 V 650 See Note 4

12 V ≤ VI ≤ 13 V

VOH = 0.9 V VOH = 2.4 V – 2 mA See Notes 5 and 6

SYSCLK = 5 MHz See Notes 5 and 6

SYSCLK = 3 MHz See Notes 5 and 6

SYSCLK = 0.5 MHz See Notes 5 and 6

SYSCLK = 5 MHz See Notes 5 and 6

SYSCLK = 3 MHz See Notes 5 and 6

SYSCLK = 0.5 MHz See Notes 5 and 6

SYSCLK = 3 MHz See Notes 5 and 6

SYSCLK = 0.5 MHz See Note 5

XTAL2/CLKIN < 0.2 V

50 mA

± 10 µA

– 50 µA

20 36

13 25

5 11

10 17

6.5 11

2 3.5

4.5 8.6

1.5 3.0

1 30 µA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

XTAL1XTAL2/CLKIN

(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic

resonators.

Crystal/Ceramic

Resonator

(see Note A)

C2 (see Note B)C1

External

Clock Signal

XTAL1XTAL2/CLKIN

C3 (see Note B)

Figure 14. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

20 pF

Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

I/O

300 Ω

30 Ω

Figure 15. Typical Output Load Circuit (See Note A)

Pin Data Output

Enable

20 Ω

GND

Figure 16. T ypical Buffer Circuitry

INT1

6 kΩ

20 Ω

GND

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

AR Array SC SYSCLK B Byte SCC SCICLK CI XTAL2/CLKIN TXD SCITXD RXD SCIRXD

Lowercase subscripts and their meanings are:

c cycle time (period) su setup time d delay time v valid time f fall time w pulse duration (width) r rise time

The following additional letters are used with these meanings:

H High L Low V Valid

All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.

0.8 VCC V (High)

0.8 V (Low)

Figure 17. XTAL2/CLKIN Measurement Points Figure 18. General Measurement Points

2 V (High)

0.8 V (Low)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

external clocking requirements for divide-by-4 clock (see Note 10 and Figure 19)

NO. MIN MAX UNIT

1 t

w(Cl)

2 t

r(Cl)

3 t

f(CI)

4 t

d(CIH-SCL)

CLKIN Crystal operating frequency 2 20 MHz SYSCLK Internal system clock operating frequency

†

SYSCLK = CLKIN/4

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns Rise time, XTAL2/CLKIN 30 ns Fall time, XTAL2/CLKIN 30 ns Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns

†

XTAL2/CLKIN

SYSCLK

0.5 5 MHz

Figure 19. External Clock Timing for Divide-by-4

external clocking requirements for divide-by-1 clock (PLL) (see Note 10 and Figure 20)

NO. MIN MAX UNIT

1 t

w(Cl)

2 t

r(Cl)

3 t

f(CI)

4 t

d(CIH-SCH)

CLKIN Crystal operating frequency 2 5 MHz SYSCLK Internal system clock operating frequency

‡

SYSCLK = CLKIN/1

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

Pulse duration, XTAL2/CLKIN (see Note 11) 20 ns Rise time, XTAL2/CLKIN 30 ns Fall time, XTAL2/CLKIN 30 ns Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns

XTAL2/CLKIN

SYSCLK

‡

2 5 MHz

Figure 20. External Clock Timing for Divide-by-1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

tcCycle time, SYSCLK (system clock)

SYSCLK

System clock operating frequenc

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

switching characteristics and timing requirements (see Note 12 and Figure 21)

NO. PARAMETER MIN MAX UNIT

Divide-by-4 200 2000 Divide-by-1 200 500

6 t

w(SCL)

7 t

w(SCH)

NOTE 12: tc = system-clock cycle time = 1/SYSCLK

Pulse duration, SYSCLK low 0.5 tc–20 0.5 t Pulse duration, SYSCLK high 0.5 t

0.5 tc + 20 ns

SYSCLK

Figure 21. SYSCLK Timing

general purpose output signal switching time requirements (see Figure 22)

MIN NOM MAX UNIT

trRise time 30 ns tfFall time 30 ns

Figure 22. Signal Switching Time

recommended EEPROM timing requirements for programming

MIN MAX UNIT

w(PGM)B

w(PGM)AR

Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms

recommended EPROM operating conditions for programming

V V I

CC PP

Supply voltage 4.75 5.5 6 V Supply voltage at MC pin 13 13.2 13.5 V Supply current at MC pin during programming (VPP = 13 V) 30 50 mA

recommended EPROM timing requirements for programming

w(EPGM)

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and V

Pulse duration, programming signal (see Note 13) 0.40 0.50 3 ms

MIN NOM MAX UNIT

(EPCTL.6) are set.

PPS

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Divide-by-4 0.5 5 Divide-by-1 2 5

MIN NOM MAX UNIT

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

SCI1 isosynchronous mode timing characteristics and requirements for internal clock (see Note 12 and Figure 23)

NO. MIN MAX UNIT

24 t

c(SCC)

25 t

w(SCCL)

26 t

w(SCCH)

27 t

d(SCCL-TXDV)

28 t

v(SCCH-TXD)

29 t

su(RXD-SCCH)

30 t

v(SCCH-RXD)

NOTE 12: tc = system-clock cycle time = 1/SYSCLK

SCICLK

Cycle time, SCICLK 2t Pulse duration, SCICLK low tc– 45 0.5t Pulse duration, SCICLK high tc– 45 0.5t Delay time, SCITXD valid after SCICLK low – 50 60 ns Valid time, SCITXD data valid after SCICLK high t Setup time, SCIRXD to SCICLK high 0.25 tc + 145 ns Valid time, SCIRXD data valid after SCICLK high 0 ns

w(SCCH)

– 50 ns

131072t

c(SCC) c(SCC)

+45 ns +45 ns

SCITXD

SCIRXD

Data Valid

Figure 23. SCI1 Isosynchronous Mode Timing for Internal Clock

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

SCI1 isosynchronous mode timing characteristics and requirements for external clock (see Note 12 and Figure 24)

NO. MIN MAX UNIT

31 t

c(SCC)

32 t

w(SCCL)

33 t

w(SCCH)

34 t

d(SCCL-TXDV)

35 t

v(SCCH-TXD)

36 t

su(RXD-SCCH)

37 t

v(SCCH-RXD)

NOTE 12: tc = system-clock cycle time = 1/SYSCLK

SCICLK

Cycle time, SCICLK 10t

ns Pulse duration, SCICLK low 4.25tc+ 120 ns Pulse duration, SCICLK high tc + 120 ns Delay time, SCITXD valid after SCICLK low 4.25tc + 145 ns Valid time, SCITXD data valid after SCICLK high t

w(SCCH)

ns Setup time, SCIRXD to SCICLK high 40 ns Valid time, SCIRXD data after SCICLK high 2t

SCITXD

Data Valid

SCIRXD

Data Valid

Figure 24. SCI1 Isosynchronous Timing for External Clock

Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name.

Table 18. TMS370Cx0x Family Package T ype and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

БББББ

FN – 28 pin

БББББ

(50-mil pin spacing)

БББББ

FZ – 28 pin (50-mil pin spacing)

БББББ

TMS370 GENERIC NAME

ББББББББ

PLASTIC LEADED CHIP CARRIER

ББББББББ

(PLCC)

ББББББББ

CERAMIC LEADED CHIP CARRIER (CLCC)

ББББББББ

ББББББББББ

FN(S-PQCC-J**) PLASTIC J-LEADED

ББББББББББ

CHIP CARRIER

ББББББББББ

FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

ББББББББББ

PKG TYPE NO. AND

MECHANICAL NAME

DEVICE PART NUMBERS

TMS370C002AFNA TMS370C002AFNL

ББББББ

TMS370C002AFNT

ББББББ

TMS370C302AFNA TMS370C302AFNL

ББББББ

TMS370C302AFNT

ББББББ

TMS370C702FNT SE370C702FZT

ББББББ

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

E1E

NO. OF

PINS

D/E

0.032 (0,81)

0.026 (0,66)

0.050 (1,27)

0.008 (0,20) NOM

D1/E1

MINMAXMIN

MAX

D2/E2

MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

D2/E2

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

MAX

20 28 44 52 68 84

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)  45°

A B

1426

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

0.120 (3,05)

0.032 (0,81)

0.026 (0,66)

0.025 (0,64) R TYP

Seating Plane

0.050 (1,27)

(at Seating

Plane)

0.020 (0,51)

0.014 (0,36)

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

NO. OFJEDEC

OUTLINE

MO-087AA

MO-087AB

MO-087AC

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

PINS**

68MO-087AD

MIN MAX

0.485

(12,32) (12,57)

0.495

0.430

MAXMIN

0.455

(11,56)(10,92)

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

4040219/B 03/95

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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Texas Instruments TMS370C702FNT Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual