Texas Instruments TMS370C702FNT Datasheet

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 8K Bytes

– EPROM: 8K Bytes – Data EEPROM: 256 Bytes – Static RAM: 256 Bytes Usable as

Registers

Flexible Operating Features – Low-Power Modes: STANDBY and HAL T – Commercial, Industrial, and Automotive

T emperature Ranges – Clock Options

– Divide-by-4 (0.5 to 5 MHz SYSCLK)

– Divide-by-1 (2 to 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Supply Voltage (V

16-Bit General-Purpose Timer

) 5 V ±10%

– Software Configurable as

a 16-Bit Event Counter, or

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

Two Compare Registers, or a

Self-Contained Pulse-Width-Modulation

(PWM) Function – Software Programmable Input Polarity – Eight-Bit Prescaler, Providing a 24-Bit

Real-Time Timer

On-Chip 24-Bit Watchdog Timer – EPROM/OTP Devices: Standard

Watchdog – Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Flexible Interrupt Handling – Two Software-Programmable Interrupt

Levels – Global- and Individual-Interrupt Masking – Programmable Rising or Falling Edge

Detect – Individual Interrupt Vectors

FZ AND FN PACKAGES

(TOP VIEW)

VA7D7D6D3

3212827

426

A6 A5 A4 A3 A2

5 6 7 8 9 10 11

12 13

14 15 16 1718

XTAL2/CLKIN

XTAL1

Serial Communications Interface 1 (SCI1)

INT1

RESET

25 24 23 22 21 20 19

INT2

INT3

SCITXD SCICLK SCIRXD T1IC/CR T1PWM T1EVT MC

– Asynchronous Mode: 156K bps

Maximum at 5 MHz SYSCLK

– Isosynchronous Mode: 25M bps

Maximum at 5 MHz SYSCLK

– Full Duplex, Double-Buffered Receiver

(RX) and Transmitter (TX)

– Two Multiprocessor Communication

Formats

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/TTL Compatible I/O Pins/Packages – All Peripheral Function Pins Software

Configurable for Digital I/O – 21 Bidirectional Pins, 1 Input Pin – 28-Pin Plastic and Ceramic Leaded Chip

Carrier Packages

Workstation/Personal Computed-Based Development System – C Compiler and C Source Debugger – Real-time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Multi-Window User Interface – Microcontroller Programmer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS370Cx0x

†

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

28 PINS

LCC

NAME

A0 A1

ÁÁÁ

A3 A4

ÁÁÁ

A6 A7

ÁÁÁ

D3 D4 D5

ÁÁÁ

D7 INT1

INT2

ÁÁÁ

INT3 T1IC/CR

ÁÁÁ

T1PWM T1EVT

SCITXD

ÁÁÁ

SCIRXD SCICLK

ÁÁÁ

RESET MC

NO.

14 13

ÁÁ

28 26 15

ÁÁ

16 17

ÁÁ

18 22

ÁÁ

21 20

ÁÁ

23 24

ÁÁ

27 19

XTAL2/CLKIN XTAL1

ÁÁÁ

†

I = input, O = output

‡

The three-pin SCI configuration is referred to as SCI1.

ÁÁ

I/O

9 8 7 3

1 2

I/O

ББББББББББББББББББББББББ

Port A is a general-purpose bidirectional I/O port.

ББББББББББББББББББББББББ

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

ББББББББББББББББББББББББ

External interrupt (non-maskable or maskable)/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin

ББББББББББББББББББББББББ

External maskable interrupt input/general-purpose bidirectional pin Timer1 input capture/counter reset input pin /general-purpose bidirectional pin

I/O

ББББББББББББББББББББББББ

Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

SCI transmit data output pin, general-purpose bidirectional pin

I/O

5 6

ББББББББББББББББББББББББ

SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

ББББББББББББББББББББББББ

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET

indicates that an internal failure was detected by watchdog or oscillator fault circuit.

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM V

Internal oscillator crystal input/External clock source input

Internal oscillator output for crystal

ББББББББББББББББББББББББ

Positive supply voltage Ground reference

Pin Descriptions

DESCRIPTION

‡

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functional block diagram

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

INT1

INT2 INT3 XTAL1

Clock Options:

Interrupts

CPU

Program Memory

ROM: 8K Bytes

EPROM: 8K Bytes

Port A Port D

Divide-By-4 Or

Divide-By-1 (PLL)

XTAL2/

CLKIN

Data EEPROM 0 or 256 Bytes

System Control

RAM

256 Bytes

RESET

Serial

Communications

Interface 1

Timer 1

Watchdog

SCIRXD SCITXD SCICLK

T1IC/CR T1EVT T1PWM

description

The TMS370C002, TMS370C302, TMS370C702, and SE370C702 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx0x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations.

The TMS370Cx0x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx0x devices attractive in system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications.

All TMS370Cx0x devices contain the following on-chip peripheral modules:

Serial communications interface 1 (SCI1)

One 16-bit general-purpose timer with an 8-bit prescaler

One 24-bit general-purpose watchdog timer

Table 1 provides a memory configuration overview of the TMS370Cx0x devices.

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TMS370Cx0x

Divide-by-1 (PLL)

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

Table 1. Memory Configurations

БББББ

DEVICE

TMS370C002A TMS370C302A TMS370C702 SE370C702

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

†

PROGRAM MEMORY

ББББББББ

ROM

8K 8K

— —

(BYTES)

EPROM

—

— 8K 8K

DATA MEMORY

БББББББ

RAM

256 256 256 256

(BYTES)

EEPROM

256

— 256 256

БББББББББ

28-PIN PACKAGE

FN – PLCC FN – PLCC FN – PLCC FZ – CLCC

The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM without A Standard Divide-by-4 (standard oscillator) Enabled

ROM A

Standard

Hard

Simple

Divide-by-4 or

Enabled or disabled

The 8K bytes of mask-programmable ROM in the associated TMS370Cx0x devices are replaced in the TMS370C702 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the TMS370C302 devices. The one-time programmable (OTP) (TMS370C702) device and reprogrammable device (SE370C702) are available.

TMS370C702 OTP devices are available in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx0x family or for low-volume production runs when the mask charge or cycle time for low-cost mask ROM devices is not practical.

The SE370C702 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development-prototyping phase of design. The SE370C702 devices allow quick updates to breadboards and prototype systems while iterating initial designs.

The TMS370Cx0x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx0x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx0x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family.

The TMS370Cx0x devices have two operational modes of serial communications provided by the SCI1 module. The SCI1 allows standard RS-232-C communications with other common data transmission equipment.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

The TMS370Cx0x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx0x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through extensive menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx0x family together with the TMS370 family CDT370, design kit, starter kit, software tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU used on the TMS370Cx0x device is the high-performance 8-bit TMS370 CPU module. The ’x0x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x0x instruction map is shown in T able 15 in the TMS370Cx0x instruction set overview section.

The ’370Cx0x CPU architecture provides the following components: CPU registers:

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global interrupt enable bits

A program counter (PC) that points to the memory location of the next instruction to be executed

Figure 1 illustrates the CPU registers and memory blocks.

CDT is a trademark of Texas Instruments Incorporated.

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TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

RAM (Includes 256-Byte Registers File)

0000h

0001h 0002h 0003h

007Fh

Stack Pointer (SP)

Status Register (ST)

R0(A) R1(B)

R2 R3

R127

Program Counter

IE1IE2ZNC

015

01234567

Legend:

C=Carry N=Negative

Z=Zero

V=Overflow

IE2=Level 2 interrupts Enable IE1=Level 1 interrupts Enable

256-Byte RAM (0000h - 00FFh)

256-Byte Data EEPROM

8K-Byte ROM/EPROM (6000h–7FFFh)

Reserved

Peripheral File

Reserved

Not Available

†

0000h 00FFh 0100h 100Fh

1010h 105Fh

1060h

1EFFh 1F00h

‡

1FFFh 2000h 5FFFh 6000h

00FFh

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

R255

Interrupts and Reset Vectors;

Trap Vectors

Figure 1. Programmer’s Model

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions, general-purpose register, or the stack

A peripheral file that provides access to all internal peripheral modules, system-wide control functions and EEPROM/EPROM programming control

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off conditions

8K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used typically to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM memory.

7FBFh 7FC0h

7FFFh

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TMS370Cx0x

8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST register includes four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional jump instructions) use the status bits to determine program flow.

The two interrupt enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers (ST)

RW-0

R = read, W = write, 0 = value after reset

RW-0

5 Z

RW-0

4 V

RW-0

IE2

RW-0

IE1 Reserved Reserved

RW-0

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most significant byte and least significant byte of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector.

Program Counter (PC)

0000h

7FFEh 7FFFh

Memory

60 00

PCH PCL

60 00

Figure 2. Program Counter After Reset

memory map

The TMS370Cx0x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx0x provides memory-mapped RAM, ROM, Data EEPROM, input/output pins, peripheral functions, and system interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file is located between 1010h to 105Fh and is divided logically into five peripheral-file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed.

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TMS370Cx0x 8-BIT MICROCONTROLLER

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central processing unit (CPU) (continued)

0000h

00FFh

0100h

100Fh 1010h

105Fh

1060h

1EFFh

1F00h

1FFFh

2000h

5FFFh

6000h

6FFFh

7000h

77FFh

7800h

7FBFh 7FC0h

7FFFh

8000h

FFFFh

†

Reserved means the address space is reserved for future expansion.

‡

Not available means the address space is not accessible.

256-Byte RAM

(Register File/Stack)

Reserved

Peripheral File

Reserved

256-Byte Data EEPROM

Not Available

8K-Byte ROM/EPROM

(6000h–7FFFh)

Interrupts and Reset Vectors;

Trap Vectors

Not Available

†

‡

Peripheral File Control Registers

System Control

Digital Port Control

Reserved

Timer 1 Peripheral Control

SCI1 Peripheral Control 1050h–105Fh

Vectors

Trap 15–0

Reserved

Serial Communications Interface TX 7FF0h–7FF1h

Serial Communications Interface RX

Timer 1 7FF4h–7FF5h Reserved Interrupt 3 7FF8h–7FF9h Interrupt 2 7FFAh–7FFBh Interrupt 1 7FFCh–7FFDh

†

Reset 7FFEh–7FFFh

1010h–101Fh 1020h–102Fh 1030h–103Fh 1040h–104Fh

7FC0h–7FDFh 7FE0h–7FEFh

7FF2h–7FF3h

7FF6h–7FF7h

Figure 3. TMS370Cx0x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx0x devices contain 256 bytes of internal memory-mapped RAM beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx0x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 shows the TMS370Cx0x PF address map.

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БББББББ

peripheral file (PF) (continued)

Table 4. TMS370Cx0x Peripheral File Address Map

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

ADDRESS RANGE

БББББ

1000h–100Fh 1010h–101Fh 1020h–102Fh 1030h–103Fh 1040h–104Fh 1050h–105Fh 1060h–10FFh

PERIPHERAL FILE

DESIGNAT OR

БББББ

БББББББББББББББББББ

P000–P00F Reserved P010–P01F P020–P02F P030–P03F P040–P04F

System and EPROM/EEPROM control registers Digital I/O port control registers Reserved

Timer 1 registers P050–P05F Serial communications interface registers P060–P0FF

Reserved

DESCRIPTION

data EEPROM

The TMS370Cx0x devices, containing 256 bytes of data EEPROM, have their memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

Family Data Manual

Programming:

(literature number SPNS014B). The data EEPROM features include the following:

– Bit-, byte-, and block-write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A. See Table 5.

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370

– In-circuit programming capability. There is no need to remove the device to program.

Write protection. Writes to the data EEPROM are disabled during the following conditions. – Reset. All programming of the data EEPROM module is halted. – Write protection active. There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

P01A P01B P01C

SYMBOL

DEECTL

Data EEPROM control register

— Reserved

EPCTL

Program EPROM control register

NAME

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TMS370Cx0x 8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

program EPROM

The TMS370C702 device contains 8K bytes of EPROM, mapped, at location 6000h and continuing through location 7FFFh as shown in Figure 3. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include:

Programming – In-circuit programming capability if VPP is applied to MC – Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset halts all programming to the EPROM module. – Low-power modes – 13 V not applied to MC

program ROM

The program read-only memory (ROM) consists of 8K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system reset operation ensures an orderly start-up sequence for the TMS370Cx0x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET pin) is controlled externally. These actions are as follows:

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer times out . See the

Family User’s Guide

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the

TMS370 Family User’s Guide

Once a reset source is activated, the external RESET cycles. This allows the ’x0x device to reset external system components. Additionally , if a cold start (V for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.

(literature number SPNU127) for more information.

pin is driven (active) low for a minimum of eight SYSCLK

TMS370

is off

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD ST ART , SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

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system reset (continued)

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 6. Reset Sources

SCCR0 SCCR0

T1CTL2

ADDRESS

1010h 1010h

104Ah

P010 P010 P04A

BIT NO.

7 4 5

CONTROL BIT

COLD START

OSC FLT FLAG

WD OVRFL INT FLAG

SOURCE OF RESET

Cold (power-up)

Oscillator out of range

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.

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interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of the status register.

EXT INT 3

INT 3

EXT INT 2

INT 2

SCI INT

TX TXRDY

TXPRI

TIMER1

Overflow

Compare1

Ext Edge

Compare2 Input Capture Watchdog

RXPRI

BRKDT

T1 PRI

INT3 PRI

INT1

EXT INT1

INT1 PRI

INT2 PRI

STATUS REG

IE1

IE2

Enable

CPU

NMI

Priority

Logic

Level 1 INT Level 2 INT

RXRDY

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx0x has six hardware system interrupts (plus RESET

) as shown in T able 7. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt.

Three of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- or global-enable-mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software-configured as general-purpose input / output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin).

Table 7. Hardware System Interrupts

INTERRUPT SOURCE

External RESET Watchdog Overflow

БББББББББ

Oscillator Fault Detect External INT1 External INT2 External INT3 Timer 1 Overflow

Timer 1 Compare 1

БББББББББ

Timer 1 Compare 2

БББББББББ

Timer 1 External Edge Timer 1 Input Capture 1

БББББББББ

Watchdog Overflow SCI RX Data Register Full

SCI RX Break Detect

БББББББББ

SCI TX Data Register Empty

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes.

Release microcontroller from STANDBY low-power mode.

INTERRUPT FLAG

COLD START WD OVRFL INT FLAG

БББББББ

OSC FLT FLAG INT1 FLAG INT2 FLAG INT3 FLAG T1 OVRFL INT FLAG

T1C1 INT FLAG

БББББББ

T1C2 INT FLAG

БББББББ

T1EDGE INT FLAG T1IC1 INT FLAG

БББББББ

WD OVRFL INT FLAG RXRDY FLAG

BRKDT FLAG

БББББББ

TXRDY FLAG

SYSTEM

INTERRUPT

‡

RESET

ÁÁÁÁ

‡

INT1

‡

INT2

‡

INT3

ÁÁÁÁ

T1INT

RXINT

‡

TXINT

VECTOR

ADDRESS

7FFEh, 7FFFh

БББББ

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

БББББ

7FF4h, 7FF5h

БББББ

7FF2h, 7FF3h

БББББ

7FF0h, 7FF1h

PRIORITY

ÁÁ

2 3 4

ÁÁ

†

privileged operation and EEPROM write protection override

The TMS370Cx0x family has significant flexibility to enable the designer to software configure the system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx0x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the

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privileged operation and EEPROM WPO (continued)

nonprivileged mode, thus disabling write operations to specific configuration control bits within the peripheral file. T able 8 lists the system configuration bits which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

Table 8. Privileged Bits

NAME

SCCR0

SCCR1

ÁÁÁ

SCCR2

ÁÁÁ

SCIPRI

ÁÁÁ

T1PRI

†

The privileged bits are shown in a bold typeface in Table 10.

†

LOCATION

P010.5 P010.6

P011.2

ÁÁÁ

P011.4 P012.0

P012.1

ÁÁÁ

P012.3

ÁÁÁ

P012.4 P012.6

ÁÁÁ

P012.7 P05F.4

P05F.5

ÁÁÁ

P05F.6

ÁÁÁ

P05F.7 P04F.6

P04F.7

PF AUTO WAIT OSC POWER

MEMORY DISABLE

БББББББ

AUTOWAIT DISABLE PRIVILEGE DISABLE

INT1 NMI

БББББББ

CPU STEST

БББББББ

BUS STEST PWRDWN/IDLE

БББББББ

HALT/STANDBY SCI ESPEN

SCIRX PRIORITY

БББББББ

SCITX PRIORITY

БББББББ

SCI STEST T1 PRIORITY

T1 STEST

The write protect override (WPO) mode is an external hardware method of overriding the write protection registers (WPR) of data EEPROM on the TMS370Cx0x. WPO mode is entered by applying a 12-V input to the MC pin after the RESET pin input goes high (logic 1). The high voltage (+ 12 V) on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the content of data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx0x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops; however, the oscillator, internal clocks, timer 1 and the receive-start bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET detected.

, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is

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low-power and IDLE modes (continued)

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx0x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET on the receive pin of the SCI1) is detected. The power-down mode selection bits are summarized in Table 9.

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

1 1 0

†

Don’t care

HALT/STANDBY

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6-7 bits are ignored. In addition, if an idle instruction executes when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

, external interrupt on the INT1, INT2, INT3, or low level

MODE SELECTED

(SCCR2.7)

0 1

†

STANDBY HALT IDLE

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing stops during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ’x0x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ’x0x ROM-masked devices of fer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’702A EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency , whereas the divide-by-4 option produces a SYSCLK which is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

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Texas Instruments TMS370C702FNT Datasheet

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