Texas Instruments TMS3473BKL, TMS3473BDW-X, TMS3473BDW Datasheet

TMS3473B

PARALLEL DRIVER

SOCS022B – NOVEMBER 1990

Copyright  1990, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• TTL-Compatible Inputs

• CCD-Compatible Outputs

• Variable-Output Slew Rates With External

Resistor Control

• Full-Frame Operation

• Frame-Transfer Operation

• Solid-State Reliability

• Adjustable Clock Levels

description

The TMS3473B is a monolithic CMOS integrated
circuit designed to drive the parallel image-area
gate (IAG), parallel storage-area gate (SAG), and
antiblooming gate (ABG) inputs of the Texas Instruments (TI) virtual-phase CCD image sensors. The
TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL-input signals
from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor.

The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When
the TMS3473B I

/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I/N is

connected to V

CC

, the noninterlace mode is selected (see Figure 2).

ABOUT follows ABIN and switches between V

ABG+

and V

ABG–

. IAOUT and SAOUT follow IAIN and SAIN,

respectively , and switch between V

CC

and VSS. Additionally , ABOUT and IAOUT can each be made to output
midlevel voltages. DC inputs to ABL VL and IALVL determine the midlevel voltages that can be output on ABOUT
and IAOUT , respectively . A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic
level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected.

Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to V

CC

and ABSR to V

ABG+

through external resistors. The larger the resistor values, the longer the rise and fall times are.
A low-logic level on PD

causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT

and SAOUT to V

SS

, ABOUT to V

ABG–

).

The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from
–20°C to 45°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these

high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.
Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices and Assemblies

available from Texas Instruments.

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2
3
4
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7
8
9
10

20
19
18
17
16
15
14
13
12
11

IAL VL

I

/N

IAIN

ABIN

MIDSEL

SAIN

PD

GND

V

ABG+

V

SS

V

SS

IASR
ABSR
V

CC

ABLVL
IAOUT
ABOUT
SAOUT
V

CC

V

ABG–

DW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

TI is a trademark of Texas Instruments Incorporated.

TMS3473B
PARALLEL DRIVER

SOCS022B – NOVEMBER 1990

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

TTL/CCD

ABOUT

14

4

ABIN

16

ABLVL

18

ABSR

3

IAIN

1

IALVL

19

IASR

6

SAIN

IAOUT

15

SAOUT

13

NONINT

2

TMS3473B

Φ

INT/M1
PWR DWN

7

ABOUT to midlevel

5

MIDSEL

1(IAOUT to midlevel)

I/N

PD

TMS3473B

PARALLEL DRIVER

SOCS022B – NOVEMBER 1990

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ABIN 4 I Antiblooming in

ABLVL 16 I DC antiblooming midlevel voltage

ABOUT 14 O Antiblooming out

ABSR 18 I Antiblooming slew rate

GND 8 Ground

IAIN 3 I Parallel-image-area in

IALVL 1 I DC parallel-image-area midlevel voltage

IAOUT 15 O Parallel-image-area out

IASR 19 I Parallel-image-area slew rate

I/N 2 I Interlace/noninterlace select

MIDSEL 5 I IAOUT/ABOUT midlevel voltage select

PD 7 I Power down

SAIN 6 I Parallel storage area in
SAOUT 13 O Parallel storage area out
V

ABG+

9 I Positive ABG supply voltage

V

ABG–

11 I Negative ABG supply voltage

V

CC

†

12 I Positive supply voltage

V

CC

†

17 I Positive supply voltage

V

SS

†

10 I Negative supply voltage

V

SS

†

20 I Negative supply voltage

†

All terminals of the same name should be connected together externally.

IAIN

ABIN

MIDSEL

IAOUT

ABOUT

I

/N

Integrate

Readout

or

Transfer to

Memory

‡

ABOUT

IAOUT

MIDSEL

ABIN

IAIN

I

/N

TV Field BTV Field A

Integrate

Readout

or

Transfer to

Memory

‡

–9 V

5 V
0 V

5 V
0 V

5 V
0 V

1.5 V
–9 V

–3 V

3 V

–8 V

–2.5 V

2 V
5 V

0 V
5 V

0 V
5 V

0 V

1.5 V
–9 V

3 V

–8 V

–2.5 V

Figure 1. Parallel-Driver Timing Diagram

(interlace mode)

Figure 2. Parallel-Driver Timing Diagram

(noninterlace mode)

‡

A readout occurs if the TMS3473B is driving a full-frame CCD image sensor; a transfer to memory occurs if the TMS3473B is driving a
frame-transfer CCD image sensor.