TEXAS INSTRUMENTS TMS320VC5421 Technical data

TMS320VC5421 Fixed-Point

Digital Signal Processor

Data Manual

Literature Number: SPRS098C

December 1999 – Revised November 2001

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

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Mailing Address:

Texas Instruments Post Office Box 655303 Dallas, Texas 75265

REVISION HISTORY

REVISION DATE PRODUCT STATUS HIGHLIGHTS

* April 1999 Product Preview Original

A January 2000 Product Preview Revised HPI timing and switching characteristics data.

B August 2000 Production Data

C November 2001 Production Data

Converted to data manual format and revised to include production characteristics data.

Removed all references to an industrial part temperature range.

iii

Contents

Section Page

1 TMS320VC5421 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Migration From the 5420 to the 5421 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Pin Assignments 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Pin Assignments for the PGE Package 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Terminal Assignments for the GGU Package 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Signal Descriptions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Overview 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Memory 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 On-Chip Dual-Access RAM (DARAM) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 On-Chip Single-Access RAM (SARAM) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 On-Chip Two-Way Shared RAM (DARAM) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 On-Chip Boot ROM 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 Extended Program Memory 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.6 Program Memory 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.7 Data Memory 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.8 I/O Memory 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Multicore Reset Signals 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Bootloader 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 External Interface (XIO) 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 On-Chip Peripherals 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Software-Programmable Wait-State Generators 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 Programmable Bank-Switching 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 Parallel I/O Ports 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 16-Bit Bidirectional Host-Port Interface (HPI16) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 HPI16 Memory Map 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2 HPI Features 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 HPI Multiplexed Mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.4 Host/DSP Interrupts 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.5 Emulation Considerations 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.6 HPI Nonmultiplexed Mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.7 Other HPI16 System Considerations 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Multichannel Buffered Serial Port (McBSP) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 Emulation Considerations 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Direct Memory Access (DMA) Controller 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 DMA Controller Features 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.2 DMA Accesses to External Memory 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.3 DMA Controller Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.4 DMA Channel Interrupt Selection 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.5 DMA in Autoinitialization Mode 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.6 Subsystem Communications 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.7 Chip Subsystem ID Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 1999 – Revised November 2001 SPRS098C

Contents

Section Page

3.9 General-Purpose I/O 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.1 Hardware Timer 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.2 Software-Programmable Phase-Locked Loop (PLL) 39. . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.3 PLL Clock Programmable Timer 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Memory-Mapped Registers 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 McBSP Control Registers and Subaddresses 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 DMA Subbank Addressed Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13 Interrupts 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14 IDLE3 Power-Down Mode 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.15 Emulating the 5421 Device 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Documentation Support 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Electrical Specifications 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Package Thermal Resistance Characteristics 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Timing Parameter Symbology 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Clock Options 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 Divide-By-Two, Divide-By-Four, and Bypass Clock Option (PLL Disabled) 54. . . . . . .

5.6.2 Multiply-By-N Clock Option (PLL Enabled) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 External Memory Interface Timing 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Memory Read 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Memory Write 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Ready Timing For Externally Generated Wait States 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Parallel I/O Interface Timing 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.1 Parallel I/O Port Read 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.2 Parallel I/O Port Write 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Externally Generated Wait States 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.1 I/O Port Read and Write With Externally Generated Wait States 63. . . . . . . . . . . . . . .

5.11 Reset, BIO

, Interrupt, and MP/MC Timings 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 HOLD and HOLDA Timings 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 External Flag (XF) and TOUT Timings 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.14 General-Purpose I/O Timing 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15 Multichannel Buffered Serial Port (McBSP) Timing 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.1 McBSP Transmit and Receive Timings 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.2 McBSP Transmit and Receive Timing Using CLKR/X as a Clock Source Input to

the Sample Rate Generator (SRGR) 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.3 McBSP General-Purpose I/O Timing 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.15.4 McBSP as SPI Master or Slave Timing 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.16 Host-Port Interface Timing 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Mechanical Data 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Ball Grid Array Mechanical Data 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Low Profile Quad Flatpack Mechanical Data 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 1999 – Revised November 2001SPRS098C

Figures

List of Figures

Figure Page

2–1 144-Pin Low-Profile Flatpack Pin Assignments (PGE – Top View) 3. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 144-Ball MicroStar BGA Pin Assignments (GGU – Bottom View) 6. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 TMS320VC5421 Functional Block Diagram 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Memory Map Relative to CPU Subsystems A and B 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 22. . .

3–4 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 23. . . . . . . . . . . . . . . . . . . . . . .

3–5 BSCR Register Bit Layout for Each DSP Subsystem 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Memory Map Relative to Host-Port Interface HPI16 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Interfacing to the HPI-16 in Non-Multiplexed Mode 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 Pin Control Register (PCR) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Multichannel Control Register 2x (MCR2x) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Multichannel Control Register 1x (MCR1x) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Receive Channel Enable Registers Bit Layout for Partitions A to H 30. . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 Transmit Channel Enable Registers Bit Layout for Partitions A to H 30. . . . . . . . . . . . . . . . . . . . . . . . .

3–13 On-Chip Memory Map Relative to DMA (DLAXS/SLAXS = 0) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–14 DMA External Program Memory Map 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–15 Arbitration Between XIO and xDMA for External Access 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 DMA Transfer Mode Control Register (DMMCRn) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–17 DMPREC Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 Chip Subsystem ID Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–19 General-Purpose I/O Control Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 Clock Mode Register (CLKMD) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–21 Bit Layout of the IMR and IFR Registers for Subsystems A and B 48. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 3.3-V Test Load Circuit 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 External Divide-by-Two Clock Timing 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 External Multiply-by-One Clock Timing 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Memory Read (MSTRB = 0) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Memory Write (MSTRB = 0) 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Memory Read With Externally Generated Wait States 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Memory Write With Externally Generated Wait States 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Parallel I/O Port Read (IOSTRB=0) 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Parallel I/O Port Write (IOSTRB=0) 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 I/O Port Read With Externally Generated Wait States 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 I/O Port Write With Externally Generated Wait States 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Reset and BIO Timings 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Interrupt Timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 XIO Timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 HOLD and HOLDA Timings (HM = 1) 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 1999 – Revised November 2001 SPRS098C

vii

Figures

Figure Page

5–16 External Flag (XF) Timing 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–17 Timer (TOUT) Timing 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–18 GPIO Timings 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–19 McBSP Receive Timings 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–20 McBSP Transmit Timings 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–21 McBSP Sample Rate Generator Timings 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–22 McBSP General-Purpose I/O Timings 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–23 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 77. . . . . . . . . . . . . . . . . . . . . . . .

5–24 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 78. . . . . . . . . . . . . . . . . . . . . . . .

5–25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 79. . . . . . . . . . . . . . . . . . . . . . . .

5–26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 80. . . . . . . . . . . . . . . . . . . . . . . .

5–27 Multiplexed Read Timings Using HAS

83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–28 Multiplexed Read Timings With HAS Held High 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–29 Multiplexed Write Timings Using HAS 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–30 Multiplexed Write Timings With HAS Held High 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–31 Nonmultiplexed Read Timings 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–32 Nonmultiplexed Write Timings 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–33 HRDY and HINT Relative to CLKOUT 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–34 SELA/B Timing 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 MicroStar BGA Package 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Low-Profile Quad Flatpack 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

December 1999 – Revised November 2001SPRS098C

Tables

List of Tables

Table Page

2–1 Pin Assignments for the 144-Pin Low-Profile Quad Flatpack 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Terminal Assignments for the 144-Pin MicroStar BGA 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Signal Descriptions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 XIO/ROMEN Modes 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Bootloader Operating Modes 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 XIO/HPI Modes 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Software Wait-State Register (SWWSR) Bit Fields 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Software Wait-State Control Register (SWCR) Bit Fields 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 BSCR Register Bit Functions for Each DSP Subsystem 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Sample Rate Generator Clock Source Selection 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 Receive Channel Enable Registers for Partitions A to H 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Transmit Channel Enable Registers for Partitions A to H 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 DMA Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 DMA Channel Interrupt Selection 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 DMA Global Reload Register Selection 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 Chip Subsystem ID Register Bit Functions 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–14 General-Purpose I/O Control Register Bit Functions 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–15 Clock Mode Register (CLKMD) Bit Functions 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 Multiplier Related to PLLNDIV, PLLDIV, and PLLMUL 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–17 VCO Truth Table 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 VCO Lockup Time 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–19 Processor Memory-Mapped Registers for Each DSP Subsystem 42. . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 Peripheral Memory-Mapped Registers for Each DSP Subsystem 43. . . . . . . . . . . . . . . . . . . . . . . . . .

3–21 McBSP Control Registers and Subaddresses 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–22 DMA Subbank Addressed Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–23 5421 Interrupt Locations and Priorities for Each DSP Subsystem 47. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–24 Bit Functions for IMR and IFR Registers for Each DSP Subsystem 48. . . . . . . . . . . . . . . . . . . . . . . .

5–1 Recommended Operating Conditions 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Electrical Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Thermal Resistance Characteristics 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Divide-By-2 and Divide-by-4 Clock Options Timing Requirements 54. . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics 54. . . . . . . . . . . . . . . . . . . . . . .

5–6 Multiply-By-N Clock Option Timing Requirements 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Multiply-By-N Clock Option Switching Characteristics 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Memory Read Timing Requirements 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Memory Read Switching Characteristics 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Memory Write Switching Characteristics 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Ready Timing Requirements for Externally Generated Wait States 59. . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Parallel I/O Port Read Timing Requirements 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Parallel I/O Port Read Switching Characteristics 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 Parallel I/O Port Write Switching Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 Externally Generated Wait States Timing Requirements 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16 Reset, BIO, Interrupt, and MP/MC Timing Requirements 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 1999 – Revised November 2001 SPRS098C

Tables

Table Page

5–17 HOLD

and HOLDA Timing Requirements 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–18 HOLD and HOLDA Switching Characteristics 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–19 External Flag (XF) and TOUT Switching Characteristics 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–20 General-Purpose I/O Timing Requirements 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–21 General-Purpose I/O Switching Characteristics 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–22 McBSP Transmit and Receive Timing Requirements 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–23 McBSP Transmit and Receive Switching Characteristics 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–24 McBSP Sample Rate Generator Timing Requirements 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–25 McBSP Sample Rate Generator Switching Characteristics 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–26 McBSP General-Purpose I/O Timing Requirements 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–27 McBSP General-Purpose I/O Switching Characteristics 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 77. . . . . . . . . .

5–29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 77. . . . . .

5–30 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 78. . . . . . . . . .

5–31 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 78. . . . . . .

5–32 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 79. . . . . . . . . .

5–33 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 79. . . . . .

5–34 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 80. . . . . . . . . .

5–35 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 80. . . . . . .

5–36 HPI16 Mode Timing Requirements 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–37 HPI16 Mode Switching Characteristics 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 1999 – Revised November 2001SPRS098C

1 TMS320VC5421 Features

Features

 200-MIPS Dual-Core DSP Consisting of Two

Independent Subsystems

 Each Core Has an Advanced Multibus

Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus

 40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core

 Each Core Has a 17-Bit × 17-Bit Parallel

Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/ Accumulate (MAC) Operations

 Each Core Has a Compare, Select, and

Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator

 Each Core Has an Exponent Encoder to

Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

 Each Core Has Two Address Generators

With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

 16-Bit Data Bus With Data Bus Holder

Feature

 512K-Word × 16-Bit Extended Program

Address Space

 Total of 256K-Word × 16-Bit Dual- and

Single-Access On-Chip RAM (128K-Word x 16-Bit Two-Way Shared Memory)

 Single-Instruction Repeat and

Block-Repeat Operations

 Instructions With 32-Bit-Long Word

Operands

 Instructions With Two or Three Operand

Reads

 Fast Return From Interrupts

 Arithmetic Instructions With Parallel Store

and Parallel Load

 Conditional Store Instructions  Output Control of CLKOUT  Output Control of TOUT  Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions

 Dual 1.8-V (Core) and 3.3-V (I/O) Power

Supplies for Low-Power, Fast Operations

 10-ns Single-Cycle Fixed-Point Instruction  Interprocessor Communication via Two

Internal 8-Element FIFOs

 Twelve Channels of Direct Memory Access

(DMA) for Data Transfers With No CPU Loading (Six Channels Per Subsystem With External Access)

 Six Multichannel Buffered Serial Ports

(McBSPs) With 128-Channel Selection Capability (Three McBSPs per Subsystem)

 16-Bit Host-Port Interface (HPI) Multiplexed

With External Memory Interface Pins

 Software-Programmable Phase-Locked

Loop (APLL) Provides Several Clocking Options (Requires External Oscillator)

 On-Chip Scan-Based Emulation Logic,

IEEE Standard 1149-1 Scan Logic



(JTAG) Boundary-

 Two Software-Programmable Timers

(One Per Subsystem)

 Software-Programmable Wait-State

Generator (14 Wait States Maximum)

 Provided in 144-pin MicroStar BGA Ball

Grid Array (GGU Suffix) and 144-pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) Packages

MicroStar BGA is a trademark of Texas Instruments.

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

December 1999 – Revised November 2001 SPRS098C

Introduction

2 Introduction

This section describes the main features, gives a brief functional overview of the TMS320VC5421, lists the pin assignments, and provides a signal description table. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307).

2.1 Description

The TMS320VC5421 fixed-point digital signal processor (DSP) is a dual-core solution running at 200-MIPS performance. The 5421 consists of two DSP subsystems capable of core-to-core communications and a 128K-word zero-wait-state on-chip program memory shared by the two DSP subsystems. Each subsystem consists of one 54x DSP core, 32K-word program/data DARAM, 32K-word data SARAM, 2K-word ROM, three multichannel serial interfaces, xDMA logic, one timer, one APLL, and other miscellaneous circuitry.

The 5421 also contains a host-port interface (HPI) that allows the 5421 to be viewed as a memory-mapped peripheral to a host processor. The 5421 is pin-compatible with the TMS320VC5420.

Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. T wo read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5421 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5421 has 128K words of on-chip program memory that can be shared between the two subsystems.

The 5421 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.

2.2 Migration From the 5420 to the 5421

Customers migrating from the 5420 to the 5421 need to take into account the following:

• The memory structure of the 5421 has been changed to incorporate 128K x 16-bit words of two-way shared memory.

• The DMA of the 5421 has been enhanced to provide access to external, as well as internal memory.

• The HPI and DMA memory maps have been changed to incorporate the new memory 5421.

• 2K x 16-bit words of ROM have been added to the 5421 for bootloading purposes only.

• The VCO pin on the 5420 has been replaced with the HOLDA

added to the 5421 at a previously unused pin location.

• The McBSPs have been updated with a new mode that allows 128-channel selection capability.

• McBSP CLKX/R pins can be used as inputs to internal clock rate generator for CLKS-like function without

the penalty of extra pins.

• The SELA/B pin on 5421 is changed to type I/O/Z for added functionality.

For additional information, see TMS320VC5420 to TMS320VC5421 DSP Migration (literature number SPRA621).

TMS320C54x is a trademark of Texas Instruments.

pin on the 5421 and the HOLD pin was

NOTE:

December 1999 – Revised November 2001SPRS098C

2.3 Pin Assignments

Figure 2–1 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package. Figure 2–2 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2–2 to locate signal names and ball grid numbers.

2.3.1 Pin Assignments for the PGE Package

The TMS320VC5421PGE 144-pin low-profile quad flatpack (LQFP) is footprint- and pin-compatible with the

5420. Table 2–1 lists the pin number and associated signal name for both the multiplexed mode and the nonmultiplexed mode.

Introduction

PPD7

PPA8 PPA0

PPA9

PPD1

A_INT1

A_NMI

IOSTRB

A_GPIO2/BIO

A_GPIO1

A_RS

A_GPIO0

V V

A_BFSR1

A_BDR1

A_BCLKR1

A_BFSX1

A_BDX1

A_BCLKX1

A_XF

A_CLKOUT

HOLDA

TCK

TMS

TDI

TRST

EMU1/OFF

A_INT0

EMU0

TDO

PPD4

PPD0

PPD5

PPD6

A_BFSX2

141

140

A_BDX2

139

138

144

143

142

1 2 3 4 5 6 7 8 9 10 11 12 13 14

16 17 18 19 20 21 22

23 24 25 26 27 28 29 30 31 32 33 34 35 36

373839404142434445464748495051525354555657585960616263646566676869

A_BFSR2

A_BDR2

A_BCLKR2

137

136

135

134

A_BCLKX2

133

132

READY

131DV130

HOLD

CLKIN

129

128

SSA

127

126

125

B_BCLKX2

124

B_BDX2

B_BFSX2

B_BCLKR2

123

122

121

120

119

B_BDR2

PPD2

B_BFSR2

118

117

116

PPD3

PPA1

115

114

PPA5

113

112

PPA6

PPA4

111

110

707172

PPA7

109

108 107 106 105 104 103 102 101 100

PPA14 PPA15 V PPA16 PPA17 B_INT0 B_INT1 B_NMI IS

B_GPIO2/BIO

B_GPIO1

B_GPIO0

B_BFSR1

B_BDR1

B_BCLKR1

B_BFSX1

B_BDX1

B_BCLKX1

TEST

XIO

B_RS

B_XF

B_CLKOUT

HMODE

HPIRS PPA13

78 77

PPA12 V

PPA11

PPA10

MSTRB

A_BDX0

A_BCLKX0

B_BDX0

B_BCLKX0

B_BFSX0

B_BDR0

B_BCLKR0

R/W

PPA2

B_BFSR0

PPA3

PPD8

SELA/B

PPD9

PPD10

PPD11

PPD15

PPD14SSPPD13

PPD12

A_BDR0

A_BFSR0

A_BCLKR0

A_BFSX0

NOTES: A. DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins

and the core CPU.

B. Pin configuration shown for nonmultiplexed mode only. See the pin assignments table for the TMS320VC5421PGE for multiplexed

functions of specific pins and for specific pin numbers.

Figure 2–1. 144-Pin Low-Profile Flatpack Pin Assignments (PGE – Top View)

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–1. Pin Assignments for the 144-Pin Low-Profile Quad Flatpack

SIGNAL NAME

(NONMULTIPLEXED)

SIGNAL NAME

(MULTIPLEXED)

NO.

SIGNAL NAME

(NONMULTIPLEXED)

SIGNAL NAME

(MULTIPLEXED)

PIN NO.

PPD7 HD7 1 PPA8 HA8 2 PPA0 A_HINT/HA0 3 DV

PPA9 HA9 5 PPD1 HD1 6 A_INT1 7 A_NMI 8 IOSTRB A_GPIO3/A_TOUT 9 A_GPIO2/BIO 10 A_GPIO1 11 A_RS 12 A_GPIO0 A_ROMEN 13 V V

15 CV

16 A_BFSR1 17 A_BDR1 18 A_BCLKR1 19 A_BFSX1 20 CV

21 V

22 A_BDX1 23 A_BCLKX1 24 A_XF 25 A_CLKOUT 26 HOLDA 27 TCK 28 TMS 29 TDI 30 TRST 31 EMU1/OFF 32 DV

33 A_INT0 34 EMU0 35 TDO 36 V

PPD14 HD14 39 V

37 PPD15 HD15 38

40 PPD13 HD13 41 PPD12 HD12 42 A_BFSR0 43 A_BDR0 44 A_BCLKR0 45 A_BFSX0 46 V

47 CV

48 A_BDX0 49 A_BCLKX0 50 MSTRB HCS 51 DS HDS2 52 PS HDS1 53 B_BCLKX0 54 B_BDX0 55 DV V

57 B_BFSX0 58

B_BCLKR0 59 B_BDR0 60 CV

61 V

62 B_BFSR0 63 R/W HR/W 64 PPA2 HCNTL1/HA2 65 PPA3 HCNTL0/HA3 66 SELA/B PPA18 67 PPD8 HD8 68 PPD9 HD9 69 PPD10 HD10 70 PPD11 HD11 71 V

72 PPA10 HA10 73 PPA11 HA11 74 DV

75 V

76 PPA12 HA12 77 PPA13 HA13 78 HPIRS 79 HMODE 80 B_CLKOUT 81 B_XF 82 B_RS 83 XIO 84 TEST 85 V

December 1999 – Revised November 2001SPRS098C

Table 2–1. Pin Assignments for the 144-Pin Low-Profile Quad Flatpack (Continued)

Introduction

SIGNAL NAME

(NONMULTIPLEXED)

SIGNAL NAME

(MULTIPLEXED)

NO.

87 B_BCLKX1 88

B_BDX1 89 V

SIGNAL NAME

(NONMULTIPLEXED)

SIGNAL NAME

(MULTIPLEXED)

PIN NO.

90 B_BFSX1 91 B_BCLKR1 92 V

93 CV

94 B_BDR1 95 B_BFSR1 96 B_GPIO0 B_ROMEN 97 B_GPIO1 98 B_GPIO2/BIO 99 IS B_GPIO3/B_TOUT 100 B_NMI 101 B_INT1 102 B_INT0 103 PPA17 HA17 104 PPA16 HA16 105 V

106 PPA15 HA15 107 PPA14 HA14 108 PPA7 HA7 109 PPA6 HA6 110 PPA4 HAS/HA4 111 DV

112 PPA5 HA5 113 PPA1 B_HINT/HA1 114 PPD3 HD3 115 PPD2 HD2 116 B_BFSR2 117 B_BDR2 118 V

119 CV

120 B_BCLKR2 121 B_BFSX2 122 B_BDX2 123 B_BCLKX2 124 V

SSA

CLKIN 129 DV

125 AV

126

127 HOLD 128

130 READY HRDY 131 A_BCLKX2 132 CV

133 V

134 A_BCLKR2 135 A_BDR2 136 A_BFSR2 137 A_BDX2 138 A_BFSX2 139 PPD6 HD6 140 PPD4 HD4 141 PPD5 HD5 142 PPD0 HD0 143 V

144

December 1999 – Revised November 2001 SPRS098C

Introduction

2.3.2 Terminal Assignments for the GGU Package

Table 2–2 lists each ball number and its associated signal name for the TMS320VC5421GGU 144-ball BGA package, which is footprint- and pin-compatible with the 5420.

3456781012 1113 9

A B C D E F G H J K L M N

†

To locate the A1 reference maker, see package top view in Figure 6–1.

Figure 2–2. 144-Ball MicroStar BGA Pin Assignments (GGU – Bottom View)

December 1999 – Revised November 2001SPRS098C

Introduction

Table 2–2. Terminal Assignments for the 144-Pin MicroStar BGA

SIGNAL NAME SIGNAL NAME BALL SIGNAL NAME SIGNAL NAME BALL

(NONMULTIPLEXED) (MULTIPLEXED) NO. (NONMULTIPLEXED) (MULTIPLEXED) NO.

PPD7 HD7 A1 PPA8 HA8 B1 DV

A_RS E1 CV A_BDR1 G1 CV A_XF J1 TMS K1 EMU1/OFF L1 EMU0 M1 V

A_INT1 D2 A_GPIO1 E2 V

TDI K2 DV TDO M2 PPD15 HD15 N2 PPD6 HD6 A3 PPD4 HD4 B3 PPD5 HD5 C3 PPD1 HD1 D3 A_GPIO2/BIO E3 V A_BCLKR1 G3 A_BDX1 H3 HOLDA J3 TRST K3 A_INT0 L3 PPD14 HD14 M3 V

A_BDX2 B4 A_BFSX2 C4 PPA9 HA9 D4 IOSTRB A_GPIO3/A_TOUT E4 A_GPIO0 A_ROMEN F4 A_BFSX1 G4 A_BCLKX1 H4 TCK J4 PPD13 HD13 K4 PPD12 HD12 L4 A_BFSR0 M4 A_BDR0 N4 CV

A_BCLKR2 C5 A_BDR2 D5 A_BCLKR0 K5 A_BFSX0 L5 V

CLKIN A6 DV READY HRDY C6 A_BCLKX2 D6 A_BDX0 K6 A_BCLKX0 L6 MSTRB HCS M6 DS HDS2 N6 AV

SSA

PS HDS1 M7 B_BCLKX0 N7

C1 A_NMI D1

DD DD

N1 PPD0 HD0 A2 B2 PPA0 A_HINT/HA0 C2

F2 A_BFSR1 G2 H2 A_CLKOUT J2

N3 A_BFSR2 A4

A5 V

M5 CV

A7 V

DD DD

N5 B6

B7 C7 HOLD D7 K7 B_BDX0 L7

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–2. Terminal Assignments for the 144-Pin MicroStar BGA (Continued)

SIGNAL NAME BALLSIGNAL NAMESIGNAL NAMEBALLSIGNAL NAME

(NONMULTIPLEXED) NO.(MULTIPLEXED)(NONMULTIPLEXED)NO.(MULTIPLEXED)

B_BCLKX2 A8 B_BDX2 B8 B_BFSX2 C8 B_BCLKR2 D8 B_BDR0 K8 B_BCLKR0 L8 B_BFSX0 M8 V CV

A9 V B_BDR2 C9 B_BFSR2 D9 R/W HR/W K9 B_BFSR0 L9 V

M9 CV PPD2 HD2 A10 PPD3 HD3 B10 PPA1 B_HINT/HA1 C10 PPA5 HA5 D10 IS B_GPIO3/B_TOUT E10 B_BFSR1 F10 B_BCLKR1 G10 TEST H10 B_CLKOUT J10 PPA12 HA12 K10 SELA/B PPA18 L10 PPA3 HCNTL0/HA3 M10 PPA2 HCNTL1/HA2 N10 DV PPA4 HAS/HA4 B11 V B_INT0 D11 B_GPIO2/BIO E11

B_BDR1 F11 B_BFSX1 G11

H11 B_XF J11 PPA13 HA13 K11 PPD10 HD10 L11 PPD9 HD9 M11 PPD8 HD8 N11 PPA6 HA6 A12 PPA14 HA14 B12 PPA16 HA16 C12 B_INT1 D12 B_GPIO1 E12 CV B_BDX1 G12 CV B_RS J12 HPIRS K12 DV

L12 V PPD11 HD11 N12 PPA7 HA7 A13 PPA15 HA15 B13 PPA17 HA17 C13 B_NMI D13 B_GPIO0 B_ROMEN E13 V

F13 V B_BCLKX1 H13 XIO J13 HMODE K13 V

PPA11 HA11 M13 PPA10 HA10 N13

SS SS

DD DD

N8 B9

A11 C11

F12

H12

M12

G13

L13

December 1999 – Revised November 2001SPRS098C

2.4 Signal Descriptions

Table 2–3 lists each signal, function, and operating mode(s) grouped by function. See pin assignments section for exact pin locations based on package type.

Introduction

Table 2–3. Signal Descriptions

PIN NAME TYPE

†

DESCRIPTION

DATA SIGNALS

PPA18 (MSB) PPA17 PPA16 PPA15 PPA14 PPA13 PPA12 PPA11

Parallel port address bus. The DSP can access the external memory locations by way of the external memory interface using PPA[18:0] in external memory interface (EMIF) mode when the XIO pin is logic high. PPA18 is a secondary output function of the SELA/B pin.

The PPA[17:0] pins are also multiplexed with the HPI interface. In HPI mode (XIO pin is low), the external address pins PPA[17:0] are used by a host processor for access to the memory map by way of the on-chip HPI. Refer to the Host-Port Interface (HPI) Signals section of this table for details on the secondary functions of these pins.

These pins are placed into the high-impedance state when OFF

is low.

PPA10 PPA9

I/O/Z PPA8 PPA7 PPA6 PPA5

‡§

PPA4 PPA3 PPA2 PPA1 PPA0 (LSB)

PPD15 (MSB) PPD14

Parallel port data bus. The DSP uses this bidirectional data bus to access external memory when the device is in external memory interface (EMIF) mode (the XIO pin is logic high).

PPD13 PPD12 PPD11

This data bus is also multiplexed with the 16-bit HPI data bus. When in HPI mode, the bus is used to transfer data between the host processor and internal DSP memory via the HPI. Refer to the HPI section of this table for details on the secondary functions of these pins.

PPD10 PPD9 PPD8 PPD7 PPD6

I/O/Z

The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external pullup resistors on unused pins. When the data bus is not being

driven by the 5421, the bus holders keep data pins at the last driven logic level. The data bus keepers are disabled at reset and can be enabled/disabled via the BH bit of the BSCR register.

PPD5 PPD4

These pins are placed into high-impedance state when OFF

is low.

PPD3 PPD2 PPD1 PPD0 (LSB)

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–3. Signal Descriptions (Continued)

PIN NAME DESCRIPTIONTYPE

†

DATA SIGNALS (CONTINUED)

A_INT0 B_INT0 A_INT1 B_INT1

External user interrupts. A_INT0–B_INT0 are prioritized and are maskable by the interrupt mask register (IMR) and the interrupt mode bit. A_INT1

–B_INT1 can be polled and reset by way of the interrupt flag

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

A_NMI B_NMI

A_RS B_RS

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

When NMI

is activated, the processor traps to the appropriate vector location.

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS

program memory. RS

affects various registers and status bits.

is brought to a high level, execution begins at location 0FF80h of

The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low), or as an asynchronous memory interface (EMIF mode when XIO pin is high).

XIO I

NOTE: Because the XIO signal is asynchronous, caution must be taken when changing the state of the

XIO pin to ensure the current cycle is properly ended.

At device reset, the XIO pin level determines the initialization value of the MP/MC bit (a bit in the processor mode status (PMST) register). Refer to the memory section for details.

GENERAL-PURPOSE I/O PINS

A_XF B_XF

A_GPIO0

A_GPIO0 B_GPIO0

A_GPIO1 B_GPIO1

A_GPIO2/BIO B_GPIO2/BIO

O/Z

I/O/Z

External flag output (latched software-programmable output-only signal). Bit-addressable. A_XF and B_XF are placed into the high-impedance state when OFF

A_ROMEN B_ROMEN

General-purpose I/O pins. The secondary function of these pins. In XIO mode, the ROM enable (ROMEN) pins are used to enable the applicable on-chip ROM after

reset.

is low.

General-purpose I/O pins (software-programmable I/O signal). Values can be latched (output) by writing into the GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO register. The GPIO direction is also programmable by way of the DIRn field in the GPIO register.

General-purpose I/O. These pins can be configured like GPIO0–GPIO1; however, as an input, the pins operate as the traditional branch control bit (BIO

). If application code does not perform BIO-conditional

instructions, these pins operate as general inputs.

PRIMARY

A_GPIO3 (A_TOUT) B_GPIO3 (B_TOUT)

I/O/Z

IOSTRB

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

When the device is in HPI mode and HMODE = 0 (multiplexed), these pins act according to the general-purpose I/O control register. TOUT bit must be set to “1” to drive the timer output on the pin. IF TOUT = 0, then these pins are

general-purpose I/Os. In EMIF mode (XIO = 1), these signals are active during I/O space accesses.

December 1999 – Revised November 2001SPRS098C

Table 2–3. Signal Descriptions (Continued)

Introduction

PIN NAME DESCRIPTIONTYPE

‡§

DS IS

‡§

MSTRB

READY I

O/Z

†

MEMORY CONTROL SIGNALS

Program space select signal. The PS signal is asserted during external program space accesses. This pin is placed into the high-impedance state when OFF

is low.

This pin is also multiplexed with the HPI, and functions as the HDS1 data strobe input signal in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin.

Data space select signal. The DS signal is asserted during external data space accesses. This pin is placed into the high-impedance state when OFF

is low.

This pin is also multiplexed with the HPI, and functions as the HDS2 data strobe input signal in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin.

I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed into the high-impedance state when OFF

is low.

This pin is also multiplexed with the general-purpose I/O feature, and functions as the B_GPIO3 (B_TOUT) input/output signal in HPI mode. Refer to the General-Purpose I/O section of this table for details on the secondary function of this pin.

Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance state when OFF

is low.

Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to be completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY again. The processor performs the READY detection if at least two software wait states are programmed.

This pin is also multiplexed with the HPI, and functions as the host-port data ready (output) in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin.

Read/write output signal. R/W indicates transfer direction during communication to an external device. R/W

is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation.

R/W O/Z

This pin is also multiplexed with the HPI, and functions as the host-port read/write input in HPI mode. Refer to the HPI section of this table for details on the secondary function of this pin.

This pin is placed into the high-impedance state when OFF

is low.

I/O space memory strobe. External I/O space is accessible by the CPU and not the direct memory access (DMA) controller. The DMA has its own dedicated I/O space that is not accessible by the CPU.

IOSTRB O/Z

This pin is also multiplexed with the general-purpose I/O feature, and functions as the A_GPIO3 (A_TOUT) signal in HPI mode. Refer to the General Purpose I/O section of this table for details on the secondary function of this pin.

This pin is placed into the high-impedance state when OFF

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

is low.

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–3. Signal Descriptions (Continued)

PIN NAME DESCRIPTIONTYPE

PPA18 O/Z

‡

HOLD

HOLDA O/Z

A_CLKOUT B_CLKOUT

CLKIN

A_BCLKR0 B_BCLKR0 A_BCLKR1 B_BCLKR1 A_BCLKR2 B_BCLKR2

A_BCLKX0 B_BCLKX0 A_BCLKX1 B_BCLKX1 A_BCLKX2 B_BCLKX2

‡§ ‡§ ‡§ ‡§ ‡§ ‡§

O/Z

I/O/Z

†

MEMORY CONTROL SIGNALS (CONTINUED)

PRIMARY

For HPI access (XIO=0), SELA/B is an input. See T able 3–3 for a truth table of SELA/B, HMODE, and XIO pins and functionality.

SELA/B I

For external memory accesses (XIO=1), SELA/B is multiplexed as output PPA18. See the PPA signal descriptions. These pins are placed into the high-impedance

state when OFF

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged,

these lines go into the high-impedance state.

is low.

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external circuitry. HOLDA

also goes into the high-impedance state when OFF is low.

CLOCKING SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOFF bit of the PMST register. CLKOUT goes into the high-impedance state when EMU1/OFF is low.

I Input clock to the device. CLKIN connects to an oscillator circuit/device (PLL).

MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS

Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver . Input from an external clock source for clocking data into the McBSP. When not being used as a clock, these pins can be used as general-purpose I/O by setting RIOEN = 1.

BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register. These pins are placed into the high-impedance state when OFF

is low.

Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be configured as an input by setting the CLKXM = 0 in the PCR register. BCLKX can be sampled as an input by way of the IN1 bit in the SPC register. When not being used as a clock, these pins can be used as general-purpose I/O by setting XIOEN = 1.

These pins are placed into the high-impedance state when OFF

is low.

A_BDR0 B_BDR0 A_BDR1 B_BDR1

Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can be used

as general-purpose I/O by setting RIOEN = 1.

A_BDR2 B_BDR2

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

December 1999 – Revised November 2001SPRS098C

Table 2–3. Signal Descriptions (Continued)

Introduction

PIN NAME DESCRIPTIONTYPE

MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS (CONTINUED)

A_BDX0 B_BDX0 A_BDX1 B_BDX1 A_BDX2 B_BDX2

A_BFSR0 B_BFSR0 A_BFSR1 B_BFSR1

I/O/Z A_BFSR2

B_BFSR2 A_BFSX0

B_BFSX0 A_BFSX1 B_BFSX1

I/O/Z A_BFSX2

B_BFSX2

HA[17:0] I

O/Z

†

Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins can be used as general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF

is low.

Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the receive-data process over the BDR pin. When not being used as data-receive synchronization pins, these pins can be used as general-purpose I/O by setting RIOEN = 1. These pins are placed into the high-impedance state when OFF

is low.

Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the transmit-data process over the BDX pin. If RS

is asserted when BFSX is configured as output, then BFSX is turned into input mode by the reset operation. When not being used as data-transmit synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF

is low.

HOST-PORT INTERFACE (HPI) SIGNALS

PRIMARY

These pins ar e m ultiplexed with the external interface pins and are used by the HPI when the subsystem is in HPI mode (XIO = 0, MP/MC = 0).

PPA[17:0] O/Z

See the PPA signal descriptions. These pins are placed into the high-impedance state when OFF

is low.

NOTE: HA4 has a pullup and a Schmitt trigger buffer.

PRIMARY

Parallel bidirectional data bus. These pins are multiplexed with the external interface pins and are used as an HPI interface when XIO = 0.

These pins include bus holders to reduce power dissipation caused by floating, unused inputs. The bus holders also eliminate the need for external pullup resistors

HD[15:0] I/O/Z

PPD[15:0] I/O/Z

on unused inputs. In multiplexed address/data mode (HMODE = 0), when the data bus is not being driven by the 5421, the bus holders keep the multiplexed address inputs on these pins at the last logic level driven by the host. The data bus holders are disabled at reset and can be enabled/disabled via the BH bit of the BSCR register.

See the PPD signal descriptions. These pins are placed into the high-impedance state when OFF

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

is low.

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–3. Signal Descriptions (Continued)

PIN NAME DESCRIPTIONTYPE

†

HOST-PORT INTERFACE (HPI) SIGNALS (CONTINUED)

HPI control inputs. Use PPA3 and PP A2 for the HCNTL0 and HCNTL1 values during the HPI HPIC, HPIA, and HPID reads/writes. Only used in multiplexed address/data

HCNTL0 HCNTL1

PPA3 PPA2

mode (HMODE = 0).

O/Z

These pins are shared with the external memory interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low). These pins are placed into the high-impedance state when OFF

is low.

Address strobe input. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. This signal is only used in HPI multiplexed

HAS

‡§

I PPA4

‡§

address/data mode (HMODE pin is low).

O/Z

This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). This pin is placed into the high-impedance state when OFF

is low.

HPI chip-select signal. This signal must be active during HPI transfers, and can remain active between concurrent transfers.

HCS

‡§

I MSTRB

‡§

O/Z

This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). This pin is placed into the high-impedance state when OFF

is low.

HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes

HDS1 HDS2

‡§ ‡§

to control HPI transfers. These pins are shared with the external memory interface and are only used by the

O/Z

HPI when the interface is in HPI mode (XIO pin is low). These pins are placed into the high-impedance state when OFF HPI read/write signal. This signal is used by the host to control the direction of an

HPI transfer.

HR/W I R/W O/Z

This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low).

This pin is placed into the high-impedance state when OFF HPI data-ready output. The ready output informs the host when the HPI is ready for

the next transfer.

HRDY O/Z READY I

This pin is shared with the external memory interface and is only used by the HPI when the interface is in HPI mode (XIO pin is low). HRDY is placed into the high-impedance state when OFF

is low.

PRIMARY

A_HINT B_HINT

O/Z

PPA0 PPA1

Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this interrupt by writing a “1” to the HINT

O/Z

HPI multiplexed address/data mode (HMODE pin is low). These pins are placed into

bit of the HPIC register. Only supported in

the high-impedance state when OFF is low.

HPIRS

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

I Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.

is low.

December 1999 – Revised November 2001SPRS098C

Table 2–3. Signal Descriptions (Continued)

Introduction

PIN NAME DESCRIPTIONTYPE

†

HOST-PORT INTERFACE (HPI) SIGNALS (CONTINUED)

Host mode select. When this pin is low, it selects the HPI multiplexed address/data mode. The multiplexed address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC, HPIA, and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.

HMODE I

When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with separate address/data buses to access the HPI address range by way of the 18-bit address bus and the HPI data (HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.

SUPPLY PINS

AV CV DV V

DD DD

SSA

S Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD. S Dedicated “clean” power supply that powers the core CPUs. CVDD = 1.8 V S Dedicated “dirty” power supply that powers the I/O pins. DVDD = 3.3 V S Digital ground. Dedicated ground plane for the device.

Analog ground. Dedicated ground for the PLL. V

are not separated.

can be connected to VSS if digital and analog grounds

SSA

TEST PIN

TEST

No connection

EMULATION/TEST PINS

Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the

TCK

‡§

test access port (T AP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,

or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

TDI

‡

Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or

data) on a rising edge of TCK. Test data output. The contents of the selected register is shifted out of TDO on the falling edge of TCK.

TDO O/Z

‡

TMS

TRST

TDO is in high-impedance state except when the scanning of data is in progress. These pins are placed into high-impedance state when OFF

Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller

on the rising edge of TCK.

is low.

Test reset. When high, TRST gives the scan system control of the operations of the device. If TRST is driven low, the device operates in its functional mode and the IEEE 1149.1 signals are ignored. Pin with

internal pulldown device.

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

December 1999 – Revised November 2001 SPRS098C

Introduction

Table 2–3. Signal Descriptions (Continued)

PIN NAME DESCRIPTIONTYPE

†

EMULATION/TEST PINS (CONTINUED)

Emulator interrupt 0 pin. When TRST is driven low , EMU0 must be high for the activation of the EMU1/OFF

EMU0 I/O/Z

condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O.

Emulator interrupt 1 pin. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as I/O. When TRST

. EMU/OFF = 0 puts all output drivers into the high-impedance state.

OFF

EMU1/OFF I/O/Z

Note that OFF applications). Therefore, for the OFF

= 0, EMU0 = 1, EMU1 = 0

TRST

†

I = Input, O = Output, S = Supply, Z = High Impedance

‡

This pin has an internal pullup resistor.

These pins are Schmitt triggered inputs.

This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

This pin is used by Texas Instruments for device testing and should be left unconnected.

This pin has an internal pulldown resistor.

is used exclusively for testing and emulation purposes (and not for multiprocessing

condition, the following conditions apply:

transitions from high to low, then EMU1 operates as

December 1999 – Revised November 2001SPRS098C

3 Functional Overview

Functional Overview

P, C, D, E Buses and Control Signals

DSP Subsystem A

XIO

16HPI

16 HPI

Arbitrator

Cbus

Dbus

Pbus

54X cLEAD

(Core A)

Arbitrator

Interprocessor

Ebus

TI BUS

IRQs

Cbus

Dbus

Ebus

32K RAM

Single Access

Data

RHEA

logic

RHEA Bus

Cycle

Arrangmnt

RHEAbus

Bridge

P bus

xDMA

128K Dual

Access

PRAM

P, C, D, E Buses and Control Signals

Cbus

Dbus

Pbus

32K RAM

Dual Access

Program/Data

MBus

RHEA bus

MBus

Core-to-Core

FIFO Interface

MBus

Ebus

MBusMBus

Clocks

Pbus

2K Program

ROM

GPIO

McBSP1

McBSP2

McBSP3

TIMER

APLL

JTAG

16 HPI

DSP Subsystem B

Pbus

54X cLEAD

Arbitrator

(Core B)

Ebus

Cbus

Dbus

TI Bus

Host Access Bus

Cbus

Dbus

32K RAM

Single Access

Data

Ebus

RHEA

Bridge

xDMA Logic

Pbus

Cbus

Dbus

32K RAM

Dual Access

Program/Data

MBus

RHEA Bus

MBus

Ebus

RHEA bus

MBus

Pbus

Program ROM

GPIO

McBSP1

McBSP2

McBSP3

TIMER

JTAG

Figure 3–1. TMS320VC5421 Functional Block Diagram

December 1999 – Revised November 2001 SPRS098C

Functional Overview

3.1 Memory

Each 5421 DSP subsystem maintains the peripheral register memory map and interrupt location/priorities of the standard 5420. Figure 3–2 shows the size of the required memory blocks and their link map within the program and data space of the cLEAD core. The total on-chip memory for the 5421 devices is 256K-word data/program.

DataHex Program Page 0Hex

00 0000

00 005F 00 0060

00 7FFF

00 8000

00 FFFF

†

ROM enabled after reset.

‡

When CPU PMST register bit MP/MC=0 and an address is generated outside the on-chip memory bound or the address reach, i.e.,

Memory-

Mapped

Registers

On-Chip

DARAM A/B

(32K Words)

Prog/Data

On-Chip SARAM A/B (32K Words)

Data Only (DROM=1)

External

(DROM=0)

00 0000

00 005F

00 0060

00 7FFF

00 8000

00 DFFF

00 E000 00 F7FF

00 F800

00 FFFF

Reserved

On-Chip

DARAM A/B

(32K Words)

Prog/Data (OVLY=1)

External

(OVLY=0)

On-Chip two-way

shared

DARAM 0

(24K Words)

Prog Only

Shared 0

Reserved

ROM

(ROMEN=1)

01 0000

01 005F 01 0060

01 7FFF

01 8000

†

01 FFFF

XPC > 3h, access is always external, if XIO = 1. Pages 8–127 are mapped over pages 4–7. When XIO = 1 and MP/MC 1, 2, and 3 are external. Pages 4–127 are mapped over pages 0–3.

On-chip DARAM A and SARAM A are for subsystem A. Likewise, on-chip DARAM B and SARAM B are for subsystem B.

On-chip DRAM 0 and DRAM 1 are owned by subsystem A and shared with subsystem B.

On-chip DRAM 2 and DRAM 3 are owned by subsystem B and shared with subsystem A.

Program Page 1Hex

Reserved

On-Chip

Prog/Data

(OVLY=1)

External

(OVLY=0)

On-Chip two-way

shared

Prog Only

Shared 1

02 FFFF

DARAM A/B

(32K Words)

DARAM 1

(32K Words)

(extended) (extended)

02 0000

02 005F 02 0060

02 7FFF

02 8000

Program Page 2Hex

Reserved

On-Chip

DARAM A/B

(32K Words)

Prog/Data

(OVLY=1)

External

(OVLY=0)

On-Chip two-way

shared

DARAM 2

(32K Words)

Prog Only

Shared 2

Program Page 3Hex

03 0000

Reserved

03 005F 03 0060

03 7FFF

03 8000

03 FFFF

On-Chip

DARAM A/B

(32K Words)

Prog/Data

(OVLY=1)

External

(OVLY=0)

On-Chip two-way

shared

DARAM 3

(32K Words)

Prog Only

Shared 3

(extended)

0n 0000

0n 005F 0n 0060

0n 7FFF

0n 8000

0n FFFF

Program Page nHex

Reserved

External

(n = 4 – 127)

= 1, program pages 0,

NOTES: A. Clearing the ROMEN bit (GPIO[7]) enables an 8K-word block (0E000h – 0FFFFh) of DARAM .

B. All external accesses require the XIO pin to be high. C. CPU I/O space is a single page of 64K words. Access is always external. D. All internal memory is divided into 8K blocks.

‡

Figure 3–2. Memory Map Relative to CPU Subsystems A and B

3.1.1 On-Chip Dual-Access RAM (DARAM)

The 5421 subsystems A and B each have 32K 16-bit words of on-chip DARAM (4 blocks of 8K words). Each of these DARAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory space. The DARAM can be mapped into program/data memory space by setting the OVLY bit in the processor-mode status (PMST) register of the 54x CPU in each DSP subsystem.

December 1999 – Revised November 2001SPRS098C

3.1.2 On-Chip Single-Access RAM (SARAM)

The 5421 subsystems A and B each have 32K 16-bit words of on-chip SARAM (4 blocks of 8K words). Each of these SARAM blocks can be accessed once per machine cycle. This memory is intended to store data values only. At reset, the SARAM is disabled. The SARAM can be enabled in data memory space by setting the DROM bit in the PMST register.

3.1.3 On-Chip Two-Way Shared RAM (DARAM)

The 5421 has 128K 16-bit words of on-chip DARAM (16 blocks of 8K words) that is shared between the two DSP subsystems. This memory is intended to store program only. Each subsystem is able to make one instruction fetch from any location in two-way shared memory each cycle. Neither subsystem CPU can write to the two-way shared memory as only the DMA can write to two-way shared memory.

3.1.4 On-Chip Boot ROM

The 5421 subsystems A and B each have 2K 16-bit words of on-chip ROM. This ROM is used for bootloading functions only. Enabling the ROM maps out one 8K-word block of the shared program memory . The ROM can be disabled by clearing bit 7 (ROMEN) of the general-purpose I/O (GPIO) register. Table 3–1 shows the XIO/ROMEN modes. The ROM is enabled or disabled at reset for each subsystem depending on the state of the GPIO0 pin for that subsystem.

Table 3–1. XIO/ROMEN Modes

XIO ROMEN/GPIO0 MODE

0 x Fetch internal from RAM 1 0 Fetch external 1 1 ROM enabled

Functional Overview

3.1.5 Extended Program Memory

The program memory space on the 5421 device addresses up to 512K 16-bit words. The 5421 device uses a paged extended memory scheme in program space to allow access of up to 512K of program memory . This extended program memory (each subsystem) is organized into eight pages (0–7), pages 0–3 are internal, pages 4–7 are external, each 64K in length. (Pages 8–127 as defined by the program counter extension register (XPC) are aliases for pages 4–7.) Access to the extended program memory is similar to the 5420. To implement the extended program memory scheme, the 5421 device includes the following feature:

• Two 54x instructions are extended to use the additional two bits in the 5421 device.

– READA – Read program memory addressed by accumulator A and store in data memory – WRITA – Write data to program memory addressed by accumulator A

(Writes not allowed for CPUs to shared program memory)

December 1999 – Revised November 2001 SPRS098C

Functional Overview

3.1.6 Program Memory

The program memory is accessible on multiple pages, depending on the XPC value. Within these pages, memory is accessible, depending on the address range.

• Access in the lower 32K of each page is dependent on the state of OVLY.

– OVLY = 0 – Program memory is accessed externally for all values of XPC. – OVLY = 1 – Program memory is accessed from local data/program DARAM for all values of XPC.

• Access in the upper 32K of each page is dependent on the state of MP/MC

– MP/MC

= 0 – Program memory is accessed internally from two-way shared DARAM for XPC = 0–3.

Program memory is accessed externally for XPC = 4–127.

– MP/MC

= 1 – Program memory is accessed externally for all values of XPC.

3.1.7 Data Memory

The data memory space is a single page of 64K. Access is dependent on the address range. Access in the lower 32K of data memory is always from local DARAM.

Access in the upper 32K of data memory is dependent on the state of DROM.

• DROM = 0 – Data memory is accessed externally

• DROM = 1 – Data memory is accessed internally from local SARAM

3.1.8 I/O Memory

The I/O space is a single page of 64K. Access is always external.

and the value of XPC.

When XIO = 0 and an access to external memory is attempted, any write is ignored and any read is an unknown value.

3.2 Multicore Reset Signals

The 5421 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the CPU registers and upon release, initiate the reset function. Additionally, the A_RS PLL and initializes the CLKMD register to bypass mode.

The HPI reset signal (HPIRS

) places the HPI peripheral into a reset state. It is necessary to wait three clock cycles after the rising edge of HPIRS by turning off the PLL and initializing the CLKMD register to bypass mode.

3.3 Bootloader

The on-chip bootloader is used to automatically transfer user code from an external source to anywhere in program memory after reset. The XIO pin is sampled during a hardware reset and the results indicate the operating mode as shown in Table 3–2.

Table 3–2. Bootloader Operating Modes

XIO AFTER RESET

HPI mode, bootload is controlled by host. The external host holds the 5421 in reset while it loads the on-chip memory of one or both subsystems as determined by the SELA/B pin.

The host can release the 5421 from reset by either of the following methods:

1. If the A_RS

1 XIO mode. ROM is mapped in, if ROMEN pin = 1 during reset.

be controlled by the A_RS high to release the cores from reset.

2. If the A_RS until a HPI data write to address 0x2F occurs. This means the host can download code to subsystem A and then release core A from reset by writing any data to core A address 0x2F via the HPI. The host can then repeat the sequence for core B. This mode allows the host to control the 5421 reset without additional hardware.

signal resets the on-chip

before performing an HPI access. The HPIRS signal also resets the PLL

/B_RS pins are held low while HPIRS transitions from low to high, the subsystem cores reset will

/B_RS pins. When the host has finished downloading code, it drives A_RS/B_RS

/B_RS pins are held high while HPIRS transitions from low to high, the subsystems stay in reset

December 1999 – Revised November 2001SPRS098C

The 5421 bootloader provides the following options for the source of code to download:

• Parallel from 8-bit or 16-bit-wide EPROM

• Serial boot from McBSPs, 8-bit mode

GPIO register bit 7 (ROMEN) is used to enable/disable the ROM after reset. The ROMEN bit reflects the status of the ROMEN/GPIO0 pin for each core. ROMEN = 1 indicates that the ROM and the 8K-word program memory block (00 E000h–00 FFFFh) are not available for a CPU write. When ROMEN = 0, this 8K-word program memory is available and the ROM is disabled.

A combination of interrupt flags and the bit values of an external memory location determine the selection of the various boot options.

3.4 External Interface (XIO)

The external interface (XIO) supports the 5421 master boot modes and other external accesses. Its features include:

• Multiplexed with the HPI pins

• Selection of XIO or HPI mode is determined by a dedicated pin (XIO)

• Provides 512K words of external program space, 64K words of external data space, and 64K words of

external I/O space.

• Different boot modes are selectable by the XIO, HMODE, and A_RS

• After reset, the control register bit ROMEN is always preset to 1.

Functional Overview

/B_RS pins.

While XIO = 0 during reset, host HPI mode is on, the host sees all RAM, and ROM is disabled. A host write to 002Fh releases the CPUs from reset; the 002Fh write by the host clears the ROMEN bit in the GPIO register.

While XIO = 1 and ROMEN = 1 during reset, the CPU starts from ROM (0FF80h) to do boot selection. After branching to non-ROM area, the code changes the ROMEN bit to enable the RAM area occupied by ROM. While XIO = 1 and ROMEN = 0 during reset, the CPU starts from external (0FF80h) to do boot selection.

Table 3–3 provides a complete description of HMODE, SELA/B, and XIO pin functionality.

HMODE SELA/B HPI MODES (XIO = 0) XIO MODES (XIO = 1)

0 0 HPI muxed address/data subsystem A slave to host SELA/B pin is multiplexed as PPA18 output. 0 1

1 0 1 1

HPI muxed address/data subsystem B slave to host HPI non-muxed address/data subsystem A slave to host HPI non-muxed address/data subsystem B slave to host

3.5 On-Chip Peripherals

All the 54x devices have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. The on-chip peripheral options provided are:

• Software-programmable wait-state generator

• Programmable bank-switching

• Parallel I/O ports

• Multichannel buffered serial ports (McBSPs)

• A hardware timer

• A software-programmable clock generator using a phase-locked loop (PLL)

Table 3–3. XIO/HPI Modes

SELA/B pin is multiplexed as PPA18 output. SELA/B pin is multiplexed as PPA18 output. SELA/B pin is multiplexed as PPA18 output.

December 1999 – Revised November 2001 SPRS098C

+ 68 hidden pages

TEXAS INSTRUMENTS TMS320VC5421 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

IMPORTANT NOTICE

REVISION HISTORY

Contents

List of Figures

List of Tables

1 TMS320VC5421 Features

Introduction

2.1 Description

2.2 Migration From the 5420 to the 5421

2.3 Pin Assignments

2.4 Signal Descriptions

Functional Overview

3.1 Memory

3.2 Multicore Reset Signals

3.3 Bootloader

3.4 External Interface (XIO)

3.5 On-Chip Peripherals