Texas Instruments TMS320TCI6487 Datasheet

TMS320TCI6487 DSP Platform

Technology for Innovators

TM

Product Bulletin

Key Benefits

• Multi-standard SOC platform

•• SOC baseband solution for

TD-SCDMA, WiMAX,
cdma2000 and UMTS Tx

• Scalable platform

•• Modular design is ideal for

pico, micro and macro BTS

• Quick time to market

•• Software-programmable

solutions with the reuse of
existing software leads to a
shorter development cycle

• Cost optimization

•• Functional integration leads to

lower system cost and
eliminates the need for
accelerator ASICs

flexibility, the 3 Mbytes of L2
SRAM/cache can be configured in
multiple ways, such as 1/1/1 Mbytes
or 1.5/1/0.5 Mbytes, among the three
DSP cores. To support wireless

Figure 1. TCI6487 DSP Block Diagram

TCI6487 DSP Architecture

The TCI6487 high-performance DSP
has three independent DSP subsys­tems. At the heart of each subsystem
is a 1.0-GHz C64x+ DSP core. For

The TMS320TCI6487 (TCI6487) device is a very high-performance DSP
designed specifically for wireless infrastructure baseband applications. With
a high level of functional integration and a high channel density supported on
a single device, the TCI6487 DSP offers a modular and scalable design with
a small footprint. The TCI6487 DSP is therefore an ideal solution for pico,
micro and macro BTS and enables an SOC baseband solution for UMTS, TD­SCDMA, WiMAX and cdma2000 applications. OEMs can accelerate their
channel card development with the use of the TCI6487 DSP, since it offers a
software-programmable solution and allows for the reuse of existing C64x

TM

and C64x+TMDSP code. Advanced features such as MIMO, beamforming
and Parallel Interface Cancellation (PIC) can be easily supported without
the need for any hardware redesign.

GPIO

PLL

IC

2

Timers Others

Boot
ROM

McBSP

Antenna
Interface

EDMA 3.0 with Switch Fabric

DDR2

IF

C64x+

Core

TM

C64x+

Core

C64x+

Core

L1 Data L1 Data L1 Data

L1 Prog L1 Prog L1 Prog

L2 Memory L2 MemoryL2 Memory

RSA RSA RSA

10/100/1000

Ethernet

Serial

RapidIO

VCP2

TCP2

CPRI

Common Public Radio Interface

applications, the DSP contains a
number of specialized coprocessors:

• Viterbi Decoder Coprocessor
(VCP2)

• Turbo Code Decoder Coprocessor
(TCP2)

• Rake Search/Spread Accelerator
(RSA)

The RSA is a tightly coupled
coprocessor that can be used to
accelerate CDMA chip-rate process­ing. Another important feature of
the device is its support of standard
interfaces such as serial RapidIO
(SRIO), Gigabit Ethernet, DDR2
and McBSP. The TCI6487 also
supports the OBSAI and CPRI
antenna interfaces, with up to six
configurable links at a maximum
rate of 3.072 Gbps (OBSAI) and

2.4576 Gbps (CPRI).

The EDMA 3.0 switch-fabric
engine supports high-bandwidth,
low-latency internal communications.
The EDMA manages communica­tions between peripherals, memories,
accelerators and DSP cores.

Interfaces

TCI6487 supports standard antenna,
network, device and interdevice
communication interfaces as well as
a high-speed interface to communi­cate with external memory:

Antenna Interface

Six configurable (full-duplex) links
in either OBSAI or CPRI modes that
can support a variety of data rates.
Supports OBSAI/CPRI daisy chain­ing between DSPs.

• OBSAI—614.4-Mbps, 1.2288-Gbps,

2.4576-Gbps link rates supported

• CPRI—768-Mbps, 1.536-Gbps,

3.072-Gbps link rates supported

Key Features

• 3.0 GHz of total raw DSP
processing power

• A total of 3 Mbytes of total on-chip
L2 SRAM/cache

• Standard C64x+TMDSP core

•• Enables reuse of existing DSP

software

• RSA on all three DSP cores

•• Enables high-performance

transmit chip-rate processing

•• Enables high-performance RACH

preamble detection solution

• Industry-leading 65-nm silicon
technology

•• Enables a high level of functional

integration on a single device

•• Enables a high-channel-density

solution

• Software-programmable resources

•• Enables the reuse of MIPS and

memory resources on the DSP for
various types of functionality

• Standard interfaces

•• SGMII Gigabit Ethernet, DDR2,

two serial RapidIO (SRIO) links,
McBSP, I2C, GPIO

• Debug interface

•• EMU/trace

• Antenna interfaces

•• OBSAI and CPRI standards-

compliant antenna interface

Advanced Features
Supported/Enabled

•MIMO

• Fixed and adaptive beamforming
(on both uplink and downlink)

• Parallel interference cancellation

Network Interface

• 10/100/1000 Ethernet (SGMII)

Interdevice Communication

• SRIO—Two 1x lanes at a rate of

1.25, 2.5 or 3.125 Gbps each

• SRIO daisy chain capability
between TCI6487 DSPs

•• Multiple TCI6487 DSPs on a

card can be interconnected via
an SRIO daisy chain

•• Hardware packet-forwarding

mechanism supports passing
data through the daisy chain to
a specific TCI6487 DSP

• McBSP—Two McBSP links, each
at 100 Mbps

• McBSP can be used for multi­channel clocked serial
communications

•I

2

C—One I2C link at 400 kbps

•I

2

C can be used for communica­tion links between integrated
circuits or for peripheral devices
on an embedded system

Memory Interface

• DDR2-400 to DDR2-667 support

TCI6487 DSP Applications

The TCI6487 DSP offers a very high­density “all-DSP” SOC baseband
solution that is easily scalable for pico,
micro and macro BTS applications for
multiple standards.

General Characteristics

• Supports pico to macro via the
TCI6487 scalable architecture

• Supports various radio topologies
including:

••

TD-SCDMA, WiMAX, cdma2000
and UMTS Tx

•• ASIC-plus-DSP implementations

for UMTS

• Code compatible with C64x and
C64x+ platforms

TD-SCDMA Solution

• Support for TD-SCDMA chip rate and
symbol rate (baseband on chip)

• Up to 3 carriers/69 users with SCJD
per device

• Up to 2 carriers with MCJD per
device

WiMAX (802.16e) Solution

• Supports implementation of
software-based (Tx/Rx) modems

• 3 sectors (5 MHz) or 1 sector (10 MHz)
per device

GSM Solution

• High-density BTS baseband on a chip

• 10 EDGE-enabled carriers (all soft)

cdma2000 Solution

• Complete baseband on a chip

• 144 users (macro)

UMTS Macro BTS—Tx Only

• 92 users per device (voice)

• Includes softer handover

Other UMTS Capabilities

• High-density RACH solution

•• 6-antenna RACH preamble

detection and 3-sector, 20-km or
6-sector, 10-km PD

• HSUPA (E-DCH)

•• 1 sector of E-DCH

• HSDPA (3 sectors)

••

Symbol rate and MAC-HS