TEXAS INSTRUMENTS TMS320R2811, TMS320R2812 Technical data

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TMS320R2811, TMS320R2812

Digital Signal Processors

Data Manual

Literature Number: SPRS257C

June 2004 − Revised June 2006

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Copyright © 2006, Texas Instruments Incorporated

Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS257B
device-specific data sheet to make it an SPRS257C revision.

PAGE

NO.

23−24 Modified description of EMU0 and EMU1 in Table 2−2

100 Modified note under Table 6−9
100 Modified note under Table 6−10 and changed values from MIN to MAX
100 Moved values from MIN to MAX in Table 6−12
101 Moved values from MIN to MAX in Table 6−14

ADDITIONS/CHANGES/DELETIONS

13 Changed Temperature Options bullet in Features list
15 Added a separate row to Table 2−1 Hardware Features to modify Q temperature options
20 Modified symbol (§) note in Table 2−2
23 Modified Note in description of TRST in Table 2−2

31 Modified memory map in Figure 3−2
32 Modified memory map in Figure 3−3
87 Added the ZHH package to the Absolute Maximum Ratings table (6.1)
88 Added X1 to XCLKIN in the Recommended Operating Conditions table (6.2)
93 Modified XCLKIN values in Table 6−3

102 Modified note C in Figure 6−13
103 Modified the last symbol note (
109 Modified note in Figure 6−22

111 Modified note in Figure 6−23
105 Modified note on Table 6−19
105 Modified note on Table 6−20

113 Modified note on Figure 6−24
127 Deleted last sentence in the fifth paragraph under section 6.27 XHOLD and XHOLDA
131 Modified gain error and internal voltage reference values in Table 6−41

||)

in Table 6−16

June 2004 − Revised June 2006 SPRS257C

3

Revision History

This page intentionally left blank.

4

June 2004 − Revised June 2006SPRS257C

Contents

Contents

Section Page

1 Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Description 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Device Summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Pin Assignments 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Terminal Assignments for the GHH and ZHH Packages 16. . . . . . . . . . . . . . . . . . .

2.3.2 Pin Assignments for the PGF Package 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Pin Assignments for the PBK Package 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Signal Descriptions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Overview 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Memory Map 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Brief Descriptions 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 C28x CPU 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Memory Bus (Harvard Bus Architecture) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Peripheral Bus 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Real-Time JTAG and Analysis 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 External Interface (XINTF) (2812 Only) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 M0, M1 SARAMs 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 L0, L1, L2, L3, H0 SARAMs 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 Boot ROM 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 Security 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.10 Peripheral Interrupt Expansion (PIE) Block 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 External Interrupts (XINT1, 2, 13, XNMI) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.12 Oscillator and PLL 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.13 Watchdog 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.14 Peripheral Clocking 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.15 Low-Power Modes 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.16 Peripheral Frames 0, 1, 2 (PFn) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer 37. . . . . . . . . . . . . . . . . . . . . . . .

3.2.18 32-Bit CPU-Timers (0, 1, 2) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.19 Control Peripherals 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.20 Serial Port Peripherals 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Register Map 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Device Emulation Registers 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 External Interface, XINTF (2812 Only) 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Timing Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 XREVISION Register 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Interrupts 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 External Interrupts 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 System Control 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 OSC and PLL Block 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.2 Loss of Input Clock 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 PLL-Based Clock Module 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.4 External Reference Oscillator Clock Option 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.5 Watchdog Block 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.6 Low-Power Modes Block 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Peripherals 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 32-Bit CPU-Timers 0/1/2 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

June 2004 − Revised June 2006 SPRS257C

5

Contents

4.2 Event Manager Modules (EVA, EVB) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 General-Purpose (GP) Timers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Full-Compare Units 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Programmable Deadband Generator 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4 PWM Waveform Generation 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5 Double Update PWM Mode 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.6 PWM Characteristics 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.7 Capture Unit 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.9 External ADC Start-of-Conversion 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Enhanced Analog-to-Digital Converter (ADC) Module 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Enhanced Controller Area Network (eCAN) Module 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Multichannel Buffered Serial Port (McBSP) Module 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Serial Communications Interface (SCI) Module 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Serial Peripheral Interface (SPI) Module 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 GPIO MUX 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Development Support 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Device and Development Support Tool Nomenclature 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Documentation Support 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Electrical Specifications 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Absolute Maximum Ratings 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Recommended Operating Conditions† 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Electrical Characteristics Over Recommended Operating Conditions

(Unless Otherwise Noted) 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions

During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x) 89. . . . . . . . . . . . . . . . . .

6.5 Current Consumption Graphs 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 Reducing Current Consumption 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Power Sequencing Requirements 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Signal Transition Levels 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Timing Parameter Symbology 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 General Notes on Timing Parameters 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11 Test Load Circuit 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12 Device Clock Table 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13 Clock Requirements and Characteristics 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.1 Input Clock Requirements 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.2 Output Clock Characteristics 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.14 Reset Timing 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15 Low-Power Mode Wakeup Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16 Event Manager Interface 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.1 PWM Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.2 Interrupt Timing 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.17 General-Purpose Input/Output (GPIO) − Output Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.18 General-Purpose Input/Output (GPIO) − Input Timing 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.19 SPI Master Mode Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.20 SPI Slave Mode Timing 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.21 External Interface (XINTF) Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.22 XINTF Signal Alignment to XCLKOUT 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.23 External Interface Read Timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.24 External Interface Write Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

June 2004 − Revised June 2006SPRS257C

Contents

6.25 External Interface Ready-on-Read Timing With One External Wait State 121. . . . . . . . . . . . . . . .

6.26 External Interface Ready-on-Write Timing With One External Wait State 124. . . . . . . . . . . . . . . .

6.27 XHOLD

and XHOLDA 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.28 XHOLD/XHOLDA Timing 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29 On-Chip Analog-to-Digital Converter 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.1 ADC Absolute Maximum Ratings 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions 131. .

6.29.3 Current Consumption for Different ADC Configurations

(at 25-MHz ADCCLK) 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.4 ADC Power-Up Control Bit Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.5 Detailed Description 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.5.1 Reference Voltage 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.5.2 Analog Inputs 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.5.3 Converter 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.5.4 Conversion Modes 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) 134. . . . . . . . . . . . . . .

6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) 136. . . . . . . . . . . . . .

6.29.8 Definitions of Specifications and Terminology 137. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.30 Multichannel Buffered Serial Port (McBSP) Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.30.1 McBSP Transmit and Receive Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.30.2 McBSP as SPI Master or Slave Timing 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Migration From F281x Devices 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Mechanical Data 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

June 2004 − Revised June 2006 SPRS257C

7

Figures

List of Figures

Figure Page

Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View) 16. . . . . . . . . . . . . . . . . . . . . .

Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View) 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−1. Functional Block Diagram 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−2. R2812 Memory Map 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−3. R2811 Memory Map 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−4. External Interface Block Diagram 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−5. Interrupt Sources 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−6. Multiplexing of Interrupts Using the PIE Block 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−7. Clock and Reset Domains 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−8. OSC and PLL Block 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−9. Recommended Crystal/Clock Connection 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3−10. Watchdog Module 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−1. CPU-Timers 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−2. CPU-Timer Interrupts Signals and Output Signal 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−3. Event Manager A Functional Block Diagram 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−4. Block Diagram of the R281x ADC Module 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−5. ADC Pin Connections With Internal Reference 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−6. ADC Pin Connections With External Reference 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−7. eCAN Block Diagram and Interface Circuit 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−8. eCAN Memory Map 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−9. McBSP Module With FIFO 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram 75. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 79. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4−12. GPIO/Peripheral Pin MUXing 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5−1. TMS320x28x Device Nomenclature 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−1. Typical Current Consumption Over Frequency 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−2. Typical Power Consumption Over Frequency 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−3. Output Levels 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−4. Input Levels 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−5. 3.3-V Test Load Circuit 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−6. Clock Timing 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−7. Power-on Reset in Microcomputer Mode (XMP/MC = 0) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−8. Power-on Reset in Microprocessor Mode (XMP/MC = 1) 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−9. Warm Reset in Microcomputer Mode 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−10. Effect of Writing Into PLLCR Register 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−11. IDLE Entry and Exit Timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−12. STANDBY Entry and Exit Timing 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−13. HALT Wakeup Using XNMI 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−14. PWM Output Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

June 2004 − Revised June 2006SPRS257C

Figure 6−15. TDIRx Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−16. EVASOC Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−17. EVBSOC Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−18. External Interrupt Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−19. General-Purpose Output Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−20. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−21. General-Purpose Input Timing 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−22. SPI Master Mode External Timing (Clock Phase = 0) 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−23. SPI Master External Timing (Clock Phase = 1) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 0) 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−25. SPI Slave Mode External Timing (Clock Phase = 1) 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−26. Relationship Between XTIMCLK and SYSCLKOUT 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−27. Example Read Access 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−28. Example Write Access 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−29. Example Read With Synchronous XREADY Access 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−30. Example Read With Asynchronous XREADY Access 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−31. Write With Synchronous XREADY Access 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−32. Write With Asynchronous XREADY Access 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−33. External Interface Hold Waveform 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−34. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 129. . . . . . . . . . . . . . . . . . . . .

Figure 6−35. ADC Analog Input Impedance Model 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−36. ADC Power-Up Control Bit Timing 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−37. Sequential Sampling Mode (Single-Channel) Timing 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−38. Simultaneous Sampling Mode Timing 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−39. McBSP Receive Timing 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−40. McBSP Transmit Timing 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 141. . . . . . . . . . . . . . . . . . . . . .

Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 142. . . . . . . . . . . . . . . . . . . . . .

Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 143. . . . . . . . . . . . . . . . . . . . . .

Figure 6−44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 144. . . . . . . . . . . . . . . . . . . . . .

Figures

June 2004 − Revised June 2006 SPRS257C

9

Tables

List of Tables

Table Page

Table 2−1. Hardware Features 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2−2. Signal Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−1. Wait States 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−2. Boot Mode Selection 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−3. Peripheral Frame 0 Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−4. Peripheral Frame 1 Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−5. Peripheral Frame 2 Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−6. Device Emulation Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−7. XINTF Configuration and Control Register Mappings 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−8. XREVISION Register Bit Definitions 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−9. PIE Peripheral Interrupts 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−10. PIE Configuration and Control Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−11. External Interrupt Registers 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−12. PLL, Clocking, Watchdog, and Low-Power Mode Registers 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−13. PLLCR Register Bit Definitions 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−14. Possible PLL Configuration Modes 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3−15. R281x Low-Power Modes 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−2. Module and Signal Names for EVA and EVB 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−3. EVA Registers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−4. ADC Registers 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−6. CAN Registers Map 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−7. McBSP Register Summary 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−8. SCI-A Registers 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−9. SCI-B Registers 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−10. SPI Registers 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−11. GPIO MUX Registers 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4−12. GPIO Data Registers 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) 90. . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−2. TMS320R281x Clock Table and Nomenclature 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−3. Input Clock Frequency 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−5. XCLKIN Timing Requirements − PLL Disabled 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−6. Possible PLL Configuration Modes 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) 95. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−8. Reset (XRS) Timing Requirements 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−9. IDLE Mode Timing Requirements 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−10. IDLE Mode Switching Characteristics 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−11. STANDBY Mode Timing Requirements 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−12. STANDBY Mode Switching Characteristics 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−13. HALT Mode Timing Requirements 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−14. HALT Mode Switching Characteristics 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−15. PWM Switching Characteristics†‡ 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−16. Timer and Capture Unit Timing Requirements 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−17. External ADC Start-of-Conversion − EVA − Switching Characteristics† 104. . . . . . . . . . . . . . . . . . . . .

10

June 2004 − Revised June 2006SPRS257C

Table 6−18. External ADC Start-of-Conversion − EVB − Switching Characteristics 104. . . . . . . . . . . . . . . . . . . . . .

Table 6−19. Interrupt Switching Characteristics 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−20. Interrupt Timing Requirements 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−21. General-Purpose Output Switching Characteristics 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−22. General-Purpose Input Timing Requirements 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−23. SPI Master Mode External Timing (Clock Phase = 0) 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−24. SPI Master Mode External Timing (Clock Phase = 1) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−25. SPI Slave Mode External Timing (Clock Phase = 0) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−26. SPI Slave Mode External Timing (Clock Phase = 1) 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−27. Relationship Between Parameters Configured in XTIMING and Duration of Pulse 115. . . . . . . . . . . .

Table 6−28. XINTF Clock Configurations 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−29. External Memory Interface Read Switching Characteristics 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−30. External Memory Interface Read Timing Requirements 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−31. External Memory Interface Write Switching Characteristics 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−32. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) 121. . . .

Table 6−33. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) 121. . . . . .

Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 121. . . . . . . . . . . . . . .

Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) 121. . . . . . . . . . . . . .

Table 6−36. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) 124. . .

Table 6−37. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 124. . . . . . . . . . . . . . .

Table 6−38. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) 124. . . . . . . . . . . . . .

Table 6−39. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) 128. . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 129. . . . . . . . . . . . . . . . . . . . . .

Table 6−41. DC Specifications 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−42. AC Specifications 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−43. ADC Power-Up Delays 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−44. Sequential Sampling Mode Timing 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−45. Simultaneous Sampling Mode Timing 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−46. McBSP Timing Requirements 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−47. McBSP Switching Characteristics 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6−48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 141. . . . . . . . .

Table 6−49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 141. . . . . .

Table 6−50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 142. . . . . . . . . .

Table 6−51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 142. . . . . .

Table 6−52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 143. . . . . . . . .

Table 6−53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 143. . . . . .

Table 6−54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 144. . . . . . . . . .

Table 6−55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 144. . . . . .

Table 6−56. Feature Comparison Between F281x and R281x Devices 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−1. Thermal Resistance Characteristics for 179-GHH 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−2. Thermal Resistance Characteristics for 179-ZHH 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−3. Thermal Resistance Characteristics for 176-PGF 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7−4. Thermal Resistance Characteristics for 128-PBK 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

June 2004 − Revised June 2006 SPRS257C

11

Tables

12

June 2004 − Revised June 2006SPRS257C

1 Features

Features

D High-Performance Static CMOS Technology

− 150 MHz (6.67-ns Cycle Time)

− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design

D JTAG Boundary Scan Support

†

D High-Performance 32-Bit CPU

(TMS320C28x)

− 16 x 16 and 32 x 32 MAC Operations

− 16 x 16 Dual MAC

− Harvard Bus Architecture

− Atomic Operations

− Fast Interrupt Response and Processing

− Unified Memory Programming Model

− 4M Linear Program/Data Address Reach

− Code-Efficient (in C/C++ and Assembly)

− Code and Pin Compatible to F2810,
F2811, and F2812 devices

− TMS320F24x/LF240x Processor Source
Code Compatible

D On-Chip Memory

− 20K x 16 Total Single-Access RAM
(SARAM)

− L0 and L1: 2 Blocks of 4K x 16 Each

SARAM

− L2 and L3: 2 Blocks of 1K X 16 SARAM

− H0: 1 Block of 8K x 16 SARAM

− M0 and M1: 2 Blocks of 1K x 16 Each

SARAM

D SPI, SCI, and GPIO Boot Loader Modes to

Support Loading Code From Off-chip
Sources to On-chip RAM. SPI Boot Mode
Supports Loading From an External Serial
EEPROM.

D Boot ROM (4K x 16)

− With Software Boot Modes

− Standard Math Tables

D External Interface (2812)

− Up to 1M Total Memory

− Programmable Wait States

− Programmable Read/Write Strobe Timing

− Three Individual Chip Selects

D Clock and System Control

− Dynamic PLL Ratio Changes Supported

− On-Chip Oscillator

− Watchdog Timer Module

D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block

That Supports 45 Peripheral Interrupts

D Three 32-Bit CPU-Timers
D Motor Control Peripherals

− Two Event Managers (EVA, EVB)

− Compatible to 240xA Devices

D Serial Port Peripherals

− Serial Peripheral Interface (SPI)

− Two Serial Communications Interfaces
(SCIs), Standard UART

− Enhanced Controller Area Network
(eCAN)

− Multichannel Buffered Serial Port
(McBSP)

D 12-Bit ADC, 16 Channels

− 2 x 8 Channel Input Multiplexer

− Two Sample-and-Hold

− Single/Simultaneous Conversions

− Fast Conversion Rate: 80 ns/12.5 MSPS

D Up to 56 General Purpose I/O (GPIO) Pins
D Advanced Emulation Features

− Analysis and Breakpoint Functions

− Real-Time Debug via Hardware

D Development Tools Include

− ANSI C/C++ Compiler/Assembler/Linker

− Code Composer Studio IDE

− DSP/BIOS

− JTAG Scan Controllers

†

D Low-Power Modes and Power Savings

− IDLE, STANDBY, HALT Modes Supported

− Disable Individual Peripheral Clocks

D Package Options

− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)

− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)

− 128-Pin LQFP Without External Memory
Interface (PBK) (2811)

D Temperature Options:

− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)

− S: −40°C to 125°C (GHH, ZHH, PGF, PBK)

− Q: −40°C to 125°C (PGF, PBK)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†

IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port

June 2004 − Revised June 2006 SPRS257C

13

Introduction

2 Introduction

This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.

2.1 Description

The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in Section 3, Functional Overview.

Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812,
respectively.

TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

14

June 2004 − Revised June 2006SPRS257C

Introduction

Temperature Options

2.2 Device Summary

Table 2−1 provides a summary of each device’s features.

Table 2−1. Hardware Features

FEATURE R2811 R2812

Instruction Cycle (at 150 MHz) 6.67 ns 6.67 ns
Single-Access RAM (SARAM)

(16-bit word)
Boot ROM Yes Yes
External Memory Interface — Yes
Event Managers A and B

(EVA and EVB)

S General-Purpose (GP) Timers 4 4
S Compare (CMP)/PWM 16 16
S Capture (CAP)/QEP Channels 6/2 6/2

Watchdog Timer Yes Yes
12-Bit ADC Yes Yes

S Channels 16 16
32-Bit CPU Timers 3 3
SPI Yes Yes
SCIA, SCIB SCIA, SCIB SCIA, SCIB
CAN Yes Yes
McBSP Yes Yes
Digital I/O Pins (Shared) 56 56
External Interrupts 3 3
Supply Voltage 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O

Packaging 128-pin PBK

A: −40°C to 85°C Yes Yes

Temperature Options

Product Status

†

See Section 5.1, Device and Development Support Nomenclature for descriptions of product development stages.

†

S: −40°C to 125°C Yes Yes
Q: −40°C to 125°C Yes PGF package only

†

20K 20K

EVA, EVB EVA, EVB

179-ball GHH

179-ball ZHH

176-pin PGF

TMS TMS

June 2004 − Revised June 2006 SPRS257C

15

Introduction

2.3 Pin Assignments

Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.

2.3.1 Terminal Assignments for the GHH and ZHH Packages

See Table 2−2 for a description of each terminal’s function(s).

P

N

M

XZCS0AND1

SPISOMIA PWM9 XR/W

SPISIMOA XA[1] XRD

L

K

J

MCLKXA MFSRA XD[3]

H

G

F

E

MDXA MDRA XD[0]

XMP/MC

AVDD-

REFBG

PWM8

PWM10

PWM7 TEST2

V

DD

V

SPICLKA

SS

V

MCLKRA XD[1] MFSXA XD[2]

DD

RESEXT

ADCREFP

XD[6] PWM11 XD[7] C5TRIP

V

SS

XD[4]

ADC-

V

AVSS-

REFBG

V

PWM12

SPISTEA

V

DDIO

V

V

SSA1

DDA1

ADCREFM ADCINA5

SS

T4PWM

_T4CMP

_QEP3

T3PWM

_T3CMP

SS

ADCINB7 C3TRIP

CAP6

V

DD

_QEPI2

C4TRIP

CAP4

CAP5

_QEP4

XD[5] XD[13]

XA[0]

ADC-

BGREFIN

XD[8]

TEST1 XD[9] X2

V

V

C6TRIP

SS

XHOLD

DDIO

V

SS

V

DDIO

TDIRB XD[10]

TCLKINB

XNMI

_XINT13

T3CTRIP

V

DD

_PDPINTB

XD[11] XA[2] XWE

X1/

XCLKIN

V

DDIO

T4CTRIP/

EVBSOC

V

XA[3] PWM1

SS

V

DDIOVSS

XHOLDA

T2CTRIP

EVASOC

PWM5

T1PWM

_T1CMP

CAP1

_QEP1

XA[13] C2TRIP XA[8] C1TRIP

CAP2

_QEP2

/

V

XCLKOUT XA[7] TCLKINA TDIRA

V

DD

CANTXA CANRXA

PWM3 PWM4 XD[12]

V

DD

XA[4]

CAP3

_QEPI1

V

DDIO

DD

XZCS2

SCIRXDB

V

SS

T2PWM

_T2CMP

XA[5]

V

SS

SCITXDB

V

DDIO

PWM2

PWM6

V

SS

T1CTRIP

_PDPINTA

XA[6]

V

SS

16

XINT1

D

C

B

A

ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6 XRS

ADCINB3 ADCINB0 ADCINB1 ADCINA2

ADCINB2

V

DDAIO

V

ADCINA0 ADCINA4 V

SSAIO

ADCLO ADCINA3 ADCINA7 XREADY XA[17]

V

SSA2VSS1

DDA2VDD1

XA[18]

SCITXDA

SCIRXDA XA[16] XD[15] TESTSEL XA[11]

XINT2

_ADCSOC

V

DD

V

SS

_XBIO

EMU1

XA[15]

V

EMU0 TDO TMS XA[9]

SS

V

XA[12] XA[10] TDI

SS

XD[14] TRST

V

DD

XA[14]

XF

_XPLLDIS

TCK

XZCS6AND7

V

DD

V

SS

1412 1310 1189563412 7

Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)

June 2004 − Revised June 2006SPRS257C

2.3.2 Pin Assignments for the PGF Package

The TMS320R2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2.
See Table 2−2 for a description of each pin’s function(s).

Introduction

XZCS6AND7

TESTSEL

TRST

TCK

EMU0
XA[12]
XD[14]

XF_XPLLDIS

XA[13]

V
V

DD
XA[14]
V

DDIO

EMU1
XD[15]
XA[15]

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

XA[16]

V

V

DD

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

V

DD1

V

SS1

ADCBGREFIN

V

SSA2

V

DDA2
ADCINA7
ADCINA6
ADCINA5

ADCINA4

ADCINA3
ADCINA2

ADCINA1
ADCINA0

ADCLO

V

SSAIO

SS

VDDV

XA[11]

TDI

XA[10]

TDO

TMS

XA[9]

132 89

133

SS

SS

176

131

130

129

128

127

126

134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175

23456789101112131415161718192021222324252627282930313233343536373839404142

125

C2TRIP

C3TRIP

124

123

C1TRIP

XA[8]

121

122

SS

V

XCLKOUT

120

119

XA[7]

TCLKINA

118

117

T2CTRIP / EVASOC

TDIRA

116

115

DDIO

114

T1CTRIP_PDPINTA

VDDVSSV

XA[6]

111

113

112

110

SS

CAP3_QEPI1

XA[5]

CAP2_QEP2

CAP1_QEP1

V

109

108

107

106

105

DD

T2PWM_T2CMP

XA[4]

T1PWM_T1CMP

PWM6

VSSV

99989796959493

101

104

103

102

100

PWM5

XD[13]

XD[12]

PWM4

PWM3

PWM2

PWM1

929190

SCIRXDB

SCITXDB

CANRXA

87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

43

88

XZCS2
CANTXA

V

SS

XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
V

DDIO

XA[2]
T3CTRIP_PDPINTB
V

SS

X1/XCLKIN
X2

V

DD
XD[11]
XD[10]

TCLKINB
TDIRB
V

SS
V

DDIO
XD[9]
TEST1

TEST2
XD[8]
V

DDIO
C6TRIP

C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
V

SS
CAP4_QEP3
V

DD
T4PWM_T4CMP

XD[7]
T3PWM_T3CMP
V

SS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7

45

1

DDAIO

V

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFP

ADCREFM

SSA1

DDA1

V

V

AVSSREFBG

AVDDREFBG

SS

MCXMP/

V

XA[0]

MDRA

ADCRESEXT

XD[0]

MDXA

DD

V

XD[1]

MCLKRA

XD[2]

MFSXA

XD[3]VDDIO

MFSRA

MCLKXA

SS

V

XD[4]

SPICLKA

DD

V

XD[5]

SPISTEA

SS

V

XD[6]

SPISIMOA

XRD

XA[1]

SPISOMIA

44

XZCS0AND1

Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)

June 2004 − Revised June 2006 SPRS257C

17

Introduction

2.3.3 Pin Assignments for the PBK Package

The TMS320R2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−3.
See Table 2−2 for a description of each pin’s function(s).

TESTSEL

TRST

TCK

EMU0

XF_XPLLDIS

V

DD

V

SS

V

DDIO

EMU1

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

ADCBGREFIN

V

SS

V

DD

SCITXDA

SCIRXDA

XRS

V

DD1

V

SS1

V

SSA2

V

DDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0

ADCLO

V

SSAIO

97

128

SS

TDI

TDO

TMS

VDDV

96 65

93

9291908988

95

94

98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

2345678

C1TRIP

C2TRIP

C3TRIP

SS

XCLKOUT

V

878685

9

101112

TCLKINA

TDIRA

T2CTRIP/ EVASOC

84

131415

DDIO

VDDV

83

82

T1CTRIP_PDPINTA

CAP1_QEP1

CAP2_QEP2

CAP3_QEPI1

81

79

78

80

16

18

19

17

DD

T2PWM_T2CMP

T1PWM_T1CMP

76

77

21

20

PWM6

757473

222324

VSSV

PWM5

72

25

PWM4

PWM3

71

70

27

26

PWM1

PWM2

69

68

28

29

SCIRXDB

SCITXDB

CANRXA

66

67

63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

31

30

64

CANTXA
V

DD

V

SS
T4CTRIP
T3CTRIP_PDPINTB

V

SS
X1/XCLKIN
X2
V

DD
TCLKINB
TDIRB

V

SS
V

DDIO
TEST1
TEST2
V

DDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3

V

DD
T4PWM_T4CMP

T3PWM_T3CMP
V

SS
PWM12

PWM11
PWM10
PWM9
PWM8
PWM7

33

/EVBSOC

18

1

SS

DD

V

DDAIO

V

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFP

ADCREFM

AVSSREFBG

AVDDREFBG

SSA1

DDA1

V

V

ADCRESEXT

MDRA

MDXA

V

MCLKRA

MFSXA

Figure 2−3. TMS320R2811 128-Pin PBK LQFP

(Top View)

DDIO

V

MFSRA

MCLKXA

SS
V

SPICLKA

SS

DD

V

V

SPISTEA

32

SPISIMOA

SPISOMIA

June 2004 − Revised June 2006SPRS257C

2.4 Signal Descriptions

Table 2−2 specifies the signals on the R281x devices. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Introduction

June 2004 − Revised June 2006 SPRS257C

19

Introduction

§

19-bit XINTF Address Bus

16-bit XINTF Data Bus

Table 2−2. Signal Descriptions

PIN NO.

NAME

XA[18] D7 158 − O/Z −
XA[17] B7 156 − O/Z −
XA[16] A8 152 − O/Z −
XA[15] B9 148 − O/Z −
XA[14] A10 144 − O/Z −
XA[13] E10 141 − O/Z −
XA[12] C11 138 − O/Z −
XA[11] A14 132 − O/Z
XA[10] C12 130 − O/Z −
XA[9] D14 125 − O/Z −
XA[8] E12 121 − O/Z −
XA[7] F12 118 − O/Z −
XA[6] G14 111 − O/Z −
XA[5] H13 108 − O/Z −
XA[4] J12 103 − O/Z −
XA[3] M11 85 − O/Z −
XA[2] N10 80 − O/Z −
XA[1] M2 43 − O/Z −
XA[0] G5 18 − O/Z

XD[15] A9 147 − I/O/Z PU
XD[14] B11 139 − I/O/Z PU
XD[13] J10 97 − I/O/Z PU
XD[12] L14 96 − I/O/Z PU
XD[11] N9 74 − I/O/Z PU
XD[10] L9 73 − I/O/Z PU
XD[9] M8 68 − I/O/Z PU
XD[8] P7 65 − I/O/Z PU
XD[7] L5 54 − I/O/Z PU
XD[6] L3 39 − I/O/Z PU
XD[5] J5 36 − I/O/Z PU
XD[4] K3 33 − I/O/Z PU
XD[3] J3 30 − I/O/Z PU
XD[2] H5 27 − I/O/Z PU
XD[1] H3 24 − I/O/Z PU

XD[0] G3 21 − I/O/Z PU 16-bit XINTF Data Bus
†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH

AND
ZHH

176-PIN

PGF

128-PIN

PBK

XINTF SIGNALS (2812 ONLY)

XINTF SIGNALS (2812 ONLY) (CONTINUED)

I/O/Z‡PU/PD

†

DESCRIPTION

19-bit XINTF Address Bus

16-bit XINTF Data Bus

20

June 2004 − Revised June 2006SPRS257C

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

XMP/MC F1 17 − I PD

XHOLD E7 159 − I PU

XHOLDA K10 82 − O/Z −

XZCS0AND1 P1 44 − O/Z −

XZCS2 P13 88 − O/Z −

XZCS6AND7 B13 133 − O/Z −

XWE N11 84 − O/Z −

XRD M3 42 − O/Z −

XR/W N4 51 − O/Z −

XREADY B6 161 − I PU

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH

AND
ZHH

176-PIN

PGF

128-PIN

PBK

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode.
When high, Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the external interface,
and on-chip boot ROM may be accessed instead. This
signal is latched into the XINTCNF2 register on a reset and
the user can modify this bit in software. The state of the
XMP/MC

External Hold Request. XHOLD, when active (low),
requests the XINTF to release the external bus and place
all buses and strobes into a high-impedance state. The
XINTF will release the bus when any current access is
complete and there are no pending accesses on the
XINTF.

External Hold Acknowledge. XHOLDA is driven active
(low) when the XINTF has granted a XHOLD
XINTF buses and strobe signals will be in a
high-impedance state. XHOLDA is released when the
XHOLD
drive the external bus when XHOLDA

XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is
active (low) when an access to the XINTF Zone 0 or
Zone 1 is performed.

XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.

XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is
active (low) when an access to the XINTF Zone 6 or
Zone 7 is performed.

Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.

Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The
XRD

Read Not Write Strobe. Normally held high. When low,
XR/W
indicates read cycle is active.

Ready Signal. Indicates peripheral is ready to complete
the access when asserted to 1. XREADY can be
configured to be a synchronous or an asynchronous input.
See the timing diagrams for more details.

pin is ignored after reset.

request. All

signal is released. External devices should only

is active (low).

and XWE signals are mutually exclusive.

indicates write cycle is active; when high, XR/W

June 2004 − Revised June 2006 SPRS257C

21

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

X1/XCLKIN K9 77 58 I

X2 M9 76 57 O Oscillator Output

XCLKOUT F11 119 87 O −

TESTSEL A13 134 97 I PD Test Pin. Reserved for TI. Must be connected to ground.

179-PIN

GHH
AND

ZHH

176-PIN

PGF

128-PIN

PBK

JTAG AND MISCELLANEOUS SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

Oscillator Input − input to the internal oscillator. This pin is
also used to feed an external clock. The 28x can be
operated with an external clock source, provided that the
proper voltage levels be driven on the X1/XCLKIN pin. It
should be noted that the X1/XCLKIN pin is referenced to
the 1.8-V (or 1.9-V) core digital power supply (VDD), rather
than the 3.3-V I/O supply (V
be used to clamp a buffered clock signal to ensure that the
logic-high level does not exceed VDD (1.8 V or 1.9 V) or a

1.8-V oscillator may be used.

Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose
clock source. XCLKOUT is either the same frequency , 1/ 2
the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT
signal can be turned off by setting bit 3 (CLKOFF) of the
XINTCNF2 register to 1. Unlike other GPIO pins, the
XCLKOUT pin is not placed in a high impedance state
during reset.

Device Reset (in) and Watchdog Reset (out).

). A clamping diode may

DDIO

Device reset. XRS causes the device to terminate
execution. The PC will point to the address contained at
the location 0x3FFFC0. When XRS
level, execution begins at the location pointed to by the

XRS D6 160 113 I/O PU

TEST1 M7 67 51 I/O −

TEST2 N7 66 50 I/O −
†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

PC. This pin is driven low by the DSP when a watchdog
reset occurs. During watchdog reset, the XRS
driven low for the watchdog reset duration of 512 XCLKIN
cycles.

The output buffer of this pin is an open-drain with an
internal pullup (100 µA, typical). It is recommended that
this pin be driven by an open-drain device.

This pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).

This pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).

is brought to a high

pin will be

22

June 2004 − Revised June 2006SPRS257C

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

TRST B12 135 98 I PD

TCK A12 136 99 I PU JTAG test clock with internal pullup

TMS D13 126 92 I PU

TDI C13 131 96 I PU

TDO D12 127 93 O/Z −

EMU0 D11 137 100 I/O/Z PU

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH

AND
ZHH

176-PIN

PGF

128-PIN

PBK

I/O/Z

I/O/Z

‡

‡

JTAG

†

(Continued)

§

§

JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset
signals are ignored.

NOTE: Do not use pullup resistors on TRST
internal pulldown device. TRST
and must be maintained low at all times during normal
device operation. In a low-noise environment, TRST
be left floating. In other instances, an external pulldown
resistor is highly recommended. The value of this resistor
should be based on drive strength of the debugger pods
applicable to t h e design. A 2.2-kΩ resistor generally of fers
adequate protection. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.

JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on the
rising edge of TCK.

JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on
a rising edge of TCK.

JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) is shifted out of
TDO on the falling edge of TCK.

Emulator pin 0. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and
is defined as input/output through the JTAG scan. This
pin is also used to put the device into boundary-scan
mode. With the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on the
TRST

pin would latch the device into boundary-scan

mode.
NOTE: An external pullup resistor is recommended on

this pin. The value of this resistor should be based on
the drive strength of the debugger pods applicable to
the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.

is an active high test pin

; it has an

may

June 2004 − Revised June 2006 SPRS257C

23

Introduction

ADC pins should not be driven before V

, V

, and

V

pins have been fully powered up.

V

DDAIO

pins have been fully powered up.

ADC pins should not be driven before the V

, V

,

and V

DDAIO

pins have been fully powered up.

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

EMU1 C9 146 105 I/O/Z PU

ADCINA7 B5 167 119 I
ADCINA6 D5 168 120 I
ADCINA5 E5 169 121 I
ADCINA4 A4 170 122 I
ADCINA3 B4 171 123 I
ADCINA2 C4 172 124 I
ADCINA1 D4 173 125 I
ADCINA0 A3 174 126 I
ADCINB7 F5 9 9 I
ADCINB6 D1 8 8 I
ADCINB5 D2 7 7 I
ADCINB4 D3 6 6 I
ADCINB3 C1 5 5 I
ADCINB2 B1 4 4 I
ADCINB1 C3 3 3 I
ADCINB0 C2 2 2 I

ADCREFP E2 11 11 I/O

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH
AND

ZHH

176-PIN

PGF

128-PIN

PBK

JTAG (CONTINUED)

ADC ANALOG INPUT SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

Emulator pin 1. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and
is defined as input/output through the JTAG scan. This
pin is also used to put the device into boundary-scan
mode. With the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on the
TRST

pin would latch the device into boundary-scan

mode.
NOTE: An external pullup resistor is recommended on

this pin. The value of this resistor should be based on
the drive strength of the debugger pods applicable to
the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.

8-Channel analog inputs for Sample-and-Hold A. The

DDA1

DDA2

8-Channel Analog Inputs for Sample-and-Hold B. The

DDA1

ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to
analog ground. (Can accept external reference input (2 V)
if the software bit is enabled for this mode. 1−10 µF low
ESR capacitor can be used in the external reference
mode.)

DDA2

24

June 2004 − Revised June 2006SPRS257C

Introduction

,

Recommended Operating Conditions, for voltage
requirements.

requirements.

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

ADCREFM E4 10 10 I/O

ADCRESEXT F2 16 16 O ADC External Current Bias Resistor (24.9 kΩ ±5%)
ADCBGREFIN E6 164 116 I Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG E3 12 12 I ADC Analog GND
AVDDREFBG E1 13 13 I ADC Analog Power (3.3-V)

ADCLO B3 175 127 I
V

SSA1

V

SSA2

V

DDA1

V

DDA2

V

SS1

V

DD1

V

DDAIO

V

SSAIO

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH

AND
ZHH

P12 − 63
K12 100 74
G12 112 82
C14 128 94
B10 143 102

176-PIN

PGF

F3 15 15 I ADC Analog GND
C5 165 117 I ADC Analog GND

F4 14 14 I ADC Analog 3.3-V Supply
A5 166 118 I ADC Analog 3.3-V Supply
C6 163 115 I ADC Digital GND
A6 162 114 I ADC Digital 1.8-V (or 1.9-V) Supply
B2 1 1 3.3-V Analog I/O Power Pin
A2 176 128 Analog I/O Ground Pin

H1 23 20
L1 37 29
P5 56 42
P9 75 56

C8 154 110

128-PIN

PBK

ADC ANALOG INPUT SIGNALS (CONTINUED)

POWER SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to
analog ground. (Can accept external reference input (1 V)
if the software bit is enabled for this mode. 1−10 µF low
ESR capacitor can be used in the external reference
mode.)

Common Low Side Analog Input. Connect to analog
ground.

1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2

June 2004 − Revised June 2006 SPRS257C

25

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

GPIOA0
PWM1 (O)

GPIOA1
PWM2 (O)

GPIOA2
PWM3 (O)

GPIOA3
PWM4 (O)

GPIOA4/PWM5 (O) K11 98 72 I/O/Z PU GPIO or PWM Output Pin #5
GPIOA5

PWM6 (O)
GPIOA6

T1PWM_T1CMP (I)
†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH
AND

ZHH

M10 78 59

K13 99 73

G13 113 −
E14 120 88
B14 129 95
D10 142 −
C10 − 103

N14 − −
G11 114 83

M12 92 68 I/O/Z PU GPIO or PWM Output Pin #1

M14 93 69 I/O/Z PU GPIO or PWM Output Pin #2

K14 101 75 I/O/Z PU GPIO or PWM Output Pin #6

176-PIN

PGF

G4 19 17
K1 32 26

L2 38 30
P4 52 39
K6 58 −
P8 70 53

L11 86 62

J14 105 −

B8 153 109

J4 31 25

L7 64 49

L10 81 −

E9 145 104
N8 69 52

L12 94 70 I/O/Z PU GPIO or PWM Output Pin #3

L13 95 71 I/O/Z PU GPIO or PWM Output Pin #4

J11 102 76 I/O/Z PU GPIO or Timer 1 Output

128-PIN

PBK

POWER SIGNALS (CONTINUED)

GPIO OR EVA SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

Core and Digital I/O Ground Pins

3.3-V I/O Digital Power Pins

26

June 2004 − Revised June 2006SPRS257C

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOA7
T2PWM_T2CMP (I)

GPIOA8
CAP1_QEP1 (I)

GPIOA9
CAP2_QEP2 (I)

GPIOA10/
CAP3_QEPI1 (I)

GPIOA11
TDIRA (I)

GPIOA12
TCLKINA (I)

GPIOA13
C1TRIP

(I)

GPIOA14
C2TRIP

(I)

GPIOA15
C3TRIP

(I)

GPIOB0
PWM7 (O)

GPIOB1
PWM8 (O)

GPIOB2
PWM9 (O)

GPIOB3
PWM10 (O)

GPIOB
PWM11 (O)

GPIOB5
PWM12 (O)

GPIOB6/
T3PWM_T3CMP (I)

GPIOB7/
T4PWM_T4CMP (I)

GPIOB8/CAP4_QEP3 (I) M5 57 43 I/O/Z PU GPIO or Capture Input #4
GPIOB9/CAP5_QEP4 (I) M6 59 44 I/O/Z PU GPIO or Capture Input #5
GPIOB10/CAP6_QEPI2 (I) P6 60 45 I/O/Z PU GPIO or Capture Input #6
GPIOB11/TDIRB (I) L8 71 54 I/O/Z PU GPIO or Timer Direction
GPIOB12/TCLKINB (I) K8 72 55 I/O/Z PU GPIO or Timer Clock Input

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

179-PIN

GHH

AND
ZHH

J13 104 77 I/O/Z PU GPIO or Timer 2 Output

H10 106 78 I/O/Z PU GPIO or Capture Input #1

H11 107 79 I/O/Z PU GPIO or Capture Input #2

H12 109 80 I/O/Z PU GPIO or Capture Input #3

F14 116 85 I/O/Z PU GPIO or Timer Direction

F13 117 86 I/O/Z PU GPIO or Timer Clock Input

E13 122 89 I/O/Z PU GPIO or Compare 1 Output Trip

E11 123 90 I/O/Z PU GPIO or Compare 2 Output Trip

F10 124 91 I/O/Z PU GPIO or Compare 3 Output Trip

176-PIN

PGF

N2 45 33 I/O/Z PU GPIO or PWM Output Pin #7

P2 46 34 I/O/Z PU GPIO or PWM Output Pin #8

N3 47 35 I/O/Z PU GPIO or PWM Output Pin #9

P3 48 36 I/O/Z PU GPIO or PWM Output Pin #10

L4 49 37 I/O/Z PU GPIO or PWM Output Pin #11

M4 50 38 I/O/Z PU GPIO or PWM Output Pin #12

K5 53 40 I/O/Z PU GPIO or Timer 3 Output

N5 55 41 I/O/Z PU GPIO or Timer 4 Output

128-PIN

PBK

GPIO OR EVA SIGNALS (CONTINUED)

GPIOB OR EVB SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

June 2004 − Revised June 2006 SPRS257C

27

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOB13/C4TRIP (I) N6 61 46 I/O/Z PU GPIO or Compare 4 Output Trip
GPIOB14/C5TRIP (I) L6 62 47 I/O/Z PU GPIO or Compare 5 Output Trip
GPIOB15/C6TRIP (I) K7 63 48 I/O/Z PU GPIO or Compare 6 Output Trip

GPIOD0/
T1CTRIP_PDPINTA

GPIOD1/
T2CTRIP

GPIOD5/
T3CTRIP_PDPINTB

GPIOD6/
T4CTRIP

GPIOE0/XINT1_XBIO (I) D9 149 106 I/O/Z − GPIO or XINT1 or XBIO input
GPIOE1/

XINT2_ADCSOC (I)
GPIOE2

XNMI_XINT13 (I)

GPIOF0
SPISIMOA (O)

GPIOF1
SPISOMIA (I)

GPIOF2
SPICLKA (I/O)

GPIOF3
SPISTEA (I/O)

GPIOF4
SCITXDA (O)

GPIOF5
SCIRXDA (I)

GPIOF6
CANTXA (O)

GPIOF7
CANRXA (I)

†
‡

§

/EVASOC (I)

/EVBSOC (I)

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

(I)

(I)

179-PIN

GHH
AND

ZHH

H14 110 81 I/O/Z PU Timer 1 Compare Output Trip

G10 115 84 I/O/Z PU

P10 79 60 I/O/Z PU Timer 3 Compare Output Trip

P11 83 61 I/O/Z PU

N12 87 64 I/O/Z PU GPIO or eCAN transmit data

N13 89 65 I/O/Z PU GPIO or eCAN receive data

176-PIN

PGF

D8 151 108 I/O/Z − GPIO or XINT2 or ADC start of conversion

E8 150 107 I/O/Z PU GPIO or XNMI or XINT13

M1 40 31 I/O/Z − GPIO or SPI slave in, master out

N1 41 32 I/O/Z − GPIO or SPI slave out, master in

K2 34 27 I/O/Z − GPIO or SPI clock

K4 35 28 I/O/Z − GPIO or SPI slave transmit enable

C7 155 111 I/O/Z PU GPIO or SCI asynchronous serial port TX data

A7 157 112 I/O/Z PU GPIO or SCI asynchronous serial port RX data

128-PIN

PBK

GPIOD OR EVA SIGNALS

GPIOD OR EVB SIGNALS

GPIOE OR INTERRUPT SIGNALS

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

Timer 2 Compare Output Trip or External ADC
Start-of-Conversion EV-A

Timer 4 Compare Output Trip or External ADC
Start-of-Conversion EV-B

28

June 2004 − Revised June 2006SPRS257C

Introduction

Table 2−2. Signal Descriptions

PIN NO.

NAME DESCRIPTIONPU/PD

NAME DESCRIPTIONPU/PD

GPIOF8
MCLKXA (I/O)

GPIOF9
MCLKRA (I/O)

GPIOF10
MFSXA (I/O)

GPIOF11
MFSRA (I/O)

GPIOF12
MDXA (O)

GPIOF13
MDRA (I)

GPIOF14
XF_XPLLDIS

GPIOG4/SCITXDB (O) P14 90 66 I/O/Z − GPIO or SCI asynchronous serial port transmit data
GPIOG5/SCIRXDB (I) M13 91 67 I/O/Z − GPIO or SCI asynchronous serial port receive data

†

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡

I = Input, O = Output, Z = High impedance

§

PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.

(O)

179-PIN

GHH

AND
ZHH

A11 140 101 I/O/Z PU

176-PIN

PGF

J1 28 23 I/O/Z PU GPIO or transmit clock

H2 25 21 I/O/Z PU GPIO or receive clock

H4 26 22 I/O/Z PU GPIO or transmit frame synch

J2 29 24 I/O/Z PU GPIO or receive frame synch

G1 22 19 I/O/Z − GPIO or transmitted serial data

G2 20 18 I/O/Z PU GPIO or received serial data

128-PIN

PBK

GPIOF OR XF CPU OUTPUT SIGNAL

GPIOG OR SCI-B SIGNALS

I/O/Z

I/O/Z

‡

‡

†

(Continued)

§

§

This pin has three functions:

1) XF − General-purpose output pin.

2) XPLLDIS − This pin will be sampled during reset to
check if the PLL needs to be disabled. The PLL will
be disabled if this pin is sensed low. HALT and
STANDBY modes cannot be used when the PLL is
disabled.

3) GPIO − GPIO function

NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However , i t i s acceptable for an I/O pin to ramp along with
the 3.3-V supply.

June 2004 − Revised June 2006 SPRS257C

29

Functional Overview

3 Functional Overview

Memory Bus

GPIO Pins

TINT0

TINT1

G
P

I

O

M

U
X

XINT13

XNMI

CPU-Timer 0
CPU-Timer 1

CPU-Timer 2

TINT2

PIE

(96 interrupts)

External Interrupt

Control

(XINT1/2/13, XNMI)

SCIA/SCIB

SPI FIFO

McBSP

eCAN

EVA/EVB

†

FIFO

FIFO

INT14

INT[12:1]

INT13
NMI

C28x CPU

Real-Time JTAG

External

Interface

‡

(XINTF)

M0 SARAM

1K x 16

M1 SARAM

1K x 16

L0 SARAM

4K x 16

L1 SARAM

4K x 16

L2 SARAM

1K X 16

Control

Address(19)

Data(16)

XRS

X1/XCLKIN

X2

XF_XPLLDIS

†

45 of the possible 96 interrupts are used on the devices.

‡

XINTF is available on the R2812 devices only.

16 Channels

12-Bit ADC

System Control

(Oscillator and PLL

+

Peripheral Clocking

+

Low-Power

Modes

+

WatchDog)

Peripheral Bus

RS
CLKIN

Memory Bus

Figure 3−1. Functional Block Diagram

L3 SARAM

1K X 16

H0 SARAM

8K × 16

Boot ROM

4K × 16

30

June 2004 − Revised June 2006SPRS257C