TEXAS INSTRUMENTS TMS320LF2407A Technical data

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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

D High-Performance Static CMOS Technology

− 25-ns Instruction Cycle Time (40 MHz)

− 40-MIPS Performance

− Low-Power 3.3-V Design

D Based on TMS320C2xx DSP CPU Core

− Code-Compatible With F243/F241/C242

− Instruction Set and Module Compatible

With F240

D Flash (LF) and ROM (LC) Device Options

− LF240xA: LF2407A, LF2406A, LF2403A, LF2402A

− LC240xA: LC2406A, LC2404A, LC2403A, LC2402A

D On-Chip Memory

− Up to 32K Words x 16 Bits of Flash

EEPROM (4 Sectors) or ROM

− Programmable “Code-Security” Feature

for the On-Chip Flash/ROM

− Up to 2.5K Words x 16 Bits of

Data/Program RAM

− 544 Words of Dual-Access RAM

− Up to 2K Words of Single-Access RAM

D Boot ROM (LF240xA Devices)

− SCI/SPI Bootloader

D Up to Two Event-Manager (EV) Modules

(EVA and EVB), Each Includes:

− Two 16-Bit General-Purpose Timers

− Eight 16-Bit Pulse-Width Modulation

(PWM) Channels Which Enable:

− Three-Phase Inverter Control

− Center- or Edge-Alignment of PWM

Channels

− Emergency PWM Channel Shutdown With External PDPINTx

− Programmable Deadband (Deadtime) Prevents Shoot-Through Faults

− Three Capture Units for Time-Stamping of External Events

− Input Qualifier for Select Pins

− On-Chip Position Encoder Interface

Circuitry

− Synchronized A-to-D Conversion

− Designed for AC Induction, BLDC,

Switched Reluctance, and Stepper Motor Control

− Applicable for Multiple Motor and/or Converter Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D External Memory Interface (LF2407A)

− 192K Words x 16 Bits of Total Memory: 64K Program, 64K Data, 64K I/O

D Watchdog (WD) Timer Module

D 10-Bit Analog-to-Digital Converter (ADC)

− 8 or 16 Multiplexed Input Channels

− 500-ns MIN Conversion Time

− Selectable Twin 8-State Sequencers

Triggered by Two Event Managers

D Controller Area Network (CAN) 2.0B Module

(LF2407A, 2406A, 2403A)

D Serial Communications Interface (SCI)

D 16-Bit Serial Peripheral Interface (SPI)

(LF2407A, 2406A, LC2404A, 2403A)

D Phase-Locked-Loop (PLL)-Based Clock

Generation

D Up to 40 Individually Programmable,

Multiplexed General-Purpose Input/Output (GPIO) Pins

D Up to Five External Interrupts (Power Drive

Protection, Reset, Two Maskable Interrupts)

D Power Management:

− Three Power-Down Modes

− Ability to Power Down Each Peripheral

Independently

D Real-Time JTAG-Compliant Scan-Based

Emulation, IEEE Standard 1149.1

†

(JTAG)

D Development Tools Include:

− Texas Instruments (TI) ANSI C Compiler, Assembler/Linker, and Code Composer Studio Debugger

− Evaluation Modules

− Scan-Based Self-Emulation (XDS510)

− Broad Third-Party Digital Motor Control

Support

D Package Options

− 144-Pin LQFP PGE (LF2407A)

− 100-Pin LQFP PZ (2406A, LC2404A)

− 64-Pin TQFP PAG (LF2403A, LC2403A,

LC2402A)

− 64-Pin QFP PG (2402A)

D Extended Temperature Options (A and S)

− A: − 40°C to 85°C

− S: − 40°C to 125°C

Code Composer Studio and XDS510 are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.

†

IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

Table of Contents

Description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x240xA Device Summary 5. . . . . . . . . . . . . . . . .

Functional Block Diagram of the 2407A

DSP Controller 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pinouts 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Maps 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Memory Map of the 2407A/2406A 29. . . . . . .

Device Reset and Interrupts 30. . . . . . . . . . . . . . . . . . . . .

DSP CPU Core 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x240xA Instruction Set 34. . . . . . . . . . . . . . . . . . .

Scan-Based Emulation 34. . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Block Diagram

Internal Memory 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripherals 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Event Manager Modules (EVA, EVB) 45. . . . . . . . . . . .

Enhanced Analog-to-Digital Converter

(ADC) Module 49. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Communications Interface (SCI) Module 53. . . .

of the 2407A DSP CPU 35. .

Controller Area Network (CAN) Module 51. . . . . . . . . .

Serial Peripheral Interface (SPI) Module 55. . . . . . . . . .

PLL-Based Clock Module 57. . . . . . . . . . . . . . . . . . . . . .

Digital I/O and Shared Pin Functions 60. . . . . . . . . . . . .

External Memory Interface (LF2407A) 64. . . . . . . . . . . .

Watchdog (WD) Timer Module 65. . . . . . . . . . . . . . . . . .

Development Support 67. . . . . . . . . . . . . . . . . . . . . . . . . . .

Documentation Support 70. . . . . . . . . . . . . . . . . . . . . . . . .

LF240xA and LC240xA Electrical

Specifications Data 71. . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 71. . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 71. . . . . . . . . . . . .

Migrating From LF240xA (Flash) Devices to

LC240xA (ROM) Devices 110. . . . . . . . . . . . . . . . . . .

Migrating From 240x Devices to 240xA Devices 111. . . Migrating From LF240x Devices to

LC240xA Devices 112. . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Register Description 113. . . . . . . . . . . . . . . . . .

Mechanical Data 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

REVISION HISTORY

PAGE HIGHLIGHTS

1 Deleted C240 from the second bullet on the features page

16 Modified description of the signal TRST in Table 2

27 Modified the Program section of the memory map in Figure 7

58 Changed the text under external reference crystal clock option

71 Modified Note 2 in the absolute maximum ratings table

71 Added the RS signal to Group 1 in the notes on the recommended operating conditions table

77 Changed the maximum logic−low level of 0.8 to 0.4 V in the signal transition levels section

110 Added LC2403A device to Table 18

DSP CONTROLLERS

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

description

The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features.

The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based “code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash counterparts.

All 240xA devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single 240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes inadvertent pin-triggering by glitches.

The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.

A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces, the 2407A, 2406A, 2404A, and 2403A offer a 16-bit synchronous serial peripheral interface (SPI). The 2407A, 2406A, and 2403A offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs).

To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level development tools, but also system-level design and development support.

TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

TMS320x240xA device summary

Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation of devices.

Table 1. Hardware Features of 240xA Devices

FEATURE LF2407A LF2406A LF2403A LF2402A LC2406A LC2404A LC2403A LC2402A

C2xx DSP Core Yes Yes Yes Yes Yes Yes Yes Yes

Instruction Cycle 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns

MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS

Dual-Access

RAM (16-bit word)

3.3-V On-chip Flash (16-bit word) (4 sectors: 4K, 12K, 12K, 4K)

On-chip ROM (16-bit word) — — — — 32K 16K 16K 6K

Code Security for On-Chip Flash/ROM Ye s Yes Yes Yes Yes Yes Yes Yes

Boot ROM Yes Yes Yes Yes — — — —

External Memory Interface Yes — — — — — — —

Event Managers A and B (EVA and EVB)

S General-Purpose (GP) Timers 4 4 2 2 4 4 2 2

S Compare (CMP)/PWM 12/16 12/16 6/8 6/8 12/16 12/16 6/8 6/8

S Capture (CAP)/QEP 6/4 6/4 3/2 3/2 6/4 6/4 3/2 3/2

S Input qualifier circuitry on

PDPINTx XINT1/2, and ADCSOC pins

S Status of PDPINTx pin reflected

in COMCONx register

Watchdog Timer Yes Yes Yes Yes Yes Yes Yes Yes

10-Bit ADC Yes Yes Yes Yes Yes Yes Yes Yes

S Channels 16 16 8 8 16 16 8 8

S Conversion Time (minimum) 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns

SPI Yes Yes Yes — Ye s Ye s Ye s —

SCI Yes Ye s Ye s Yes Ye s Ye s Yes Yes

CAN Yes Yes Yes — Ye s — Yes —

Digital I/O Pins (Shared)

External Interrupts 5 5 3 3 5 5 3 3

Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

Packaging

Product Status:

Product Preview (PP) Advance Information (AI) Production Data (PD)

RAM (DARAM)

Single-Access RAM (SARAM)

, CAPx, QEPx,

544 544 544 544 544 544 544 544

2K 2K 512 512 2K 1K 512 —

32K 32K 16K 8K — — — —

EVA,

EVB

Yes Yes Yes Yes Yes Yes Yes Yes

41 41 21 21 41 41 21 21

144-pin

PGE

PD PD PD PD PD PD PD PD

EVA,

EVB

100-pinPZ64-pin

EVA EVA

PAG

EVA,

EVB

64-pinPG100-pinPZ100-pinPZ64-pin

EVA,

EVB

EVA EVA

PAG

PG, PAG

64-pin

Denotes features that are different/new compared to 240x devices.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

functional block diagram of the 2407A DSP controller

PLLF

PLLV

XINT1/IOPA2

CLKOUT/IOPE0

TMS2

BIO/IOPC1

MP/MC

BOOT_EN/XF

VDD (3.3 V)

TP1

TP2

(5V)

CCP

A0−A15

D0−D15

PS, DS, IS

R/W

READY

STRB

ENA_144

VIS_OE

W/R / IOPC0

PDPINTA

CAP1/QEP1/IOPA3

CAP2/QEP2/IOPA4

CAP3/IOPA5

PWM1/IOPA6 PWM2/IOPA7

PWM3/IOPB0

PWM4/IOPB1

PWM5/IOPB2 PWM6/IOPB3

T1PWM/T1CMP/IOPB4

T2PWM/T2CMP/IOPB5

TDIRA/IOPB6

TCLKINA/IOPB7

DARAM (B0)

256 Words

C2xx

DSP

Core

DARAM (B1)

256 Words

DARAM (B2)

32 Words

PLL Clock

10-Bit ADC

(With Twin

Autosequencer)

SCI

SARAM (2K Words)

SPI

Flash/ROM

(32K Words:

4K/12K/12K/4K)

External Memory

Interface

CAN

Digital I/O

(Shared With

Other Pins)

JTAG Port

Event Manager A

D 3 × Capture Input D 6 × Compare/PWM

Output

D 2 × GP

Timers/PWM

Event Manager B

D 3 × Capture Input D 6 × Compare/PWM

Output

D 2 × GP

Timers/PWM

CCA

PLLF2

XTAL1/CLKIN

XTAL2

ADCIN00−ADCIN07 ADCIN08−ADCIN15 V

CCA

SSA

REFHI

REFLO

XINT2/ADCSOC/IOPD0

SCITXD/IOPA0 SCIRXD/IOPA1

SPISIMO/IOPC2

SPISOMI/IOPC3

SPICLK/IOPC4

SPISTE/IOPC5

CANTX/IOPC6 CANRX/IOPC7

Port A(0−7) IOPA[0:7]

Port B(0−7) IOPB[0:7]

Port C(0−7) IOPC[0:7] Port D(0) IOPD[0]

Port E(0−7) IOPE[0:7]

Port F(0−6) IOPF[0:6] TRST

TDO

TDI

TMS

TCK EMU0 EMU1

PDPINTB

CAP4/QEP3/IOPE7

CAP5/QEP4/IOPF0

CAP6/IOPF1

PWM7/IOPE1

PWM8/IOPE2

PWM9/IOPE3

PWM10/IOPE4

PWM11/IOPE5

PWM12/IOPE6

T3PWM/T3CMP/IOPF2

T4PWM/T4CMP/IOPF3

TDIRB/IOPF4

TCLKINB/IOPF5

Indicates optional modules. The memory size and peripheral selection of these modules change for different 240xA devices. See Table 1 for device-specific details.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

TRST

TDIRB/IOPF4

SSO

DDO

T4PWM/T4CMP/IOPF3

T3PWM/T3CMP/IOPF2

T1PWM/T1CMP/IOPB4

T2PWM/T2CMP/IOPB5

XINT2/ADCSOC/IOPD0

PDPINTA

PLLF2

PLLF

PLLV

CCA

TDIRA/IOPB6

D10

D11

W/R/IOPC0

D12

D13

XINT1/IOPA2

D14

SCITXD/IOPA0

SCIRXD/IOPA1

D15

SPISIMO/IOPC2

SPISOMI/IOPC3

A15

/IOPC5

SPISTE

A14

SPICLK/IOPC4

TMS2

PGE PACKAGE

†

(TOP VIEW)

‡

IOPF5

SSO

DDO

PDPINTB

138

A12

137

136

A11

IOPB2

PWM5/

TCK

135

IOPE5

PWM11/

134RS133

A10

IOPB1

PWM4/

TDI

TDO

TMS

144

143

142

141

140

139

373839404142434445464748495051525354555657585960616263646566676869

A13

SSO

DDO

IOPE6

IOPB7

IOPB3

PWM6/

PWM12/

TCLKINA/

IOPF6

132

131

130

129

TMS320LF2407A PGE

IOPB0

PWM3/

128

TCLKINB/

127

126

IOPA7

IOPE4

PWM2/

PWM10/

SSO

125

IOPA6

PWM1/

XTAL1/CLKIN

XTAL2

124

123

CCP

BOOT_EN/XF

ENA_144

122

121

TP1

IOPE3

PWM9/

IOPC1BIO/

READY

119

120

IOPE2

PWM8/

SSA

MP/MC

118

117

TP2

CCA

116

IOPE1

PWM7/

REFHI

115

SSO

REFLO

114

DDO

ADCIN00

ADCIN08

113

112

IOPF1

CAP6/

ADCIN01

ADCIN09

111

110

707172

IOPC7

CANRX/

ADCIN10

109

108

107

106

105

104

103

102

101

100

IOPC6

CANTX/

ADCIN11

ADCIN02

ADCIN12

ADCIN03

ADCIN13

ADCIN04

ADCIN05

ADCIN14

ADCIN06

ADCIN07

ADCIN15

VIS_OE

STRB

DDO

SSO

R/W

EMU1/OFF

EMU0

CAP4/QEP3/IOPE7

CAP1/QEP1/IOPA3

CAP5/QEP4/IOPF0

CAP2/QEP2/IOPA4

DDO

SSO

CAP3/IOPA5

CLKOUT/IOPE0

†

Bold, italicized pin names indicate pin function after reset.

‡

BOOT_EN is available only on Flash devices.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pinouts (continued)

DDO

SSO

OFF

EMU1/

†

IOPE7

IOPA3

IOPF0

EMU0

CAP4/QEP3/VCAP1/QEP1/

CAP5/QEP4/

IOPA4

/IOPE0

IOPA5

DDO

SSO

CAP2/QEP2/VCAP3/

CLKOUT

51525354555657585960616263646566676869707172737475

25242322212019181716151413121110987654321

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26100

CANTX/IOPC6 CANRX/IOPC7 CAP6/IOPF1 V

DDO

SSO

PWM7/IOPE1 TP2 PWM8/IOPE2 TP1 PWM9/IOPE3

CCP

PWM1/IOPA6 PWM10/IOPE4 PWM2/IOPA7 PWM3/IOPB0 V

PWM4/IOPB1 PWM11/IOPE5 PWM5/IOPB2 V

DDO

SSO

PWM6/IOPB3 PWM12/IOPE6 TCLKINA/IOPB7

ADCIN10 ADCIN01 ADCIN09 ADCIN00

ADCIN08

REFLO

REFHI

CCA

SSA

BIO/IOPC1

BOOT_EN

/XF

XTAL1/CLKIN

XTAL2

TCLKINB/IOPF5

IOPF6

TCK

PDPINTB

TDI

SSO

DDO

TDO TMS

PZ PACKAGE

( TOP VIEW)

ADCIN11

ADCIN02

ADCIN12

ADCIN03

ADCIN13

ADCIN04

ADCIN05

ADCIN14

ADCIN06

ADCIN07

ADCIN15

76 77 78 79 80 81 82 83 84 85

86 87 88 89 90

91 92 93 94 95 96 97 98 99

TMS320LC2404A PZ TMS320LC2406A PZ TMS320LF2406A PZ

‡

SSOVSSO

DDO

TRST

IOPF4

IOPF3

TDIRB/

TDIRB/ IOPF4

T4PWM/T4CMP/

†

Bold, italicized pin names indicate pin function after reset.

‡

CANTX and CANRX are not available on LC2404A devices.

BOOT_EN is available only on Flash devices.

On the ROM devices (LC240xA), V

is a No Connect (NC).

CCP

PLLF

IOPF2

PLLF2

PDPINTA

T3PWM/T3CMP/

CCA

IOPB6

IOPB4

PLLV

TDIRA/

T1PWM/T1CMP/

IOPA2

IOPA0

IOPC0

IOPD0

IOPB5

XINT1/

SCITXD/

T2PWM/T2CMP/

XINT2/ADCSOC/

IOPA1

SCIRXD/

IOPC2

IOPC3

IOPC5

SPISTE/

SPISIMO/

SPISOMI/

TMS2

IOPC4

SPICLK/

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

pinouts (continued)

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

T1PWM/T1CMP/IOPB4

T2PWM/T2CMP/IOPB5

†‡

CCA

PLLV

PLLF

PDPINTA

PLLF2

DDO

SSO

TRST

IOPC4

TMS2

SPICLK/

PAG PACKAGE

IOPC3

IOPC2

IOPA1

SPISOMI/

SPISIMO/

SCIRXD/

(TOP VIEW)

IOPA0

XINT2/ADCSOC/IOPD0

SCITXD/

TCLKINA/IOPB7

PWM6/IOPB3

SSO

DDO

PWM5/IOPB2 PWM4/IOPB1

PWM3/IOPB0 PWM2/IOPA7 PWM1/IOPA6

CCP

TP1 TP2

CANRX/IOPC7

ADCIN03

ADCIN05

ADCIN04

32 3150 3051 2952 2853 27 2655 2556

2457 2358 2259 2160 2061 1962 1863

ADCIN02

TMS TDO

TDI

TCK

XTAL2 XTAL1/CLKIN

BOOT_EN/XF

SSA

CCA

REFHI

REFLO

ADCIN00 ADCIN01CANTX/IOPC6

47 46 45 44 4342 41 40 39 38 37 36 35 34

TMS320LF2403A PAG TMS320LC2403A PAG TMS320LC2402A PAG

64 17

234567 89101112131415

/IOPE0

CAP3/IOPA5

EMU0

EMU1/ OFF

SSO

DDO

ADCIN07

ADCIN06

CLKOUT

CAP2/QEP2/IOPA4

CAP1/QEP1/IOPA3

†

Bold, italicized pin names indicate pin function after reset.

‡

For LC2402A, the following pins are different from what is shown:

Pin 45: IOPC2 Pin 46: IOPC3 Pin 47: IOPC4 Pin 63: IOPC7 Pin 64: IOPC6

BOOT_EN is available only on flash devices.

On the ROM devices (LC240xA), V

is a No Connect (NC).

CCP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pinouts (continued)

IOPD0

IOPB5

†

IOPB4

PG PACKAGE

(TOP VIEW)

DDO

PWM5/IOPB2 PWM4/IOPB1

PWM3/IOPB0

PWM2/IOPA7 PWM1/IOPA6

CCP

TP1 TP2

IOPC7 IOPC6

SSO

IOPB7

IOPB3

TCLKINA/

PWM6/

TMS2

IOPC4

IOPC2

IOPC3

IOPA1

IOPA0

XINT2/ADCSOC/

SCITXD/

SCIRXD/

CCA

T1PWM/T1CMP/

T2PWM/T2CMP/

PLLV

PLLF2

PLLF

SSO

DDO

PDPINTA

TRST

3351 343550 49 48 47 46 45 44 43 42 41 40 39 38 37 36

52 53 54

56 57

TMS320LC2402A PG TMS320LF2402A PG

61 62 63 64

32 31

30 29 28 27 26 25 24 23 22 21 20

TMS TDO

TDI TCK RS V

XTAL2 XTAL1/CLKIN BOOT_EN/XF V

SSA

CCA

REFHI

‡

191 2 3 4 5 6 7 8 9101112131415161718

VDDV

OFF

SSO

DDO

IOPA5

/IOPE0

CAP3/

IOPA4

IOPA3

EMU0

EMU1/

ADCIN05

ADCIN06

ADCIN07

ADCIN02

ADCIN03

ADCIN04

REFLO

ADCIN00

ADCIN01

CLKOUT

CAP1/QEP1/

CAP2/QEP2/

†

Bold, italicized pin names indicate pin function after reset.

‡

BOOT_EN is available only on Flash devices.

On the ROM devices (LC240xA), V

is a No Connect (NC).

CCP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions

The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A device. Table 2 lists the signals available in the 240xA generation of devices.

Table 2. LF240xA and LC240xA Pin List and Package Options

2403A,

PIN NAME

CAP1/QEP1/IOPA3 83 57 57 4

CAP2/QEP2/IOPA4 79 55 55 3

CAP3/IOPA5 75 52 52 2 Capture input #3 (EVA) or GPIO (↑) PWM1/IOPA6 56 39 39 59 Compare/PWM output pin #1 (EVA) or GPIO (↑) PWM2/IOPA7 54 37 37 58 Compare/PWM output pin #2 (EVA) or GPIO (↑) PWM3/IOPB0 52 36 36 57 Compare/PWM output pin #3 (EVA) or GPIO (↑) PWM4/IOPB1 47 33 33 54 Compare/PWM output pin #4 (EVA) or GPIO (↑) PWM5/IOPB2 44 31 31 53 Compare/PWM output pin #5 (EVA) or GPIO (↑) PWM6/IOPB3 40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO (↑) T1PWM/T1CMP/IOPB4 16 12 12 40 Timer 1 compare output (EVA) or GPIO (↑) T2PWM/T2CMP/IOPB5 18 13 13 41 Timer 2 compare output (EVA) or GPIO (↑)

TDIRA/IOPB6 14 11 11

TCLKINA/IOPB7 37 26 26 49

CAP4/QEP3/IOPE7 88 60 60

CAP5/QEP4/IOPF0 81 56 56

CAP6/IOPF1 69 48 48 Capture input #6 (EVB) or GPIO (↑) PWM7/IOPE1 65 45 45 Compare/PWM output pin #7 (EVB) or GPIO (↑) PWM8/IOPE2 62 43 43 Compare/PWM output pin #8 (EVB) or GPIO (↑) PWM9/IOPE3 59 41 41 Compare/PWM output pin #9 (EVB) or GPIO (↑) PWM10/IOPE4 55 38 38 Compare/PWM output pin #10 (EVB) or GPIO (↑) PWM11/IOPE5 46 32 32 Compare/PWM output pin #11 (EVB) or GPIO (↑) PWM12/IOPE6 38 27 27 Compare/PWM output pin #12 (EVB) or GPIO (↑)

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

LF2407A

(144-PGE)

CCA

, VSS, or V

DDO

2406A

(100-PZ)

be isolated from the digital supply voltage (and V

SSO

LC2404A

(100-PZ)

EVENT MANAGER A (EVA)

EVENT MANAGER B (EVB)

) should be left unconnected. All power supply pins must be connected appropriately for proper

LC2402A (64-PAG)

and

2402A

(64-PG)

DESCRIPTION

Capture input #1/quadrature encoder pulse input #1 (EVA) or GPIO (↑)

Capture input #2/quadrature encoder pulse input #2 (EVA) or GPIO (↑)

Counting direction for general-purpose (GP) timer (EVA) or GPIO. If TDIRA = 1, upward counting is selected. If TDIRA = 0, downward counting is selected. (↑)

External clock input for GP timer (EVA) or GPIO. Note that the timer can also use the internal device clock. (↑)

Capture input #4/quadrature encoder pulse input #3 (EVB) or GPIO (↑)

Capture input #5/quadrature encoder pulse input #4 (EVB) or GPIO (↑)

from digital ground) to maintain the specified accuracy

SSA

†‡

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A, LC2402A (64-PAG)

and

2402A

(64-PG)

SSA

DESCRIPTION

Counting direction for general-purpose (GP) timer (EVB) or GPIO. If TDIRB = 1, upward counting is selected. If TDIRB = 0, downward counting is selected. (↑)

External clock input for GP timer (EVB) or GPIO. Note that the timer can also use the internal device clock. (↑)

from digital ground) to maintain the specified accuracy

PIN NAME

LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

EVENT MANAGER B (EVB) (CONTINUED)

T3PWM/T3CMP/IOPF2 8 7 7 Timer 3 compare output (EVB) or GPIO (↑) T4PWM/T4CMP/IOPF3 6 5 5 Timer 4 compare output (EVB) or GPIO (↑)

TDIRB/IOPF4 2 2 2

TCLKINB/IOPF5 126 89 89

ANALOG-TO-DIGITAL CONVERTER (ADC)

ADCIN00 112 79 79 18 Analog input #0 to the ADC

ADCIN01 110 77 77 17 Analog input #1 to the ADC

ADCIN02 107 74 74 16 Analog input #2 to the ADC

ADCIN03 105 72 72 15 Analog input #3 to the ADC

ADCIN04 103 70 70 14 Analog input #4 to the ADC

ADCIN05 102 69 69 13 Analog input #5 to the ADC

ADCIN06 100 67 67 12 Analog input #6 to the ADC

ADCIN07 99 66 66 11 Analog input #7 to the ADC

ADCIN08 113 80 80 Analog input #8 to the ADC

ADCIN09 111 78 78 Analog input #9 to the ADC

ADCIN10 109 76 76 Analog input #10 to the ADC

ADCIN11 108 75 75 Analog input #11 to the ADC

ADCIN12 106 73 73 Analog input #12 to the ADC

ADCIN13 104 71 71 Analog input #13 to the ADC

ADCIN14 101 68 68 Analog input #14 to the ADC

ADCIN15 98 65 65 Analog input #15 to the ADC

REFHI

REFLO

CCA

SSA

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V

CCA

DDO

, VSS, or V

115 82 82 20 ADC analog high-voltage reference input

114 81 81 19 ADC analog low-voltage reference input

116 83 83 21 Analog supply voltage for ADC (3.3 V)

117 84 84 22 Analog ground reference for ADC

be isolated from the digital supply voltage (and V

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)

CANRX/IOPC7

CANTX/IOPC6

SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO (↑)

SCIRXD/IOPA1 26 18 18 44

SPICLK/IOPC4

SPISIMO/IOPC2

SPISOMI/IOPC3

SPISTE/IOPC5

CANRX 70 49 − 63 CAN receive data or GPIO (LF2403A) (↑)

IOPC7 70 49 49 63 GPIO only (2402A) (↑)

CANTX 72 50 − 64 CAN transmit data or GPIO (LF2403A) (↑)

IOPC6 72 50 50 64 GPIO only (2402A) (↑)

SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) (↑) IOPC4 35 24 24 47 GPIO only (2402A) (↑) SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) (↑) IOPC2 30 21 21 45 GPIO only (2402A) (↑) SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) (↑) IOPC3 32 22 22 46 GPIO only (2402A) (↑)

SPISTE 33 23 23 −

IOPC5 33 23 23 −

LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

EXTERNAL INTERRUPTS, CLOCK

LC2402A (64-PAG)

and

2402A

(64-PG)

DESCRIPTION

SCI asynchronous serial port receive data or or GPIO (↑)

SPI slave transmit-enable (optional) or GPIO (↑)

Device Reset (in) and Watchdog Reset (out).

Device reset. RS causes the device to terminate execution and to set PC = 0. When RS execution begins at location 0x0000 of program memory.

RS 133 93 93 28

PDPINTA 7 6 6 36

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

be isolated from the digital supply voltage (and V

CCA

, VSS, or V

DDO

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the RS low for the watchdog reset duration of 128 CLKIN cycles.

The output buffer of this pin is an open-drain with an internal pullup (20 µA, typical). It is recommended that this pin be driven by an open-drain device. (↑)

Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVA) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINTA

from digital ground) to maintain the specified accuracy

SSA

is a falling-edge-sensitive interrupt. (↑)

is brought to a high level,

pin will be driven

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

BOOT_EN /

during reset and then driven as an output signal for XF. After

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

XINT1/IOPA2 23 16 16

XINT2/ADCSOC/IOPD0 21 15 15 42

CLKOUT/IOPE0 73 51 51 1

PDPINTB 137 95 95

XTAL1/CLKIN 123 87 87 24

XTAL2 124 88 88 25

PLLV

CCA

IOPF6 131 92 92 General-purpose I/O (↑)

BOOT_EN 121 86 − 23

BOOT_EN / XF

XF 121 86 86 23

PLLF 11 9 9 38 PLL loop filter input 1

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

LF2407A

(144-PGE)

12 10 10 39 PLL supply (3.3 V)

be isolated from the digital supply voltage (and V

CCA

, VSS, or V

DDO

2406A

(100-PZ)

EXTERNAL INTERRUPTS, CLOCK (CONTINUED)

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

LC2404A

(100-PZ)

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. (↑)

External user interrupt 2 and ADC start of conversion or GPIO. External “start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is programmable. (↑)

Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14) of the system control and status register (SCSR). This pin can be used as a GPIO if not used as a clock output pin. (↑)

Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins (EVB) in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINTB

PLL oscillator input pin. Crystal input to PLL/clock source input to PLL. XTAL1/CLKIN is tied to one side of a reference crystal.

Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference crystal. This pin goes in the high-impedance state when EMU1/OFF

Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN

reset and then driven as an output signal for XF. After

durin reset, XF is driven high. ROM devices do not have boot ROM, hence, no BOOT_EN modes. The BOOT_EN must be driven with a passive circuit only. (↑)

from digital ground) to maintain the specified accuracy

SSA

is a falling-edge-sensitive interrupt. (↑)

) to update SCSR2.3 (BOOT_EN bit)

is active low.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

PLLF2 10 8 8 37 PLL loop filter input 2

(5V) 58 40 40 60

CCP

TP1 60 42 42 61 Test pin 1. Do not connect.

TP2 63 44 44 62 Test pin 2. Do not connect.

BIO/IOPC1 119 85 85

EMU0 90 61 61 7

EMU1/OFF 91 62 62 8

TCK 135 94 94 29 JTAG test clock with internal pullup (↑)

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

LF2407A

(144-PGE)

OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)

CCA

, VSS, or V

DDO

2406A

(100-PZ)

be isolated from the digital supply voltage (and V

SSO

LC2404A

(100-PZ)

) should be left unconnected. All power supply pins must be connected appropriately for proper

LC2402A (64-PAG)

and

2402A

(64-PG)

Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e., during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series with the 5-V supply on this pin. This pin is a “no connect” (NC) on ROM parts (i.e., this pin is not connected to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference on ROM parts.

Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO it should be pulled high. This pin is configured as a branch control input by all device resets. It can be used as a GPIO, if not used as a branch control input. (↑)

EMULATION AND TEST

Emulator I/O #0 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. (↑)

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST is driven low, this pin is configured as OFF high-impedance state. Note that OFF testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF apply: TRST EMU0 = 1 EMU1/OFF

DESCRIPTION

is low, a branch is executed. If BIO is not used,

. EMU1/OFF, when active low, puts all output drivers in the

= 0

= 0 (↑)

from digital ground) to maintain the specified accuracy

SSA

is used exclusively for

condition, the following

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

TDI 139 96 96 30

TDO 142 99 99 31

TMS 144 100 100 32

TMS2 36 25 25 48

LF2407A

(144-PGE)

2406A

(100-PZ)

EMULATION AND TEST (CONTINUED)

LC2404A

(100-PZ)

LC2402A (64-PAG)

and

2402A

(64-PG)

DESCRIPTION

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. (↓)

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)

JTAG test-mode select 2 (TMS2) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. Used for test and emulation only. This pin can be left unconnected in user applications. If the PLL bypass mode is desired, TMS2, TMS, and TRST held low during reset. (↑)

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. (↓)

should be

NOTE: Do not use pullup resistors on TRST an internal pulldown device. TRST

TRST 1 1 1 33

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

be isolated from the digital supply voltage (and V

CCA

DDO

, VSS, or V

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application−specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I ↓)

from digital ground) to maintain the specified accuracy

SSA

is an active high

; it has

may be left floating. In other

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

interface. It is normally low, unless a memory write

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A, LC2402A (64-PAG)

and

2402A

(64-PG)

SSA

Data space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.

I/O space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.

Program space strobe. IS, DS, and PS are always high unless low-level asserted for access to the relevant external memory space or I/O. They are placed in the high-impedance state.

Read/write qualifier signal. R/W indicates transfer direction during communication to an external device. It is normally in read mode (high), unless low level is asserted for performing a write operation. R/W

state.

Write/Read qualifier or GPIO. This is an inverted R/W

signal useful for zero-wait-state memory interface. It is normall operation is performed. See Table 12, Port C

section, for reset note regarding LF2406A and LF2402A. (↑)

Read-enable strobe. Read-select indicates an active, external read cycle. RD external program, data, and I/O reads. RD placed in the high-impedance state.

Write-enable strobe. The falling edge of WE indicates that the device is driving the external data bus (D15− D0). WE program, data, and I/O writes. WE high-impedance state.

External memory access strobe. STRB is always high unless asserted low to indicate an external bus cycle. STRB is active for all off-chip accesses. STRB

state.

from digital ground) to maintain the specified accuracy

PIN NAME

LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS

DS 87

IS 82

PS 84

R/W 92

W/R 19

W/R / IOPC0

IOPC0 19 14 14

RD 93

WE 89

STRB 96

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V

be isolated from the digital supply voltage (and V

CCA

, VSS, or V

DDO

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

DSP CONTROLLERS

DESCRIPTION

is placed in the high-impedance

low, unless a memory write

is active on all

is active on all external

is placed in the high-impedance

is placed in the

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

READY 120

MP/MC 118

ENA_144 122

VIS_OE 97

A0 80 Bit 0 of the 16-bit address bus

A1 78 Bit 1 of the 16-bit address bus

A2 74 Bit 2 of the 16-bit address bus

A3 71 Bit 3 of the 16-bit address bus

A4 68 Bit 4 of the 16-bit address bus

A5 64 Bit 5 of the 16-bit address bus

A6 61 Bit 6 of the 16-bit address bus

A7 57 Bit 7 of the 16-bit address bus

A8 53 Bit 8 of the 16-bit address bus

A9 51 Bit 9 of the 16-bit address bus

A10 48 Bit 10 of the 16-bit address bus

A11 45 Bit 11 of the 16-bit address bus

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

LF2407A

(144-PGE)

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

CCA

, VSS, or V

DDO

2406A

(100-PZ)

be isolated from the digital supply voltage (and V

SSO

LC2404A

(100-PZ)

) should be left unconnected. All power supply pins must be connected appropriately for proper

LC2402A (64-PAG)

and

2402A

(64-PG)

DESCRIPTION

READY is pulled low to add wait states for external accesses. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready, it pulls the READY pin low. The processor waits one cycle and checks READY again. Note that the processor performs READY-detection if at least one software wait state is programmed. To meet the external READY timing parameters, the wait-state generator control register (WSGR) should be programmed for at least one wait state. (↑)

Microprocessor/Microcomputer mode select. If this pin is low during reset, the device is put in microcomputer mode and program execution begins at 0000h of internal program memory (Flash EEPROM). A high value during reset puts the device in microprocessor mode and program execution begins at 0000h of external program memory. This line sets the MP/MC in the SCSR2 register). (↓)

Active high to enable external interface signals. If pulled low, the 2407A behaves like the 2406A/2403A/2402A—i.e., it has no external memory and generates an illegal address if DS asserted. This pin has an internal pulldown. (↓)

Visibility output enable (active when data bus is output). This pin is active (low) whenever the external data bus is driving as an output during visibility mode. Can be used by external decode logic to prevent data bus contention while running in visibility mode.

from digital ground) to maintain the specified accuracy

SSA

bit (bit 2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

I/O buffer supply +3.3 V. Digital logic and buffer supply

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A,

PIN NAME

A12 43 Bit 12 of the 16-bit address bus

A13 39 Bit 13 of the 16-bit address bus

A14 34 Bit 14 of the 16-bit address bus

A15 31 Bit 15 of the 16-bit address bus D0 127 Bit 0 of 16-bit data bus (↑) D1 130 Bit 1 of 16-bit data bus (↑) D2 132 Bit 2 of 16-bit data bus (↑) D3 134 Bit 3 of 16-bit data bus (↑) D4 136 Bit 4 of 16-bit data bus (↑) D5 138 Bit 5 of 16-bit data bus (↑) D6 143 Bit 6 of 16-bit data bus (↑) D7 5 Bit 7 of 16-bit data bus (↑) D8 9 Bit 8 of 16-bit data bus (↑) D9 13 Bit 9 of 16-bit data bus (↑) D10 15 Bit 10 of 16-bit data bus (↑) D11 17 Bit 11 of 16-bit data bus (↑) D12 20 Bit 12 of 16-bit data bus (↑) D13 22 Bit 13 of 16-bit data bus (↑) D14 24 Bit 14 of 16-bit data bus (↑) D15 27 Bit 15 of 16-bit data bus (↑)

DDO

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

LF2407A

(144-PGE)

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

29 20 20 6

50 35 35 27

86 59 59 56

129 91 91

4 4 4 10

42 30 30 35

67 47 47 52

77 54 54

95 64 64

141 98 98

CCA

, VSS, or V

DDO

2406A

(100-PZ)

be isolated from the digital supply voltage (and V

SSO

LC2404A

(100-PZ)

) should be left unconnected. All power supply pins must be connected appropriately for proper

LC2402A (64-PAG)

and

2402A

(64-PG)

POWER SUPPLY

DESCRIPTION

Core supply +3.3 V. Digital logic supply voltage.

I/O buffer supply +3.3 V. Digital logic and buffer supply voltage.

from digital ground) to maintain the specified accuracy

SSA

DSP CONTROLLERS

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

SSO

I/O buffer ground. Digital logic and buffer ground reference.

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

2403A, LC2402A (64-PAG)

and

2402A

(64-PG)

DESCRIPTION

Core ground. Digital logic ground reference.

I/O buffer ground. Digital logic and buffer ground reference.

from digital ground) to maintain the specified accuracy

SSA

PIN NAME

LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

POWER SUPPLY (CONTINUED)

28 19 19 5

49 34 34 26

85 58 58 55

128 90 90

3 3 3 9

41 29 29 34

66 46 46 51

SSO

76 53 53

94 63 63

125 97 97

140

†

Bold, italicized pin names indicate pin function after reset.

‡

GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

It is highly recommended that V and improve the noise immunity of the ADC.

Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

No power supply pin (VDD, V

be isolated from the digital supply voltage (and V

CCA

DDO

, VSS, or V

) should be left unconnected. All power supply pins must be connected appropriately for proper

SSO

device operation. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory maps

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

Hex Program

0000

0FFF

1000

3FFF 4000

6FFF

7000

7FFF

8000

87FF 8800

FDFF FE00

FEFF FF00

FFFF

Flash Sector 0 (4K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

On-Chip DARAM (B0)

†

(0040−0043h)

Flash Sector 1 (12K)

Flash Sector 2 (12K)

Flash Sector 3 (4K)

SARAM (2K) Internal (PON = 1) External (PON=0)

External

Reserved‡ (CNF = 1)

External (CNF = 0)

‡

(CNF = 1)

Hex Data

0000

005F 0060

007F

0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

0FFF 1000

6FFF

7000

7FFF

8000

FFFF

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (2K)

Internal (DON = 1)

Reserved (DON=0)

Illegal

Peripheral Memory-Mapped Registers (System, WD, ADC, SCI, SPI, CAN, I/O, Interrupts)

External

Hex I/O

0000

External

FEFF

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Flash Control Mode Register

Wait-State Generator Control

Reserved

On-Chip Flash Memory (Sectored) − if MP/MC = 0 External Program Memory − if MP/MC

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†

Addresses 0040h−0043h in on-chip program memory are reserved for code security passwords.

‡

When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved when CNF = 1.

When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example, a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.

Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.

= 1

SARAM (See Table 1 for details.)

Reserved or Illegal

Figure 1. TMS320LF2407A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

memory maps (continued)

Hex Program

0000

Flash Sector 0 (4K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

0FFF

1000

3FFF

4000

6FFF

7000

7FFF

8000

87FF

8800

FDFF FE00

FEFF FF00

On-Chip DARAM (B0)

FFFF

†

(0040−0043h)

Flash Sector 1 (12K)

Flash Sector 2 (12K)

Flash Sector 3 (4K)

SARAM (2K) Internal (PON = 1) Reserved (PON=0)

Illegal

Reserved

External (CNF = 0)

‡

(CNF = 1)

Hex Data

0000

005F 0060 007F 0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

FFFF

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (2K)

Internal (DON = 1)

Reserved (DON = 0)

Illegal

Peripheral Memory-Mapped Registers (System, WD, ADC, SCI, SPI, CAN, I/O, Interrupts)

Illegal

Hex I/O

0000

Illegal

FEFF

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Flash Control Mode Register

Reserved

On-Chip Flash Memory (Sectored)

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

SARAM (See Table 1 for details.)

Reserved or Illegal

Figure 2. TMS320LF2406A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

ИИИИИИИИИ

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

memory maps (continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

Hex

0000

0FFF

1000

3FFF

4000

7FFF

8000

81FF

8200

87FF

8800

Program

Flash Sector 0 (4K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

†

(0040−0043h)

Flash Sector 1 (12K)

Reserved

SARAM (512 words)

Internal (PON = 1)

Reserved (PON = 0)

Reserved

Hex Data

0000

005F 0060 007F 0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

07FF

0800

SARAM (512 words)

Internal (DON = 1)

Reserved (DON = 0)

09FF 0A00

Reserved

0FFF

1000

6FFF

7000

Peripheral Memory-Mapped

Illegal

Registers (System, WD, ADC,

7FFF

8000

SCI, I/O, Interrupts)

Hex I/O

0000

Illegal

FDFF

FDFF FE00

FE00

FEFF

FEFF FF00

FF00

On-Chip DARAM (B0)

FFFF

On-Chip Flash Memory (Sectored)

Illegal

Reserved

‡

(CNF = 1)

Reserved (CNF = 0)

Illegal

FFFF

FEFF

FF00

FF0E

FF0F

FF10

FFFE

Flash Control Mode Register

Reserved

FFFF

SARAM (See Table 1 for details.)

Reserved or Illegal

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

Figure 3. TMS320LF2403A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

memory maps (continued)

Hex

0000

0FFF

1000

1FFF

2000

7FFF

8000

81FF

8200

87FF

8800

Program

Flash Sector 0 (4K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

†

(0040−0043h)

Flash Sector 1 (4K)

Reserved

SARAM (512 words)

Internal (PON = 1)

Reserved (PON = 0)

Reserved

Hex Data

0000

005F 0060 007F 0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

09FF

0A00

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (512 words)

Internal (DON = 1)

Reserved (DON = 0)

Reserved

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

Hex I/O

0000

Illegal

FDFF

FDFF FE00

FE00

Reserved

FEFF

FEFF FF00

FF00

On-Chip DARAM (B0)

Reserved (CNF = 0)

FFFF

On-Chip Flash Memory (Sectored)

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

(CNF = 1)

FFFF

Illegal

FEFF

FF00

FF0E

FF0F

FF10

FFFE

FFFF

Flash Control Mode Register

SARAM (See Table 1 for details.)

Reserved or Illegal

Reserved

Figure 4. TMS320LF2402A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

memory maps (continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

Hex

0000

7FBF

7FC0

7FFF

8000

87FF

8800

Program

On-Chip ROM (32K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

†

(0040−0043h)

Reserved

SARAM (2K)

Internal (PON = 1)

Reserved (PON = 0)

Hex Data

0000

005F 0060 007F

0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (2K)

Internal (DON = 1)

Reserved (DON = 0)

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, CAN, I/O, Interrupts)

Illegal

Reserved

Illegal

FDFF FE00

Reserved

FEFF FF00

On-Chip DARAM (B0)‡ (CNF = 1)

Reserved (CNF = 0)

FFFF

On-Chip ROM memory

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

FFFF

SARAM (See Table 1 for details.)

Reserved or Illegal

Figure 5. TMS320LC2406A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

memory maps (continued)

Hex

0000

3FBF 3FC0

3FFF

4000

7FFF

8000

83FF

8400

Program

On-Chip ROM (16K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

†

(0040−0043h)

Reserved

SARAM (1K)

Internal (PON = 1)

Reserved (PON = 0)

Reserved

Hex Data

0000

005F 0060

007F 0080 00FF 0100

01FF 0200

02FF 0300

03FF 0400

04FF

0500 07FF

0800

0BFF

0C00

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (1K)

Internal (DON = 1)

Reserved (DON = 0)

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, SPI, I/O, Interrupts)

Illegal

FDFF FE00

Reserved

FEFF FF00

On-Chip DARAM (B0)‡ (CNF = 1)

Reserved (CNF = 0)

FFFF

On-Chip ROM memory

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

FFFF

SARAM (See Table 1 for details.)

Reserved or Illegal

Figure 6. TMS320LC2404A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

memory maps (continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

Hex

0000

3FBF

3FCO

3FFF

4000

7FFF

8000

81FF

8200

87FF

8800

Program

On-chip ROM (16K)

Interrupt Vectors (0000−003Fh) Reserved

User code begins at 0044h

†

(0040−0043h)

Reserved

SARAM (512 words)

Internal (PON = 1)

Reserved (PON = 0)

Reserved

Hex Data

0000

005F 0060 007F 0080

00FF

0100

01FF

0200

02FF

0300

03FF

0400

04FF

0500

07FF

0800

09FF 0A00

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

SARAM (512 words)

Internal (DON = 1)

Reserved (DON = 0)

Reserved

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

Illegal

FDFF FE00

Reserved

FEFF

FF00

FFFF

On-Chip Flash Memory (Sectored)

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

On-Chip DARAM (B0)‡ (CNF = 1)

Reserved (CNF = 0)

‡

FFFF

Illegal

SARAM (See Table 1 for details.)

Reserved or Illegal

Figure 7. TMS320LC2403A Memory Map

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

memory maps (continued)

Hex

0000

17BF 17C0 17FF

1800 7FFF

8000

87FF

8800

Program

On-Chip ROM (6K)

Interrupt Vectors (0000−003Fh) Reserved User code begins at 0044h

†

(0040−0043h)

Reserved

Hex Data

0000

005F 0060 007F 0080 00FF 0100

01FF 0200

02FF 0300 03FF 0400 04FF 0500 07FF 0800

0FFF

1000

6FFF

7000

7FFF

8000

Memory-Mapped

Registers/Reserved Addresses

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM (B0)§ (CNF = 0)

Reserved (CNF = 1)

On-Chip DARAM (B1)

Reserved

Illegal

Reserved

Illegal

Peripheral Memory-Mapped

Registers (System, WD, ADC,

SCI, I/O, Interrupts)

Illegal

FDFF FE00

Reserved

FEFF

FF00

On-Chip DARAM (B0)

Reserved (CNF = 0)

FFFF

On-Chip ROM memory

†

Addresses 0040h−0043h in program memory are reserved for code security passwords.

‡

(CNF = 1)

FFFF

Reserved or Illegal

Figure 8. TMS320LC2402A Memory Map

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TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

peripheral memory map of the 2407A/2406A

Hex 0000

005F 0060

007F 0080

00FF 0100

01FF 0200

02FF 0300

03FF 0400

04FF 0500

07FF 0800

0FFF 1000

6FFF 7000

73FF 7400

743F 7440

74FF 7500

753F 7540

77EF 77F0

77F3 77F4

77FF 7800 7FFF 8000

FFFF

Illegal

Reserved

†

Available in LF2407A only

Memory-Mapped Registers

and Reserved

On-Chip DARAM B2

Illegal

Reserved

On-Chip DARAM B0

On-Chip DARAM B1

Reserved

Illegal

SARAM (2K)

Illegal

Peripheral Frame 1 (PF1)

Peripheral Frame 2 (PF2)

Illegal

Peripheral Frame 3 (PF3)

Illegal

Code Security Passwords

Reserved

Illegal

External

“Illegal” indicates that access to these addresses causes a nonmaskable interrupt (NMI).

“Reserved” indicates addresses that are reserved for test.

†

SPRS145K − JULY 2000 − REVISED AUGUST 2005

Reserved

Interrupt-Mask Register

Reserved

Interrupt Flag Register

Emulation Registers

and Reserved

Illegal

System Configuration and

Control Registers

Watchdog Timer Registers

Illegal

SPI

SCI

Illegal

External-Interrupt Registers

Illegal

Digital I/O Control Registers

ADC Control Registers

Illegal

CAN Control Registers

Illegal

CAN Mailbox

Illegal

Event Manager − EVA

General-Purpose

Timer Registers

Compare, PWM, and Deadband Registers

Capture and QEP Registers

Interrupt Mask, Vector and

Flag Registers

Illegal

Event Manager − EVB

General-Purpose

Timer Registers

Compare, PWM, and Deadband Registers

Capture and QEP Registers

Interrupt Mask, Vector, and

Flag Registers

Reserved

DSP CONTROLLERS

Hex 0000 0003 0004

0005

0006 0007

005F

7000−700F

7010−701F

7020−702F

7030−703F

7040−704F

7050−705F

7060−706F

7070−707F

7080−708F

7090−709F

70A0−70BF

70C0−70FF

7100−710E

710F−71FF

7200−722F

7230−73FF

7400−7408

7411−7419

7420−7429

742C−7431

7432−743F

7500−7508

7511−7519

7520−7529

752C−7531

7532−753F

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

device reset and interrupts

The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types of interrupt sources.

D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any

other executing functions. All maskable interrupts are disabled until the reset service routine enables them.

The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out (reset).

D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two

types:

− External interrupts are generated by one of four external pins corresponding to the interrupts XINT1, XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the CPU interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.

− Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A, event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPU IMR, which can mask each maskable interrupt line at the DSP core.

D Software-generated interrupts for the LF240xA devices include:

− The INTR instruction. This instruction allows initialization of any LF240xA interrupt with software. Its operand indicates the interrupt vector location to which the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1).

− The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only software activation is provided.

− The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts.

− An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.

Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to share the six core level interrupts. Figure 9 shows the PIE block diagram for hardware-generated interrupts.

The PIE block diagram (Figure 9) and the interrupt table (Table 3) explain the grouping and interrupt vector maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x − plus additional interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.

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device reset and interrupts (continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

PDPINTB

XINT2

PDPINTA

ADCINT

XINT1

SPIINT

RXINT

TXINT

CANMBINT

CANERINT

CMP1INT CMP2INT CMP3INT CMP4INT CMP5INT CMP6INT

T1PINT

T1CINT T1UFINT T1OFINT

T3PINT

T3CINT T3UFINT T3OFINT

T2PINT

T2CINT T2UFINT T2OFINT

T4PINT

T4CINT

T4UFINT

T4OFINT

CAP1INT CAP2INT CAP3INT

CAP4INT CAP5INT CAP6INT

SPIINT

RXINT

TXINT

CANMBINT

CANERINT

ADCINT

XINT1

Level 1

IRQ GEN

Level 2

IRQ GEN

Level 3

IRQ GEN

Level 4

IRQ GEN

Level 5

IRQ GEN

Level 6

IRQ GEN

PIE

IMR

IFR

INT1

INT2

CPU

INT3

INT4

INT5

INT6

IACK

PIVR & Logic

PIRQR# PIACK#

Addr BusData Bus

Indicates change with respect to the TMS320F243/F241/C242 data sheets.

Interrupts from external interrupt pins. The remaining interrupts are internal to the peripherals.

Figure 9. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts

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Power device protection

External interrupt pins in high

0002h 0004h

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

interrupt request structure

Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors

CPU

INTERRUPT

NAME

Reset 1

Reserved 2

NMI 3

PDPINTA 4 0.0 0020h Y EVA

PDPINTB 5 2.0 0019h Y EVB

ADCINT 6

XINT1 7 0.2 0001h Y

XINT2 8

SPIINT 9

RXINT 10

TXINT 11 0.6 0007h Y SCI

CANMBINT 12 0.7 0040 Y CAN

CANERINT 13 0.8 0041 Y CAN

CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt

CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt

CMP3INT 16 0.11 0023h Y EVA Compare 3 interrupt

T1PINT 17

T1CINT 18

T1UFINT 19

T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt

CMP4INT 21 2.1 0024h Y EVB Compare 4 interrupt

CMP5INT 22 2.2 0025h Y EVB Compare 5 interrupt

CMP6INT 23 2.3 0026h Y EVB Compare 6 interrupt

T3PINT 24 2.4 002Fh Y EVB Timer 3 period interrupt

T3CINT 25 2.5 0030h Y EVB Timer 3 compare interrupt

T3UFINT 26 2.6 0031h Y EVB Timer 3 underflow interrupt

T3OFINT 27 2.7 0032h Y EVB Timer 3 overflow interrupt

†

See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.

NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.

OVERALL PRIORITY

INTERRUPT

AND

VECTOR

ADDRESS

RSN

0000h

−

0026h

NMI

0024h

INT1

INT2

BIT POSITION IN PIRQRx AND

PIACKRx

0.1 0004h Y ADC

0.3 0011h Y

0.4 0005h Y SPI SPI interrupt pins in high priority

0.5 0006h Y SCI

0.12 0027h Y EVA Timer 1 period interrupt

0.13 0028h Y EVA Timer 1 compare interrupt

0.14 0029h Y EVA Timer 1 underflow interrupt

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

N/A N

N/A N CPU Emulator trap

N/A N

MASKABLE?

SOURCE

PERIPHERAL

MODULE

RS pin,

Watchdog

Nonmaskable

Interrupt

External

Interrupt Logic

External

Interrupt Logic

Reset from pin, watchdog timeout

Nonmaskable interrupt, software interrupt only

Power device protection interrupt pins

ADC interrupt in high-priority mode

External interrupt pins in high priority

SCI receiver interrupt in high-priority mode

SCI transmitter interrupt in high-priority mode

CAN mailbox in high-priority mode

CAN error interrupt in high-priority mode

DESCRIPTION

New peripheral interrupts and vectors with respect to the F243/F241 devices.

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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

INT3

INT4

000Ah

000Ch

External interrupt pins

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

interrupt request structure (continued)

Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors (Continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

CPU

INTERRUPT

NAME

T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt

T2CINT 29 1.1 002Ch Y EVA Timer 2 compare interrupt

T2UFINT 30 1.2 002Dh Y EVA Timer 2 underflow interrupt

T2OFINT 31

T4PINT 32

T4CINT 33 2.9 003Ah Y EVB Timer 4 compare interrupt

T4UFINT 34 2.10 003Bh Y EVB Timer 4 underflow interrupt

T4OFINT 35 2.11 003Ch Y EVB Timer 4 overflow interrupt

CAP1INT 36 1.4 0033h Y EVA Capture 1 interrupt

CAP2INT 37 1.5 0034h Y EVA Capture 2 interrupt

CAP3INT 38

CAP4INT 39

CAP5INT 40 2.13 0037h Y EVB Capture 5 interrupt

CAP6INT 41 2.14 0038h Y EVB Capture 6 interrupt

SPIINT 42 1.7 0005h Y SPI SPI interrupt (low priority)

RXINT 43 1.8 0006h Y SCI

TXINT 44

CANMBINT 45

CANERINT 46 1.11 0041h Y CAN

ADCINT 47 1.12 0004h Y ADC

XINT1 48

XINT2 49

Reserved 000Eh N/A Y CPU Analysis interrupt

TRAP N/A 0022h N/A N/A CPU TRAP instruction

Phantom Interrupt Vector

INT8−INT16 N/A 0010h−0020h N/A N/A CPU

INT20−INT31 N/A 00028h−0003Fh N/A N/A CPU

†

See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.

NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.

OVERALL

PRIORITY

N/A N/A 0000h N/A CPU Phantom interrupt vector

INTERRUPT

AND

VECTOR

ADDRESS

INT3

0006h

INT4

0008h

INT5

INT6

000Ch

BIT POSITION IN PIRQRx AND

PIACKRx

1.3 002Eh Y EVA Timer 2 overflow interrupt

2.8 0039h Y EVB Timer 4 period interrupt

1.6 0035h Y EVA Capture 3 interrupt

2.12 0036h Y EVB Capture 4 interrupt

1.9 0007h Y SCI

1.10 0040h Y CAN

1.13 0001h Y

1.14 0011h Y

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

MASK-

ABLE?

SOURCE

PERIPHERAL

MODULE

External

Interrupt Logic

External

Interrupt Logic

DESCRIPTION

SCI receiver interrupt (low-priority mode)

SCI transmitter interrupt (low-priority mode)

CAN mailbox interrupt (low-priority mode)

CAN error interrupt (low-priority mode)

ADC interrupt (low priority)

External interrupt pins (low-priority mode)

Software interrupt vectors

†

New peripheral interrupts and vectors with respect to the F243/F241 devices.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CPU core

The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See the functional block diagram of the 240xA DSP CPU for more information.

TMS320x240xA instruction set

The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control.

For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory.

addressing modes

The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register.

In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each page containing 128 words.

Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

scan-based emulation

TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardwaredevelopment support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The scan chain of these devices is useful for emulation function only.

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TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

functional block diagram of the 2407A DSP CPU

IS DS PS

A15−A0

D15−D0

R/W

STRB

READY

MP/MC

XINT[1−2]

Data Bus

Memory Map

GREG (16)

IMR (16)

IFR (16)

Control

MUXMUX

ARP(3)

ARB(3)

XTAL1 CLKOUT XTAL2

RD WE

1616

MUX

Data/Prog

DARAM

B0 (256 × 16)

MUX

FLASH EEPROM/

ROM

AR0(16)

AR1(16)

AR2(16)

AR3(16)

AR4(16)

AR5(16)

AR6(16)

AR7(16)

ARAU(16)

MUX

NPAR

PAR MSTACK

DP(9)

MUX

Data

DARAM

B2 (32 × 16)

B1 (256 × 16)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

Program Bus

Data Bus

MUX

Stack 8 × 16

Program Control

(PCTRL)

Data Bus

MUX

TREG0(16)

Multiplier

PREG(32)

PSCALE (−6, 0, 1, 4)

CALU(32)

ACCL(16)ACCH(16)C

OSCALE (0−7)

MUX

3232

MUX

7 LSB from IR

ISCALE (0−16)

Program Bus

1616

Program Bus

NOTES: A. See Table 4 for symbol descriptions.

B. For clarity, the data and program buses are shown as single buses although they include address and data bits.

C. See the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU

instruction set information.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

240xA legend for the internal hardware

Table 4. Legend for the 240xA DSP CPU Internal Hardware

SYMBOL NAME DESCRIPTION

ACC Accumulator

ARAU

AUX REGS

C Carry

CALU

DARAM Dual-Access RAM

GREG

IMR

IFR

INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.

ISCALE

MPY Multiplier

MSTACK Micro Stack

MUX Multiplexer Multiplexes buses to a common input

NPAR

OSCALE

PAR

PC Program Counter

PCTRL

Auxiliary Register Arithmetic Unit

Auxiliary Registers 0− 7

Central Arithmetic Logic Unit

Data Memory Page Pointer

Global Memory Allocation Register

Interrupt Mask Register

Interrupt Flag Register

Input Data-Scaling Shifter

Next Program Address Register

Output Data-Scaling Shifter

Program Address Register

Program Controller

32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift and rotate capabilities

An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs

These 16-bit registers are used as pointers to anywhere within the data space address range. They are operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used as an index value for AR updates of more than one and as a compare value to AR.

Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator shifts and rotates.

32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and provides status results to PCTRL.

If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM (DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2 are mapped to data memory space only, at addresses 0300−03FF and 0060−007F, respectively. Blocks 0 and 1 contain 256 words, while block 2 contains 32 words.

The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.

GREG specifies the size of the global data memory space. Since the global memory space is not used in the 240xA devices, this register is reserved.

IMR individually masks or enables the six core-level interrupts.

The 6-bit IFR indicates that the TMS320Lx240xA has latched an interrupt from one of the six maskable interrupts.

16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.

16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either signed or unsigned 2s-complement arithmetic multiply.

MSTACK provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space.

NPAR holds the program address to be driven out on the PAB in the next cycle.

16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data bus (DWEB).

PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle.

PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential data-transfer operations.

PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.

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TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

240xA legend for the internal hardware (continued)

Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued)

SYMBOL NAME DESCRIPTION

PREG Product Register 32-bit register holds results of 16 × 16 multiply

0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the

PSCALE

STACK Stack

TREG

Product-Scaling Shifter

Temporary Register

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines.

The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST) instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Figure 10 shows the organization of status registers ST0 and ST1, indicating all status bits contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status register field definitions.

additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the 32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle overhead.

STACK is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.

16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.

15 13 12 11 10 9 8 0

ST0 ARP OV OVM 1 INTM DP

15 131211109876543210

ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM

Figure 10. Organization of Status Registers ST0 and ST1

Table 5. Status Register Field Definitions

FIELD FUNCTION

ARB

ARP

CNF

Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.

Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.

Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch on the status of C. C is set to 1 on a reset.

On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instructions. RS

sets the CNF to 0.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

status and control registers (continued)

Table 5. Status Register Field Definitions (Continued)

FIELD FUNCTION

INTM

OVM

SXM

Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.

Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS

and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when

RS a maskable interrupt trap is taken.

Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.

Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset this bit, respectively. LST can also be used to modify the OVM.

Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS

Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.

Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can execute based on the condition of TC.

XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset by the CLRC XF instruction. XF is set to 1 by reset.

also sets INTM. INTM has no effect on the unmaskable

central processing unit

The TMS320x240xA central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. This section describes the CPU components and their functions. The functional block diagram shows the components of the CPU.

input scaling shifter

The TMS320x240xA provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.

The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros; the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit (sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to the system’s performance.

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multiplier

The TMS320x240xA devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier, as follow:

D 16-bit temporary register (TREG) that holds one of the operands for the multiplier

D 32-bit product register (PREG) that holds the product

Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.

Table 6. PSCALE Product-Shift Modes

PM SHIFT DESCRIPTION

00 No shift Product feed to CALU or data bus with no shift

01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product

10 Left 4

11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow

Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when using the multiply-by-a-13-bit constant

The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow.

The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication also can be performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining of the TREG load operations with CALU operations using the previous product. The pipeline operations that run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC (LTS).

Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN) logic, while the data addresses are generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes.

The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample.

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multiplier (continued)

The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value.

After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction.

central arithmetic logic unit

The TMS320x240xA central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.

The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.

The TMS320x240xA devices support floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is, floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG.

The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result in overflow.)

The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.

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central arithmetic logic unit (continued)

The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions.

The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation.

The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it.

Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset.

accumulator

The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16−31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0−15). When the postscaling shifter is used on the low word, the LSBs are zero-filled.

The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts.

auxiliary registers and auxiliary-register arithmetic unit (ARAU)

The 240xA provides a register file containing eight auxiliary registers (AR0−AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU.

The auxiliary register file (AR0 − AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.

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internal memory

The TMS320x240xA devices are configured with the following memory modules:

D Dual-access random-access memory (DARAM) D Single-access random-access memory (SARAM) D Flash D ROM D Boot ROM

dual-access RAM (DARAM)

There are 544 words × 16 bits of DARAM on the 240xA devices. The 240xA DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data memory) instructions allow dynamic configuration of the memory maps through software.

When using on-chip RAM, the 240xA runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the 240xA architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line or on-chip software wait-state generator can be used to interface the 2407A to slower, less expensive external memory.

single-access RAM (SARAM)

There are 2K words × 16 bits of SARAM on some of the 240xA devices.

†

The PON and DON bits select SARAM (2K) mapping in program space, data space, or both. See Table 19 for details on the SCSR2 register and the PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data spaces. The SARAM (starting at 8000h in program memory) is accessible in external memory space (for 2407A only), if the on-chip SARAM is not enabled.

flash EEPROM

Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile. However, it has the advantage of “in-target” reprogrammability. The LF2407A incorporates one 32K  16-bit Flash EEPROM module in program space. The Flash module has multiple sectors that can be individually protected while erasing or programming. The sector size is non-uniform and partitioned as 4K/12K/12K/4K sectors.

Unlike most discrete Flash memory, the LF240xA Flash does not require a dedicated state machine, because the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 algorithms and Flash code. This Flash requires 5 V for programming (at V

‡

(JTAG) scan port provides easy access to the on-chip RAM for downloading the

pin only) the array. The Flash runs

CCP

at zero wait state while the device is powered at 3.3 V.

ROM

The LC240xA devices contain mask-programmable ROM located in program memory space. Customers can arrange to have this ROM programmed with contents unique to any particular application. See Table 1 for the ROM memory capacity of each LC240xA device.

†

See Table 1 for device-specific features.

‡

IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.

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boot ROM (LF240xA only)

Boot ROM is a 256-word ROM memory-mapped in program space 0000−00FF. This ROM will be enabled if the BOOT_EN pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.3 bit and disabled by writing 1 to this bit.

The boot ROM has a generic bootloader to transfer code through SCI or SPI ports. The incoming code should disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not be enabled.

The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:

D If the SCITXD pin is pulled low, the PLL multiplier is set to 2. D If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default) D If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.

Care should be taken such that a combination of CLKIN and the PLL multiplication factor should not result in a CPU clock speed of greater than 40 MHz, the maximum rated speed.

Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI. See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more details about the bootloader operation.

pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN

flash/ROM security

240xA devices incorporate a security feature that prevents external access to program memory. This feature is useful in preventing unauthorized duplication of proprietary code.

If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken:

1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word “dummy” indicates that the destination address of this read is insignificant.

NOTE: Step 2 is not required if 40h−43h contain 0000 0000 0000 0000h or FFFF FFFF FFFF FFFFh.

2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h, 77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h, 41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle after the last instruction that unsecures the part.

Code Security Module Disclaimer

The Code Security Module (“CSM”) included on this device was designed to password protect the data stored in the associated memory (either ROM or Flash) and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI’s published specifications for the warranty period applicable for this device.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

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IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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PERIPHERALS

The integrated peripherals of the TMS320x240xA are described in the following subsections:

D Two event-manager modules (EVA, EVB) D Enhanced analog-to-digital converter (ADC) module D Controller area network (CAN) module D Serial communications interface (SCI) module D Serial peripheral interface (SPI) module D PLL-based clock module D Digital I/O and shared pin functions D External memory interfaces (LF2407A only) D Watchdog (WD) timer module

event manager modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 7 shows the module and signal names used. Table 7 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.

Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ.

Table 7. Module and Signal Names for EVA and EVB

EVENT MANAGER MODULES

GP Timers

Compare Units

Capture Units

QEP

External Inputs

MODULE SIGNAL MODULE SIGNAL

Timer 1 Timer 2

Compare 1 Compare 2 Compare 3

Capture 1 Capture 2 Capture 3

QEP1 QEP2

Direction

External Clock

EVA EVB

T1PWM/T1CMP T2PWM/T2CMP

PWM1/2 PWM3/4 PWM5/6

CAP1 CAP2 CAP3

QEP1 QEP2

TDIRA

TCLKINA

Timer 3 Timer 4

Compare 4 Compare 5 Compare 6

Capture 4 Capture 5 Capture 6

QEP3 QEP4

Direction

External Clock

T3PWM/T3CMP T4PWM/T4CMP

PWM7/8

PWM9/10

PWM11/12

CAP4 CAP5 CAP6

QEP3 QEP4

TDIRB

TCLKINB

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event manager modules (EVA, EVB) (continued)

240xA DSP Core

Data Bus ADDR Bus Reset

INT2,3,4

Clock

EV Control Registers

and Control Logic

GP Timer 1

Compare

GP Timer 1

Full-Compare

Units

GP Timer 2

Compare

GP Timer 2

Output

Logic

Prescaler

T1CON[8,9,10]T1CON[4,5]

SVPWM

33 3

State

Machine

Output

Logic

Deadband

Units

Output

Logic

Prescaler

ADC Start of Conversion

T1PWM/

T1CMP

†

TDIRA

TCLKINA

CLKOUT

(Internal)

PWM1

PWM6

T2PWM/

T2CMP

TCLKINA

CLKOUT

(Internal)

MUX

†

2402A devices do not support external direction control. TDIR is not available.

Capture Units

T2CON[4,5]

TDIRA

Figure 11. Event Manager A Block Diagram

QEP

Circuit

T2CON[8,9,10]

ClockDIR

CAPCONA[14,13]

CAP1/QEP1 CAP2/QEP2

CAP3

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general-purpose (GP) timers

There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

D A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

D A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes

D A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes

D A 16-bit timer-control register,TxCON, for reads or writes

D Selectable internal or external input clocks

D A programmable prescaler for internal or external clock inputs

D Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period

interrupts

D A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is

selected)

The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.

full-compare units

There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.

programmable deadband generator

The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register.

PWM waveform generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

PWM characteristics

Characteristics of the PWMs are as follows:

D 16-bit registers D Programmable deadband for the PWM output pairs, from 0 to 12 µs D Minimum deadband width of 25 ns D Change of the PWM carrier frequency for PWM frequency wobbling as needed D Change of the PWM pulse widths within and after each PWM period as needed D External-maskable power and drive-protection interrupts D Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space

vector PWM waveforms

D Minimized CPU overhead using auto-reload of the compare and period registers D The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx

signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.

− PDPINTA

− PDPINTB

capture unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.

Capture units include the following features:

pin status is reflected in bit 8 of COMCONA register.

pin status is reflected in bit 8 of COMCONB register.

D One 16-bit capture control register, CAPCONx (R/W)

D One 16-bit capture FIFO status register, CAPFIFOx

D Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

D Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

D Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs

are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]

D User-specified transition (rising edge, falling edge, or both edges) detection

D Three maskable interrupt flags, one for each capture unit

quadrature-encoder pulse (QEP) circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse).

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DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

input qualifier circuitry

An input-qualifier circuitry qualifies the input signal to the CAP1−6, QEP1−4, XINT1/2, ADCSOC and PDPINTA/B The state of the internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA

enhanced analog-to-digital converter (ADC) module

A simplified functional block diagram of the ADC module is shown in Figure 12. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

D 10-bit ADC core with built-in S/H

D 16-channel, MUXed inputs

D Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can

be programmed to select any 1 of 16 input channels

D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer

(i.e., two cascaded 8-state sequencers)

pins in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry).

, and XINT2/ADCSOC pins.

D Sixteen result registers (individually addressable) to store conversion values

− The digital value of the input analog voltage is derived by:

Digital Value = 0

Digital Value + 1024

Digital Value = 1023

Note: All fractional values are truncated.

Input Analog Voltage * V

* V

REFHI

REFLO

when input ≤ V

when V

when input ≥ V

REFLO

< input < V

REFHI

D Multiple triggers as sources for the start-of-conversion (SOC) sequence

− S/W − software immediate start

− EVA − Event manager A (multiple event sources within EVA)

− EVB − Event manager B (multiple event sources within EVB)

− Ext − External pin (ADCSOC)

D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

D Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize

conversions

D EVA and EVB triggers can operate independently in dual-sequencer mode

D Sample-and-hold (S/H) acquisition time window has separate prescale control

NOTE: The calibration and self-test features are not present in 240xA devices.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

enhanced analog-to-digital converter (ADC) module (continued)

The ADC module in the 240xA has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 10-bit ADC module with a total minimum conversion time of 375 ns (S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 12 shows the block diagram of the 240xA ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

ADCIN00

ADCIN07

ADCIN08

ADCIN15

ADCSOC

Result Registers

Sequencer 2

S/W

EVA

Analog MUX

10-Bit

ADC

Module

(375 ns MIN)

ADC Control Registers

Sequencer 1

Figure 12. Block Diagram of the 240xA ADC Module

Result Reg 0

Result Reg 1

Result Reg 7

Result Reg 8

Result Reg 15

70A8h

70AFh

70B0h

70B7h

SOCSOC

S/W

EVB

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (such as V

CCA

, V

REFHI

, and V

SSA

digital supply.

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) from the

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

controller area network (CAN) module

The CAN module is a full-CAN controller designed as a 16-bit peripheral module and supports the following features:

D CAN specification 2.0B (active)

− Standard data and remote frames

− Extended data and remote frames

D Six mailboxes for objects of 0- to 8-byte data length

− Two receive mailboxes, two transmit mailboxes

− Two configurable transmit/receive mailboxes

D Local acceptance mask registers for mailboxes 0 and 1 and mailboxes 2 and 3 D Configurable standard or extended message identifier D Programmable bit rate D Programmable interrupt scheme D Readable error counters D Self-test mode

− In this mode, the CAN module operates in a loop-back fashion, receiving its own transmitted message.

The CAN module is a 16-bit peripheral. The accesses are split into the control/status-registers accesses and the mailbox-RAM accesses.

CAN peripheral registers: The CPU can access the CAN peripheral registers only using 16-bit write accesses. The CAN peripheral always presents full 16-bit data to the CPU bus during read cycles.

CAN controller architecture

Figure 13 shows the basic architecture of the CAN controller through this block diagram of the CAN Peripherals.

CAN Module

Transmit Buffer

CAN Core

Temporary Receive Buffer

Data

Matchid

Acceptance Filter

CANTX

CANRX

CPU

Control/Status Registers

Interrupt Logic

CPU Interface/

Memory Management Unit

mailbox 0

mailbox 1

R T/R T/R T T

mailbox 2

mailbox 3

mailbox 4

mailbox 5

RAM 48x16

Control Bus

Control Logic

CAN

Transceiver

Figure 13. CAN Module Block Diagram

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40 C to 85 C

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

controller area network (CAN) module (continued)

The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN. The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and, therefore, inserts one wait state for the CPU.

Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1) 16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address bus.

Table 8. 3.3-V CAN Transceivers for the TMS320Lx240xA DSPs

PART NUMBER LOW-POWER MODE

SN65HVD230 370 µA standby mode Ye s Yes VP230

SN65HVD231 40 nA sleep mode Ye s Yes

SN65HVD232 No standby or sleep mode No No

†

This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number.

INTEGRATED

SLOPE CONTROL

PIN T

ref

−40°C to 85°C

MARKED AS

CAN interrupt logic

There are two interrupt requests from the CAN module to the peripheral interrupt expansion (PIE) controller: the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a low-priority request to the CPU. Since CAN mailboxes can generate multiple interrupts, the software should read the CAN_IFR register for every interrupt and prioritize the interrupt service, or else, these multiple interrupts will not be recognized by the CPU and PIE hardware logic. Each interrupt routine should service all the interrupt bits that are set and clear them after service.

†

VP231

VP232

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DSP CONTROLLERS

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serial communications interface (SCI) module

The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of the SCI module include:

D Two external pins:

− SCITXD: SCI transmit-output pin

− SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

D Baud rate programmable to 64K different rates

− Up to 2500 Kbps at 40-MHz CPUCLK

D Data-word format

− One start bit

− Data-word length programmable from one to eight bits

− Optional even/odd/no parity bit

− One or two stop bits

D Four error-detection flags: parity, overrun, framing, and break detection

D Two wake-up multiprocessor modes: idle-line and address bit

D Half- or full-duplex operation

D Double-buffered receive and transmit functions

D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with

status flags.

− Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and

TX EMPTY flag (transmitter-shift register is empty)

− Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

D Separate enable bits for transmitter and receiver interrupts (except BRKDT)

D NRZ (non-return-to-zero) format

D Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the

Figure 14 shows the SCI module block diagram.

register data is in the lower byte (7− 0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

serial communications interface (SCI) module (continued)

Frame Format and Mode

Parity

Even/Odd Enable

SCICCR.6 SCICCR.5

SCIHBAUD. 15 − 8

Baud Rate

Internal

Clock

SCILBAUD. 7 − 0

Baud Rate

MSbyte

LSbyte

TXWAKE

SCICTL1.3

WUT

SCITXBUF.7−0

Transmitter-Data

Buffer Register

TXSHF

SCI TX Interrupt

TXRDY

SCICTL2.7

TX EMPTY

SCICTL2.6

TXENA

SCICTL1.1

SCI Priority Level

Level 5 Int.

Level 1 Int.

Level 5 Int.

Level 1 Int.

TX INT ENA

SCICTL2.0

SCITXD

SCI TX

Priority

SCIPRI.6

SCI RX

Priority

SCIPRI.5

TXINT

External

Connections

SCITXD

RX ERR INT ENA

SCIRXST.7

RX Error

SCIRXD

RX/BK INT ENA

SCICTL2.1

RXWAKE

SCIRXST.1

SCICTL1.6

RX Error

SCIRXST.4− 2

RXSHF

RXENA

SCICTL1.0

Receiver-Data

SCIRXBUF.7−0

PEFE OE

Buffer

SCI RX Interrupt

RXRDY

SCIRXST.6

BRKDT

SCIRXST.5

Figure 14. Serial Communications Interface (SCI) Module Block Diagram

SCIRXD

RXINT

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DSP CONTROLLERS

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serial peripheral interface (SPI) module

Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

D Four external pins:

− SPISOMI: SPI slave-output/master-input pin

− SPISIMO: SPI slave-input/master-output pin

− SPISTE

− SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

: SPI slave transmit-enable pin

D Two operational modes: master and slave

D Baud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK

D Data word length: one to sixteen data bits

D Four clocking schemes (controlled by clock polarity and clock phase bits) include:

− Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

− Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

− Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

− Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

D Simultaneous receive and transmit operation (transmit function can be disabled in software)

D Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

D Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the

register data is in the lower byte (7 − 0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

serial peripheral interface (SPI) module (continued)

Figure 15 is a block diagram of the SPI in slave mode.

SPI Char

Internal Clock

SPIRXBUF.15 − 0

SPIRXBUF

Buffer Register

SPITXBUF.15 − 0

SPITXBUF

Buffer Register

SPIDAT

Data Register

SPIDAT.15 − 0

Talk

SPICTL.1

State Control

SPICCR.3 − 0

SPI Bit Rate

SPIBRR.6 − 0

456

Receiver

Overrun Flag

SPISTS.7

SPI INT FLAG

SPISTS.6

012

1230

Overrun INT ENA

SPICTL.4

SPI INT

ENA

SPICTL.0

SW1

SW2

To CPU

SW3

SPI Priority

SPIPRI.6

Master/Slave

SPICTL.2

Clock

Polarity

SPICCR.6 SPICTL.3

Clock

Phase

Level 1 INT

Level 5 INT

External

Connections

SPISIMO

SPISOMI

†

SPISTE

SPICLK

NOTE A: The diagram is shown in the slave mode.

†

The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. See the following errata for restrictions on using the SPISTE

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata

(literature number SPRZ002) TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185)

pin:

Figure 15. Four-Pin Serial Peripheral Interface Module Block Diagram

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SPI slave mode operation in LF2403A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

The LF2403A device does not have the SPISTE The following must be done to put the LF2403A SPI in slave mode:

1. Configure SPISTE

2. Configure SPISTE writing a 0 to bit 5 of PCDATDIR). Note that SPISTE configured and taken out of reset.

NOTE: The slave SPISTE are configured and taken out of reset. The initialization sequence is as follows:

a. The master SPI is configured first and taken out of reset. This ensures that the master SPICLK is

initialized to its appropriate level (high or low, depending on the polarity bit) first, before the slave SPI starts accepting clock pulses.

b. The slave SPI is configured and taken out of reset.

c. The GPIO/SPI pins of the slave is then configured for SPI operation and the SPISTE

driven low. This is done after ensuring the correct level of the master SPICLK signal. One method of doing this would be to read the level of the SPICLK pin through the PCDATDIR register and then deciding on the appropriate course of action.

d. SPI transmission may commence now. Transmission of data should not be attempted until both master

and slave are configured and the slave SPISTE

/IOPC5 signal for GPIO mode by clearing the MCRB.5 bit.

/IOPC5 signal as an output (by writing a 1 to bit 13 of PCDATDIR) and drive it low (by

/IOPC5 signal must not be driven low until after the master and slave SPI modules

/IOPC5 pin. (This function is available as an internal signal only.)

PLL-based clock module

/IOPC5 should not be driven low until after the SPI is

/IOPC5 signal is

/IOPC5 signal is driven low.

The 240xA has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different CPU clock rates. See Figure 16 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10 for the loop filter component values.

The PLL-based clock module provides two modes of operation:

D Crystal-operation

This mode allows the use of an external crystal/resonator to provide the time base to the device.

D External clock source operation

This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the XTAL1/CLKIN pin.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

PLL-based clock module (continued)

XTAL1/CLKIN

RESONATOR/

CRYSTAL

Figure 16. PLL Clock Module Block Diagram

XTAL2

PLLF

XTAL

OSC

PLLF2

PLL

3-bit

PLL Select

(SCSR1.[11:9])

CLKOUT

Table 9. PLL Clock Selection Through Bits (11−9) in SCSR1 Register

CLK PS2 CLK PS1 CLK PS0 CLKOUT

0 0 0 4 × F 0 0 1 2 × F 0 1 0 1.33 × F 0 1 1 1 × F 1 0 0 0.8 × F 1 0 1 0.66 × F 1 1 0 0.57 × F 1 1 1 0.5 × F

Default multiplication factor after reset is (1,1,1), i.e., 0.5 × Fin.

NOTE:

The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot ROM” section for more details.

external reference crystal clock option

The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown in Figure 17a. The crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 Ω −150 Ω and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF.

NOTE: Lx240xA crystal biasing needs an external 1 MΩ resistor across X1 and X2 pins for reliable operation. See the TMS320LF2407A,

LF2406A, LF2403A, LF2402A DSP Controllers Silicon Errata (literature number SPRZ002) or the TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185) for details on this requirement.

external reference oscillator clock option

The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input pin unconnected as shown in part b of Figure 17.

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external reference oscillator clock option (continued)

XTAL2XTAL1/CLKIN XTAL1/CLKIN XTAL2

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

Crystal

(see Note A)

NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The

(a) (b)

resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range.

(see Note A)

External Clock Signal

(Toggling 0− 3.3 V)

Figure 17. Recommended Crystal/Clock Connection

loop filter

The PLL module uses an external loop filter circuit for jitter minimization. The components for the loop filter circuit are R1, C1, and C2. The capacitors (C1 and C2) must be non-polarized. This loop filter circuit is connected between the PLLF and PLLF2 pins (see Figure 16). For examples of component values of R1, C1, and C2 at a specified oscillator frequency (XTAL1), see Table 10.

Table 10. Loop Filter Component Values With Damping Factor = 2.0

XTAL1/CLKIN FREQUENCY

(MHz)

4 4.7 3.9 0.082

5 5.6 2.7 0.056

6 6.8 1.8 0.039

7 8.2 1.5 0.033

8 9.1 1 0.022

9 10 0.82 0.015

10 11 0.68 0.015

11 12 0.56 0.012

12 13 0.47 0.01

13 15 0.39 0.0082

14 15 0.33 0.0068

15 16 0.33 0.0068

16 18 0.27 0.0056

17 18 0.22 0.0047

18 20 0.22 0.0047

19 22 0.18 0.0039

20 24 0.15 0.0033

R1 (Ω) (±5% TOLERANCE) C1 (µF) (±20% TOLERANCE) C2 (µF) (±20% TOLERANCE)

low-power modes

The 240xA has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if it is reset, or, if it receives an interrupt request.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

clock domains

All 240xA-based devices have two clock domains:

1. CPU clock domain − consists of the clock for most of the CPU logic

2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and the clock for the interrupt logic in the CPU.

When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues to run. This mode is also known as IDLE1 mode. The 240xA CPU also contains support for a second IDLE mode, IDLE2. By asserting IDLE2 to the 240xA CPU, both the CPU clock domain and the system clock domain are stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the oscillator and WDCLK are also shut down when in IDLE2 mode.

Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the IDLE instruction is executed (see Table 11). These bits are located in the System Control and Status Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357).

Table 11. Low-Power Modes Summary

LPMx BITS

LOW-POWER MODE

CPU running normally XX On On On On On On —

IDLE1 − (LPM0) 00 Off On On On On On

IDLE2 − (LPM1) 01 Off Off On On On On

HALT − (LPM2)

[PLL/OSC power down]

†

The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357).

SCSR1 [13:12]

1X Off Off Off Off Off Off

CPU

CLOCK

DOMAIN

SYSTEM

CLOCK

DOMAIN

WDCLK

STATUS

PLL

STATUS

OSC

STATUS

FLASH

POWER

†

EXIT

CONDITION

Peripheral

Interrupt,

External Interrupt,

Reset,

PDPINTA/B

Wakeup

Interrupts,

External Interrupt,

Reset,

PDPINTA/B

Reset,

PDPINTA/B

other power-down options

240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA. Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.

Depending on the application, these peripherals can be turned on/off to achieve low power.

See the SCSR1 register for details on the peripheral clock enable bits.

digital I/O and shared pin functions

The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:

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digital I/O and shared pin functions (continued)

D Output Control Registers — used to control the multiplexer selection that chooses between the primary

function of a pin or the general-purpose I/O function.

D Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.

description of shared I/O pins

The control structure for shared I/O pins is shown in Figure 18, where each pin has three bits that define its operation:

D MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.

D I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines

whether the pin is an input (0) or an output (1).

D I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected

is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.

The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.

IOP DIR Bit

0 = Input 1 = Output

Pullup

Pulldown

(Internal)

IOP Data Bit (Read/Write)

In Out

Primary

Function

or I/O Pin

Primary

Function

(Output Section)

Primary

Function

(Input Section)

MUX Control Bit

0 = I/O Function

1 = Primary Function

Figure 18. Shared Pin Configuration

A summary of shared pin configurations and associated bits is shown in Table 12.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

description of shared I/O pins (continued)

Table 12. Shared Pin Configurations

†

PIN FUNCTION SELECTED

(MCRx.n = 1)

(MCRX.N = 0)

Primary Function

I/O

MUX

CONTROL

(name.bit #)

MUX CONTROL

VALUE AT RESET

(MCRx.n)

I/O PORT DATA AND DIRECTION

‡

DIR BIT NO.

PORT A

SCITXD IOPA0 MCRA.0 0 PADATDIR 0 8

SCIRXD IOPA1 MCRA.1 0 PADATDIR 1 9

XINT1 IOPA2 MCRA.2 0 PADATDIR 2 10

CAP1/QEP1 IOPA3 MCRA.3 0 PADATDIR 3 11

CAP2/QEP2 IOPA4 MCRA.4 0 PADATDIR 4 12

CAP3 IOPA5 MCRA.5 0 PADATDIR 5 13

PWM1 IOPA6 MCRA.6 0 PADATDIR 6 14

PWM2 IOPA7 MCRA.7 0 PADATDIR 7 15

PORT B

PWM3 IOPB0 MCRA.8 0 PBDATDIR 0 8

PWM4 IOPB1 MCRA.9 0 PBDATDIR 1 9

PWM5 IOPB2 MCRA.10 0 PBDATDIR 2 10

PWM6 IOPB3 MCRA.11 0 PBDATDIR 3 11

T1PWM/T1CMP IOPB4 MCRA.12 0 PBDATDIR 4 12

T2PWM/T2CMP IOPB5 MCRA.13 0 PBDATDIR 5 13

TDIRA IOPB6 MCRA.14 0 PBDATDIR 6 14

TCLKINA IOPB7 MCRA.15 0 PBDATDIR 7 15

PORT C

W/R

IOPC0 MCRB.0 1 PCDATDIR 0 8

BIO IOPC1 MCRB.1 1 PCDATDIR 1 9

SPISIMO IOPC2 MCRB.2 0 PCDATDIR 2 10

SPISOMI IOPC3 MCRB.3 0 PCDATDIR 3 11

SPICLK IOPC4 MCRB.4 0 PCDATDIR 4 12

SPISTE IOPC5 MCRB.5 0 PCDATDIR 5 13

CANTX IOPC6 MCRB.6 0 PCDATDIR 6 14

CANRX IOPC7 MCRB.7 0 PCDATDIR 7 15

PORT D

XINT2/ADCSOC IOPD0 MCRB.8 0 PDDATDIR 0 8

EMU0 Reserved MCRB.9

EMU1 Reserved MCRB.10

TCK Reserved MCRB.11

TDI Reserved MCRB.12

TDO Reserved MCRB.13

TMS Reserved MCRB.14

TMS2 Reserved MCRB.15

†

Bold, italicized pin names indicate pin functions at reset.

‡

Valid only if the I/O function is selected on the pin

If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.

If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.

At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A), W/R

mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)

is reserved in these devices and must be written with a zero.

Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.

1 PDDATDIR 1 9

1 PDDATDIR 2 10

1 PDDATDIR 3 11

1 PDDATDIR 4 12

1 PDDATDIR 5 13

1 PDDATDIR 6 14

1 PDDATDIR 7 15

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description of shared I/O pins (continued)

Table 12. Shared Pin Configurations

SPRS145K − JULY 2000 − REVISED AUGUST 2005

†

(Continued)

DSP CONTROLLERS

PIN FUNCTION SELECTED

(MCRx.n = 1)

Primary Function

CLKOUT IOPE0 MCRC.0 1 PEDATDIR 0 8

PWM7 IOPE1 MCRC.1 0 PEDATDIR 1 9

PWM8 IOPE2 MCRC.2 0 PEDATDIR 2 10

PWM9 IOPE3 MCRC.3 0 PEDATDIR 3 11

PWM10 IOPE4 MCRC.4 0 PEDATDIR 4 12

PWM11 IOPE5 MCRC.5 0 PEDATDIR 5 13

PWM12 IOPE6 MCRC.6 0 PEDATDIR 6 14

CAP4/QEP3 IOPE7 MCRC.7 0 PEDATDIR 7 15

CAP5/QEP4 IOPF0 MCRC.8 0 PFDATDIR 0 8

CAP6 IOPF1 MCRC.9 0 PFDATDIR 1 9

T3PWM/T3CMP IOPF2 MCRC.10 0 PFDATDIR 2 10

T4PWM/T4CMP IOPF3 MCRC.11 0 PFDATDIR 3 11

TDIRB IOPF4 MCRC.12 0 PFDATDIR 4 12

TCLKINB IOPF5 MCRC.13 0 PFDATDIR 5 13

†

Bold, italicized pin names indicate pin functions at reset.

‡

Valid only if the I/O function is selected on the pin

If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.

If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.

At reset, all LF240xA devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406A), W/R

mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used. The XMIF Hi-Z control bit (bit 4 of the SCSR2 register)

is reserved in these devices and must be written with a zero.

Bits 15 through 9 of the MCRB register must be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation of the device.

(MCRX.N = 0)

I/O

MUX CONTROL REGISTER

(name.bit #)

MUX CONTROL

VALUE AT RESET

(MCRx.n)

I/O PORT DATA AND DIRECTION

PORT E

PORT F

‡

DIR BIT NO.

digital I/O control registers

Table 13 lists the registers available in the digital I/O module. As with other 240xA peripherals, these registers are memory-mapped to the data space.

Table 13. Addresses of Digital I/O Control Registers

ADDRESS REGISTER NAME

7090h MCRA I/O MUX control register A

7092h MCRB I/O mux control register B

7094h MCRC I/O mux control register C

7095h PEDATDIR I/O port E data and direction register

7096h PFDATDIR I/O port F data and direction register

7098h PADATDIR I/O port A data and direction register

709Ah PBDATDIR I/O port B data and direction register

709Ch PCDATDIR I/O port C data and direction register

709Eh PDDATDIR I/O port D data and direction register

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external memory interface (LF2407A)

The TMS320LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data, and I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range.

The CPU of the TMS320LF2407A schedules a program fetch, data read, and data write on the same machine cycle. This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle. However, the external interface multiplexes the internal buses to one address bus and one data bus. The external interface sequences these operations to complete first the data write, then the data read, and finally the program read.

The LF2407A supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data buses, along with the PS program, data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space (7000−7FFF), the externally addressable data-memory space is 32K 16-bit words (8000−FFFF). Note that the global memory space of the C2xx core is not used for 240xA DSP devices. Therefore, the global memory allocation register (GREG) is reserved for all these devices.

Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are accessed in the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices.

, DS, and IS space-select signals, allow addressing of 64K 16-bit words in

The LF2407A external parallel interface provides various control signals to facilitate interfacing to the device. The R/W signal provides a timing reference for all external cycles. For convenience, the device also provides the RD the WE for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the LF2407A.

The 2407A provides RD and W/R signals to help the zero-wait-state external memory interface. At higher CLKOUT speeds, RD be used as an alternative signal with some tradeoffs. See the timing parameters for details.

The TMS320LF2407A supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes take two cycles. This allows the TMS320LF2407A to buffer the transition of the data bus from input to output (or from output to input) by a half cycle. In most systems, the TMS320LF2407A ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes.

wait-state generation (LF2407A only)

Wait-state generation is incorporated in the LF2407A without any external hardware for interfacing the LF2407A with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states operate on CLKOUT cycle boundaries.

To avoid bus conflicts, writes from the LF2407A always take at least two CLKOUT cycles. The LF2407A offers two options for generating wait states:

output signal is provided to indicate whether the current cycle is a read or a write. The STRB output

output signals, which indicate a read cycle and a write cycle, respectively, along with timing information

may not meet the slow memory device’s timing. In such instances, the W/R signal could

D READY Signal. With the READY signal, you can externally generate any number of wait states. The READY

pin has no effect on accesses to internal memory.

and

D On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.

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DSP CONTROLLERS

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generating wait states with the READY signal

When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is not used, it should be pulled high.

The READY pin can be used to generate any number of wait states. However, when the LF2407A operates at full speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended wait states using external READY logic, the on-chip wait-state generator should be programmed to generate at least one wait state.

generating wait states with the LF2407A on-chip software wait-state generator

The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information on the WSGR and associated bit functions, see the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357).

watchdog (WD) timer module

The x240xA devices include a watchdog (WD) timer module. The WD function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:

D WD Timer

− Seven different WD overflow rates

− A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and

generates a system reset if an incorrect value is written to the register

− WD check bits that initiate a system reset if an incorrect value is written to the WD control register (WDCR)

D Automatic activation of the WD timer, once system reset is released

− Three WD control registers located in control register frame beginning at address 7020h.

NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte

Figure 19 shows the WD block diagram. Table 14 shows the different WD overflow (time-out) selections. The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of

the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent to the WDDIS pin of the TMS320F243/241 devices.

is read as zeros. Writing to the upper byte has no effect.

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watchdog (WD) timer module (continued)

WDCLK

System

Reset

WDPS

WDCR.2 − 0

210

WDCR.6

WDDIS

6-Bit

Free-

Running

Counter

CLR

000

111

001

110

010

011

100

101

/64 /32

/16 /8 /4 /2

÷ 512 PLL

WDCNTR.7 − 0

8-Bit Watchdog

Counter

CLR

CLKOUT CLKIN

One-Cycle

Delay

3-bit

Prescaler

Oscillator or

WDFLAG

WDCR.7

PS/257

On-Chip

External

Clock

Reset Flag

Internal

Pullup

RS Pin

WDKEY.7 −0

Watchdog Reset Key

†

Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset.

55 + AA

Detector

System Reset

Bad Key

Good Key

WDCHK2−0

WDCR.5 − 3

101

(Constant

Value)

†

Figure 19. Block Diagram of the WD Module

System Reset Request

Bad WDCR Key

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WDCLK DIVIDER

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watchdog (WD) timer module (continued)

Table 14. WD Overflow (Time-out) Selections

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

WATCHDOG

CLOCK RATE

FREQUENCY (Hz)

WDPS2 WDPS1 WDPS0

0 0 X

0 1 0 2 WDCLK/2

0 1 1 4 WDCLK/4

1 0 0 8 WDCLK/8

1 0 1 16 WDCLK/16

1 1 0 32 WDCLK/32

1 1 1 64 WDCLK/64

†

WDCLK = CLKOUT/512

‡

X = Don’t care

WD PRESCALE SELECT BITS

WDCLK DIVIDER

‡

1 WDCLK/1

development support

Texas Instruments (TI) offers an extensive line of development tools for the x240xA generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of x240xA-based applications:

Software Development Tools:

Assembler/linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler

†

Hardware Development Tools:

Emulator XDS510 (supports x24x multiprocessor system debug) TMS320LF2407 EVM (Evaluation module for 2407 DSP)

See Table 15 and Table 16 for complete listings of development support tools for the x240xA. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

Table 15. Development Support Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER

Software

Code Composer Studio v.2.2 PC TMDSCCS2000-1

Hardware − Emulation Debug Tools

XDS510PP Pod (Parallel Port) with JTAG cable PC TMDS3P701014

PC is a trademark of International Business Machines Corp.. Code Composer Studio, XDS510, and XDS510PP are trademarks of Texas Instruments.

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SPRS145K − JULY 2000 − REVISED AUGUST 2005

development support (continued)

Table 16. TMS320x24x-Specific Development Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER

Hardware − Evaluation/Starter Kits

2401A eZdsp PC TMDSeZD2401

F2407A EVM PC TMDS3P701016A

LF2407A eZdsp PC TMDSEZD2407

The LF2407 Evaluation Module (EVM) provide designers of motor and motion control applications with a complete and cost-effective way to take their designs from concept to production. These tools offer both a hardware and software development environment and include:

D Flash-based LF240xA evaluation board D Code Generation Tools D Assembler/Linker D C Compiler D Source code debugger D C24x Debugger D Code Composer IDE D XDS510PP JTAG-based emulator D Sample applications code D Universal 5-V DC power supply D Documentation and cables

device and development support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device’s electrical specifications

TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality

and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies.

TMS320 is a trademark of Texas Instruments. eZdsp is a trademark of Spectrum Digital, Inc.

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device and development support tool nomenclature (continued)

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PAG, PG, PGE, and PZ) and temperature range (for example, A). Figure 20 provides a legend for reading the complete device name for any TMS320x240xA family member. See the timing section for specific options that are available on 240xA devices.

TEMPERATURE RANGE

A=−40°C to 85°C S=−40°C to 125°C

PREFIX

TMX = experimental device TMP = prototype device TMS = qualified device

TMS 320 LF 2407A PGE

PGE

PACKAGE TYPE

DEVICE FAMILY

320 = TMS320

TECHNOLOGY

LC = ROM (3.3 V) LF = Flash EEPROM (3.3 V)

†

QFP = Quad Flatpack LQFP = Low-Profile Quad Flatpack TQFP = Thin Quad Flatpack

‡

Not yet available Lead (Pb)-free. For estimated conversion dates, go to www.ti.com/leadfree

The package dimensions of the 2407A and 2406A devices correspond to the LQFP package. These devices were stated to be in TQFP packaging in the TMX data sheets. The package dimensions have not changed; only the package designation has changed.

DSP Family

PG = 64-pin QFP PAG = 64-pin TQFP PGE = 144-pin plastic LQFP PZ = 100-pin plastic LQFP VF = 32-pin plastic LQFP

DEVICE

240xA DSP

2407A 2406A 2404A 2403A 2402A 2401A

†‡

Figure 20. TMS320x240xA Device Nomenclature

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

documentation support

Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s guides for all devices and development support tools; and hardware and software applications. Useful reference documentation includes:

D User Guides

− TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357)

− Manual Update Sheet for TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (SPRU357) [literature number SPRZ015]

− TMS320C240 DSP Controllers CPU, System, and Instruction Set Reference Guide

(literature number SPRU160)

D Data Sheets

− TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers (literature number SPRS145)

− TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers (literature number SPRS094)

− TMS320LF2401A DSP Controller (literature number SPRS161)

D Application Reports

− 3.3-V DSP for Digital Motor Control (literature number SPRA550)

To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information.

Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com.

To send comments regarding this TMS320x240xA data sheet (literature number SPRS145), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

IOHHigh level output source current, VOH 2.4 V

IOLLow level output sink current, VOL V

MAX

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

LF240xA AND LC240xA ELECTRICAL SPECIFICATIONS DATA

absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)

Supply voltage range, VDD, PLLV V

range − 0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CCP

Input voltage range, V Output voltage range, V Output voltage range,V Input clamp current, I Output clamp current, I

− 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LF240xA − 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LC240xA − 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VIN < 0 or VIN > VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature ranges, T

Junction temperature range, T Storage temperature range, T

†

Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to V

2. Long−term high−temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see the IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability Data for TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).

stg

recommended operating conditions

VDD/V

PLLV

CCA ¶

CCA

CCP

CLKOUT

‡

See the mechanical data package page for thermal resistance values, Θ of case)

The drive strengths of the EVA PWM pins and the EVB PWM pins are not identical.

CCA

The input buffers used in 240x/240xA are not 5-V compatible.

Primary signals and their groupings: Group 1: PWM1−PWM6, T1PWM, T2PWM, CAP1−CAP6, TCLKINA, IOPF6, IOPC1, TCK, TDI, TMS, XF, A0−A15, RS Group 2: PS/DS/IS, RD, W/R, STRB, R/W, VIS_OE, D0−D15, T3PWM, T4PWM, PWM7−PWM12, CANTX, CANRX, SPICLK,

Group 3: TDIRA, TDIRB, SCIRXD, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB

Supply voltage V

DDO

Supply ground 0 0 0 V

PLL supply voltage 3 3.3 3.6 V

ADC supply voltage 3 3.3 3.6 V

Flash programming supply voltage 4.75 5 5.25 V

Device clock frequency (system clock) 2 40 MHz

High-level input voltage All inputs 2 VDD + 0.3 V

Low-level input voltage All inputs 0.8 V

High-level output source current, VOH = 2.4 V

Low-level output sink current, VOL = V

Free-air temperature

Junction temperature − 40 25 150 °C

Flash endurance for the array (Write/erase cycles)

should not differ from VDD by more than 0.3 V.

SPISOMI, SPISIMO, SPISTE

, EMU0, EMU1, TDO, TMS2

, V

CCA

, and V

DDO

: A version − 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) − 0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . .

CCA

S version − 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2) − 40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2) − 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡§

MIN NOM MAX UNIT

= VDD ± 0.3 V 3 3.3 3.6 V

DDO

Output pins Group 1

Output pins Group 2

Output pins Group 3

Output pins Group 1

MAX

A version − 40 85

S version

Output pins Group 2

Output pins Group 3

− 40°C to 85°C 10K cycles

(junction-to-ambient), Θ

− 40 125

(junction-to-case), and Ψjt (junction-to-top

− 2 mA

− 4 mA

− 8 mA

2 mA

4 mA

8 mA

°C

†

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

following:

†

3.Performs a continuous conversion of all

out of SCI and executes MACD instructions.

NOTE: All I/O pins

floati

ADC module

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage

Low-level output voltage IOL = IOLMAX 0.4 V

Input current (low level)

Input current (high level)

Leakage current, high-impedance state (off-state) VO = VDD or 0 V ±2 µA

Input capacitance 2 pF

Output capacitance 3 pF

With pullup

With pulldown

With pullup

With pulldown

VDD = 3.0 V, IOH = IOHMAX 2.4 V

All outputs at 50 µA

VDD = 3.3 V, VIN = 0 V

VDD = 3.3 V, VIN = V

− 0.2

DDO

−10 −16 −30

10 16 30

current consumption by power-supply pins over recommended operating free-air temperature ranges at 40-MHz CLOCKOUT

PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT

LF2407A 95 120 mA

LF2406A 95 120 mA

LF2403A 95 120 mA

LF2402A 85 110 mA

LC2406A 85 110 mA

LC2404A 85 110 mA

LC2403A 75 95 mA

LC2402A 75 95 mA

LF2407A 10 22 mA

LF2406A 10 22 mA

LF2403A 10 22 mA

LF2402A 10 22 mA

LC2406A 10 22 mA

LC2404A 10 22 mA

LC2403A 10 22 mA

LC2402A 10 22 mA

CCA

†

IDD is the current flowing into the VDD, V

Operational Current

current

A test code running in B0 RAM does the followin

1. Enables clock to all peripherals.

2. Toggles all PWM outputs at 20 kHz.

3. Performs a continuous conversion of all

4.An infinite loop which transmits a character

DDO

ADC channels.

out of SCI and executes MACD instructions.

, and PLLV

CCA

pins.

are

ng.

DDO

±2 ±2

µA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

LPM2

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

LPM2

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

LPM2

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2407A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

Clock to all peripherals is disabled. Flash is powered down. Input clock is disabled.

pins.

‡

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2406A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

Clock to all peripherals is disabled. Flash is powered down. Input clock is disabled.

pins.

‡

70 80 mA

10 22 mA

35 45 mA

0 0 mA

200 400 µA

0 0 mA

70 80 mA

10 22 mA

35 45 mA

0 0 mA

200 400 µA

0 0 mA

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2403A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

Clock to all peripherals is disabled. Flash is powered down. Input clock is disabled.

pins.

‡

70 80 mA

10 22 mA

35 45 mA

0 0 mA

200 400 µA

0 0 mA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

LPM2

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

†

LPM2 Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

†

LPM2

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2402A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

Clock to all peripherals is disabled. Flash is powered down. Input clock is disabled.

pins.

‡

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2406A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

−40°C to 85°C 20 200 µA

−40°C to 125°C 20 400 µA

Clock to all peripherals is disabled. Input clock is disabled.

pins.

‡

60 70 mA

10 22 mA

35 45 mA

0 0 mA

200 400 µA

0 0 mA

50 70 mA

10 22 mA

35 45 mA

0 0 mA

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2404A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

Operational Current

ADC module current

Operational Current

ADC module current

LPM0

LPM1

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

−40°C to 85°C 20 200 µA

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

, and PLLV

DDO

CCA

−40°C to 125°C 20 400 µA

Clock to all peripherals is disabled. Input clock is disabled.

pins.

‡

50 70 mA

10 22 mA

35 45 mA

0 0 mA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

†

LPM2 Clock to all peripherals is enabled.

Clock to all peripherals is disabled.

†

LPM2

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2403A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

Operational Current

ADC module current

Operational Current

ADC module current

LPM0

LPM1

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

−40°C to 85°C 20 200 µA

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

, and PLLV

DDO

CCA

−40°C to 125°C 20 400 µA

Clock to all peripherals is disabled. Input clock is disabled.

pins.

‡

current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2402A)

PARAMETER MODE TEST CONDITIONS MIN TYP MAX UNIT

†

CCA

†

CCA

†

IDD is the current flowing into the VDD, V

‡

If a quartz crystal or ceramic resonator is used as the clock source, the LPM2 mode shuts down the internal oscillator.

Operational Current

ADC module current

Operational Current

ADC module current

Operational Current

ADC module current

, and PLLV

DDO

LPM0

LPM1

CCA

Clock to all peripherals is enabled. No I/O pins are switching.

Clock to all peripherals is disabled. No I/O pins are switching.

−40°C to 85°C 20 200 µA

−40°C to 125°C 20 400 µA

Clock to all peripherals is disabled. Input clock is disabled.

pins.

‡

50 70 mA

10 22 mA

35 45 mA

0 0 mA

40 60 mA

10 22 mA

35 45 mA

0 0 mA

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

current consumption graphs

100

Current (mA)

0 5 10 15 20 25 30 35 40 45

CLKOUT Frequency (MHz)

Figure 21. LF2407A Typical Current Consumption (With Peripheral Clocks Enabled)

100

Current (mA)

0 5 10 15 20 25 30 35 40 45

CLKOUT Frequency (MHz)

Figure 22. LC2406A Typical Current Consumption (With Peripheral Clocks Enabled)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

reducing current consumption

240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 17 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. See the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals.

Table 17. Typical Current Consumption by Various Peripherals (at 40 MHz)

PERIPHERAL MODULE CURRENT REDUCTION (mA)

CAN

EVA 6.1

EVB

ADC 3.7

SCI

SPI 1.3

†

This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

CCA

) as well.

8.4

6.1

†

1.9

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

LOAD

Where: I

LOAD

= 2 mA (all outputs) = 300 µA (all outputs) = 1.5 V = 50-pF typical load-circuit capacitance

50 Ω

Output Under Test

Figure 23. Test Load Circuit

signal transition levels

The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.4 V.

Figure 24 shows output levels.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

2.4 V (VOH) 80%

20%

0.4 V (VOL)

Figure 24. Output Levels

Output transition times are specified as follows:

D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the

total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower.

D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage

range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher.

Figure 25 shows the input levels.

2.0 V (VIH) 90%

10%

0.8 V (VIL)

Figure 25. Input Levels

Input transition times are specified as follows:

D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%

of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower.

D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%

of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

A A[15:0] MS Memory strobe pins IS, DS, or PS

Cl XTAL1/CLKIN R READY

CO CLKOUT RD Read cycle or RD

D D[15:0] RS RESET pin RS

INT XINT1, XINT2 W Write cycle or WE

Lowercase subscripts and their meanings: Letters and symbols and their meanings:

a access time H High

c cycle time (period) L Low

d delay time V Valid

f fall time X Unknown, changing, or don’t care level

h hold time Z High impedance

r rise time

su setup time

t transition time

v valid time

w pulse duration (width)

general notes on timing

All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this data sheet.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Input clock frequency

MHz

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

external reference crystal/clock with PLL circuit enabled

timing parameters with the PLL circuit enabled

PARAMETER MIN MAX UNIT

Resonator 4 13

†

Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.

Input clock frequency

†

Crystal 4 20

CLKIN 4 20

MHz

switching characteristics over recommended operating conditions [H = 0.5 t

] (see Figure 26)

c(CO)

PARAMETER PLL MODE MIN TYP MAX UNIT

c(CO)

f(CO)

r(CO)

w(COL)

w(COH)

†

Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.

Cycle time, CLKOUT

Fall time, CLKOUT 4 ns

Rise time, CLKOUT 4 ns

Pulse duration, CLKOUT low H −3 H H+3 ns

Pulse duration, CLKOUT high H −3 H H+3 ns

Transition time, PLL synchronized after RS pin high

×4 mode

†

25 ns

4096t

timing requirements (see Figure 26)

MIN MAX UNIT

c(Cl)

f(Cl)

r(Cl)

w(CIL)

w(CIH)

XTAL1/CLKIN

Cycle time, XTAL1/CLKIN

Fall time, XTAL1/CLKIN 5 ns

Rise time, XTAL1/CLKIN 5 ns

Pulse duration, XTAL1/CLKIN low as a percentage of t

Pulse duration, XTAL1/CLKIN high as a percentage of t

w(CIH)

c(Cl)

c(CI)

f(Cl)

w(CIL)

40 60 %

r(Cl)

c(Cl)

250 ns

CLKOUT

w(COH)

c(CO)

w(COL)

r(CO)

Figure 26. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

f(CO)

RS timing

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

timing requirements for a reset [H = 0.5t

w(RSL)

w(RSL2)

d(EX)

†

During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles.

VDD/V

DDO

CLKIN

XTAL1

(See Note B)

Pulse duration, stable CLKIN to RS high

Pulse duration, RS low

PLL lock-up time 4096t

Delay time, reset vector executed after PLL lock time

tw(RSL)

OSCST

(See Note C)

] (see Figure 27 and Figure 28)

c(CO)

MIN NOM MAX UNIT

†

c(CI)

36H ns

td(EX)

c(CI)

cycles

BOOT_EN

NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before

/XF

CLKOUT

(See Note D)

I/Os

Address/

Data/

Control

the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New generation emulators such as SPI515 and XDS510 USB emulators have built-in protection mechanism to take care of this requirement.

B. XTAL1 refers to the internal oscillator clock if on-chip oscillator is used. C. t D. All I/Os contain a clamp to V

is the oscillator start-up time, which is dependent on crystal/resonator and board design.

OSCST

or pulldowns will always sink/source a small amount of current once powered.

Hi-Z

. Inputs of approximately 0.7 V above VDD will cause the I/O to sink current. I/Os containing pullups

BOOT_EN

Address/Data/Control Valid

Code-Dependent

Figure 27. Power-on Reset (See Note A)

XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital. XDS510 and XDS510PP, are trademarks of Texas Instruments.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

RS timing (continued)

d(EX)

CLKIN

XTAL1

w(RSL2)

†

BOOT_EN

/XF

CLKOUT

I/Os

Hi-Z

Address/

Data/

Control

†

XTAL1 refers to internal oscillator clock if on-chip oscillator is used.

Figure 28. Warm Reset

BOOT_EN

Code-Dependent

Address/Data/Control Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

RS timing (continued)

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

switching characteristics over recommended operating conditions for a reset [H = 0.5t (see Figure 29)

PARAMETER MIN MAX UNIT

w(RSL1)

d(EX)

†

The parameter t

CLKIN

†

XTAL1

BOOT_EN

/XF

Pulse duration, RS low

Delay time, reset vector executed after PLL lock time

PLL lock time (input cycles)

refers to the time RS is an output.

w(RSL1)

†

w(RSL1)

BOOT_EN

d(EX)

128t

c(CI)

36H ns

4096t

c(CO)

c(CI)

]

CLKOUT

I/Os

Hi-Z

Address/

Data/

Control

†

XTAL1 refers to internal oscillator clock if on-chip oscillator is used.

Figure 29. Watchdog Initiated Reset

Code-Dependent

Address/Data/Control Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Delay time, CLKOUT switching to

HALT

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

low-power mode timing

switching characteristics over recommended operating conditions [H = 0.5t (see Figure 30, Figure 31, and Figure 32)

PARAMETER LOW-POWER MODES MIN TYP MAX UNIT

d(WAKE-A)

d(IDLE-COH)

d(WAKE-OSC)

d(IDLE-OSC)

d(EX)

A0−A15

CLKOUT

WAKE INT

†

WAKE INT can be any valid interrupt or RESET.

Delay time, CLKOUT switching to program execution resume

Delay time, Idle instruction executed to CLKOUT high

Delay time, wakeup interrupt asserted to oscillator running

Delay time, Idle instruction executed to oscillator power off

Delay time, reset vector executed after PLL lock time

†

Figure 30. IDLE1 Entry and Exit Timing − LPM0

IDLE1 LPM0 12 × t

IDLE2

IDLE2 LPM1 4t

HALT {PLL/OSC power down}

d(WAKE−A)

LPM1 15 × t

OSC start-up

LPM2

36H ns

c(CO)

]

c(CO)

time

c(CO)

A0−A15

CLKOUT

WAKE INT

†

WAKE INT can be any valid interrupt or RESET.

†

Figure 31. IDLE2 Entry and Exit Timing − LPM1

A0−A15

d(IDLE−COH)

CLKOUT

RESET

d(IDLE−COH)

d(IDLE−OSC)

d(WAKE−OSC)

Figure 32. HALT Mode − LPM2

d(WAKE−A)

w(RSL)

d(EX)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Delay time, PDPINTA low to PWM

‡

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

LPM2 wakeup timing

switching characteristics over recommended operating conditions (see Figure 33)

PARAMETER MIN MAX UNIT

d(PDP-PWM)HZ

d(INT)

†

Includes i/p qualifier cycles plus synchronization plus propagation delay

Delay time, PDPINTA low to PWM high-impedance state

Delay time, INT low/high to interrupt-vector fetch

if bit 6 of SCSR2 = 0 (6 + 1)t

if bit 6 of SCSR2 = 1

timing requirements (see Figure 33)

w(PDP−WAKE)

‡

This is different from 240x devices.

Pulse duration, PDPINTA input low

PLL lock-up time 4096t

if bit 6 of SCSR2 = 0 6t

if bit 6 of SCSR2 = 1

10t

+ tw(PDP−WAKE) ns

c(CO)

MIN MAX UNIT

c(CO)

12t

c(CO)

(12+ 1)t

c(CO)

+ 12

†

c(CI)

cycles

XTAL1

Oscillator Disabled

OSC

†

CLKIN

CLKOUT

‡

w(PDP−WAKE)

PDPINTx

d(PDP-PWM)HZ

PWM

d(INT)

CPU Status

†

is the oscillator start-up time.

OSC

‡

CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example).

PDPINTx interrupt vector, if PDPINTx interrupt is enabled.

If PDPINTx interrupt is disabled.

CPU IDLE State (LPM2)

Interrupt Vector§ or

Next Instruction

Figure 33. LPM2 Wakeup Using PDPINTx

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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

XF, BIO, and MP/MC timing

switching characteristics over recommended operating conditions (see Figure 34)

PARAMETER MIN MAX UNIT

d(XF)

timing requirements (see Figure 34)

su(BIO)CO

h(BIO)CO

CLKOUT

Delay time, CLKOUT high to XF high/low

Setup time, BIO or MP/MC low before CLKOUT low

Hold time, BIO or MP/MC low after CLKOUT low

d(XF)

MIN MAX UNIT

−3 7 ns

0 ns

19 ns

BIO,

MP/MC

su(BIO)CO

Figure 34. XF and BIO Timing

h(BIO)CO

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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

TIMING EVENT MANAGER INTERFACE

PWM timing

PWM refers to all PWM outputs on EVA and EVB.

switching characteristics over recommended operating conditions for PWM timing [H = 0.5t

†

w(PWM)

d(PWM)CO

†

PWM outputs may be 100%, 0%, or increments of t

] (see Figure 35)

c(CO)

PARAMETER MIN MAX UNIT

Pulse duration, PWMx output high/low

Delay time, CLKOUT low to PWMx output switching

c(CO)

2H+5 ns

with respect to the PWM period.

15 ns

timing requirements‡ [H = 0.5t

w(TMRDIR)

w(TMRCLK)

wh(TMRCLK)

c(TMRCLK)

‡

Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.

CLKOUT

PWMx

Pulse duration, TMRDIR low/high

Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time

Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time

Cycle time, TMRCLK

d(PWM)CO

] (see Figure 36)

c(CO)

w(PWM)

Figure 35. PWM Output Timing

MIN MAX UNIT

4H+5 ns

40 60 %

4  t

c(CO)

CLKOUT

TMRDIR

†

Parameter TMRDIR is equal to the pin TDIRx.

†

w(TMRDIR)

Figure 36. TMRDIR Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

†

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

capture and QEP timing

CAP refers to all QEP and capture input pins.

timing requirements (see Figure 37)

w(CAP)

†

This is different from 240x devices.

CLKOUT

Pulse duration, CAPx input low/high

CAPx

Figure 37. Capture Input and QEP Timing

if bit 6 of SCSR2 = 0

if bit 6 of SCSR2 = 1

w(CAP)

MIN MAX UNIT

c(CO)

12t

c(CO)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

Delay time, PDPINTA low to PWM

†

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

interrupt timing

INT refers to XINT1 and XINT2. PDP refers to PDPINTx.

switching characteristics over recommended operating conditions (see Figure 38)

PARAMETER MIN MAX UNIT

d(PDP-PWM)HZ

d(INT)

†

Includes i/p qualifier cycles plus synchronization plus propagation delay

Delay time, PDPINTA low to PWM high-impedance state

Delay time, INT low/high to interrupt-vector fetch

if bit 6 of SCSR2 = 0 (6 + 1)t

if bit 6 of SCSR2 = 1

timing requirements (see Figure 38)

w(INT)

w(PDP)

†

This is different from 240x devices.

Pulse duration, INT input low/high

Pulse duration, PDPINTx input low

if bit 6 of SCSR2 = 0

if bit 6 of SCSR2 = 1

if bit 6 of SCSR2 = 0

if bit 6 of SCSR2 = 1

10t

+ tW (INT) ns

c(CO)

(12+ 1)t

c(CO)

MIN MAX UNIT

c(CO)

12t

c(CO)

12t

c(CO)

+ 12

†

CLKOUT

w(PDP)

PDPINTx

d(PDP-PWM)HZ

†

PWM

w(INT)

XINT1, XINT2

d(INT)

A0−A15

†

PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken

Interrupt Vector

high depends on the state of the FCOMPOE bit.

Figure 38. External Interrupts Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

general-purpose input/output timing

switching characteristics over recommended operating conditions (see Figure 39)

PARAMETER MIN MAX UNIT

d(GPO)CO

r(GPO)

f(GPO)

Delay time, CLKOUT low to GPIO low/high

Rise time, GPIO switching low to high All GPIOs 8 ns

Fall time, GPIO switching high to low All GPIOs 6 ns

All GPIOs

9ns

timing requirements [H = 0.5t

w(GPI)

CLKOUT

Pulse duration, GPI high/low

CLKOUT

GPIO

] (see Figure 40)

c(CO)

d(GPO)CO

f(GPO)

Figure 39. General-Purpose Output Timing

r(GPO)

MIN MAX UNIT

2H+15 ns

GPIO

w(GPI)

Figure 40. General-Purpose Input Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

UNIT

• 91

SPI MASTER MODE TIMING PARAMETERS

SPI master mode timing information is listed in the following tables.

SPI master mode external timing parameters (clock phase = 0)†‡ (see Figure 41)

SPI WHEN (SPIBRR + 1) IS EVEN

NO.

1 t

c(SPC)M

w(SPCH)M

w(SPCL)M

w(SPCH)M

d(SPCH-SIMO)M

d(SPCL-SIMO)M

v(SPCL-SIMO)M

v(SPCH-SIMO)M

su(SOMI-SPCL)M

su(SOMI-SPCH)M

v(SPCL-SOMI)M

v(SPCH-SOMI)M

†

The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

‡

tc = system clock cycle time = 1/CLKOUT = t

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Cycle time, SPICLK 4t

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

Delay time, SPICLK high to SPISIMO valid (clock polarity = 0)

Delay time, SPICLK low to SPISIMO valid (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK low (clock polarity =0)

Valid time, SPISIMO data valid after SPICLK high (clock polarity =1)

Setup time, SPISOMI before SPICLK low (clock polarity = 0)

Setup time, SPISOMI before SPICLK high (clock polarity = 1)

Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)

Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)

c(CO)

OR SPIBRR = 0 OR 2

MIN MAX MIN MAX

128t

c(CO)

c(SPC)M

0.5t

c(CO)

c(SPC)M

−10 0.5t

− 10 0.5t

− 10 10 − 10 10

0.5t

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

0 0

0.25t

−10 0.5t

c(SPC)M

− 10 0.5t

c(SPC)M

SPI WHEN (SPIBRR + 1)

IS ODD AND SPIBRR > 3

c(CO)

− 0.5t

+0.5t

− 0.5t

− 10 0.5t

c(CO)

− 10 0.5t

c(CO)

−10 0.5t

c(CO)

− 10 0.5t

c(CO)

−10

c(CO)

−10

c(CO)

− 10

c(CO)

− 10

c(CO)

127t

c(SPC)M

c(CO)

− 0.5t

+ 0.5t

c(CO)

UNIT

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

(clock polarity = 0)

SPICLK

(clock polarity = 1)

†

The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI communication stream is complete.

SPICLK

SPISIMO

SPISOMI

SPISTE

Master Out Data Is Valid

Master In Data

Must Be Valid

†

Figure 41. SPI Master Mode External Timing (Clock Phase = 0)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

UNIT

• 93

SPI master mode external timing parameters (clock phase = 1)†‡ (see Figure 42)

SPI WHEN (SPIBRR + 1) IS EVEN

NO.

1 t

c(SPC)M

w(SPCH)M

w(SPCL)M

w(SPCH)M

Cycle time, SPICLK 4t

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0)

Setup time, SPISIMO data valid before SPICLK low

su(SIMO-SPCH)M

su(SIMO-SPCL)M

(clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK high (clock polarity =0)

Valid time, SPISIMO data valid after SPICLK low

v(SPCH-SIMO)M

v(SPCL-SIMO)M

(clock polarity =1)

Setup time, SPISOMI before SPICLK high (clock polarity = 0)

Setup time, SPISOMI before SPICLK low

su(SOMI-SPCH)M

su(SOMI-SPCL)M

(clock polarity = 1)

Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0)

Valid time, SPISOMI data valid after SPICLK low

v(SPCH-SOMI)M

v(SPCL-SOMI)M

(clock polarity = 1)

†

The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

‡

tc = system clock cycle time = 1/CLKOUT = t

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

c(CO)

OR SPIBRR = 0 OR 2

MIN MAX MIN MAX

128t

c(SPC)M

c(CO)

0.5t

c(CO)

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

0 0

0.25t

−10 0.5t

c(SPC)M

−10 0.5t

c(SPC)M

SPI WHEN (SPIBRR + 1)

IS ODD AND SPIBRR > 3

c(CO)

− 0.5t

+0.5t

−10 0.5t

c(CO)

−10 0.5t

c(CO)

− 10 0.5t

c(CO)

−10 0.5t

c(CO)

− 10

−10

127t

c(SPC)M

c(CO)

− 0.5t

+ 0.5t

c(CO)

UNIT

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISIMO

SPISOMI

†

SPISTE

†

The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI

communication stream is complete.

Master Out Data Is Valid

Master In Data Must Be Valid

Data Valid

Figure 42. SPI Master Mode External Timing (Clock Phase = 1)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

SPI slave mode timing parameters

Slave mode timing information is listed in the following tables.

SPI slave mode external timing parameters (clock phase = 0)†‡ (see Figure 43)

NO. MIN MAX UNIT

12 t

c(SPC)S

w(SPCH)S

w(SPCL)S

w(SPCH)S

d(SPCH-SOMI)S

d(SPCL-SOMI)S

v(SPCL-SOMI)S

v(SPCH-SOMI)S

su(SIMO-SPCL)S

su(SIMO-SPCH)S

v(SPCL-SIMO)S

v(SPCH-SIMO)S

†

The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

‡

= system clock cycle time = 1/CLKOUT = t

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Cycle time, SPICLK 4t

Pulse duration, SPICLK high (clock polarity = 0) 0.5t

Pulse duration, SPICLK low (clock polarity = 1) 0.5t

Pulse duration, SPICLK low (clock polarity = 0) 0.5t

Pulse duration, SPICLK high (clock polarity = 1) 0.5t

Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)

0.375t

Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375t

Valid time, SPISOMI data valid after SPICLK low (clock polarity =0)

Valid time, SPISOMI data valid after SPICLK high (clock polarity =1)

Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0

Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0

Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)

c(CO)

c(SPC)S

0.75t

0.5t

‡

−10 0.5t

−10

c(SPC)S

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

SPI slave mode external timing parameters (continued)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISIMO

†

SPISTE

†

The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until the SPI communication stream is complete.

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

Figure 43. SPI Slave Mode External Timing (Clock Phase = 0)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

SPI slave mode timing parameters (continued)

SPRS145K − JULY 2000 − REVISED AUGUST 2005

DSP CONTROLLERS

SPI slave mode external timing parameters (clock phase = 1)

†‡

(see Figure 44)

NO. MIN MAX UNIT

12 t

c(SPC)S

w(SPCH)S

w(SPCL)S

w(SPCH)S

su(SOMI-SPCH)S

su(SOMI-SPCL)S

v(SPCH-SOMI)S

v(SPCL-SOMI)S

su(SIMO-SPCH)S

su(SIMO-SPCL)S

v(SPCH-SIMO)S

v(SPCL-SIMO)S

†

The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.

‡

= system clock cycle time = 1/CLKOUT = t

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Cycle time, SPICLK 8t

Pulse duration, SPICLK high (clock polarity = 0) 0.5t

Pulse duration, SPICLK low (clock polarity = 1) 0.5t

Pulse duration, SPICLK low (clock polarity = 0) 0.5t

Pulse duration, SPICLK high (clock polarity = 1) 0.5t

c(CO)

c(SPC)S

Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125t

Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125t

Valid time, SPISOMI data valid after SPICLK high (clock polarity =0)

Valid time, SPISOMI data valid after SPICLK low (clock polarity =1)

0.75t

Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0

Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0

Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)

c(CO)

0.5t

−10 0.5t

c(SPC)S

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

SPI slave mode timing parameters (continued)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISIMO

†

SPISTE

†

The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until the SPI communication stream is complete.

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

Data Valid

Figure 44. SPI Slave Mode External Timing (Clock Phase = 1)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A

TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A

DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

external memory interface read timing

switching characteristics over recommended operating conditions for an external memory interface read at 40 MHz [H = 0.5t

d(COL-CNTL)

d(COL-CNTH)

d(COL-A)RD

d(COH-RDL)

d(COL-RDH)

d(COL-SL)

d(COL-SH)

d(WRN)

h(A)COL

su(A)RD

h(A)RD

Delay time, CLKOUT low to control valid

Delay time, CLKOUT low to control inactive

Delay time, CLKOUT low to address valid

Delay time, CLKOUT high to RD strobe active

Delay time, CLKOUT low to RD strobe inactive high

Delay time, CLKOUT low to STRB strobe active low

Delay time, CLKOUT low to STRB strobe inactive high

Delay time, W/R going low to R/W rising

Hold time, address valid after CLKOUT low

Setup time, address valid before RD strobe active low

Hold time, address valid after RD strobe inactive high

] (see Figure 45)

c(CO)

PARAMETER MIN MAX UNIT

4 ns

5 ns

8 ns

5 ns

−8 1 ns

5 ns

6 ns

5 ns

2 ns

H − 7 ns

0 ns

timing requirements [H = 0.5t

a(A)

a(RD)

su(D)RD

h(D)RD

h(AIV-D)

Access time, read data from address valid

Access time, read data from RD low

Setup time, read data before RD strobe inactive high

Hold time, read data after RD strobe inactive high

Hold time, read data after address invalid

] (see Figure 45)

c(CO)

MIN MAX UNIT

2H −10 ns

H − 7 ns

8 ns

0 ns

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS

SPRS145K − JULY 2000 − REVISED AUGUST 2005

external memory interface read timing (continued)

CLKOUT

d(COL−CNTL)

PS, DS,

A[0:15]

d(COL−A)RD

d(COH−RDL)

d(COL−A)RD

h(A)COL

d(COL−RDH)

d(COL−CNTH)

h(A)COL

W/R

R/W

D[0:15]

d(WRN)

a(RD)

a(A)

su(A)RD

su(D)RD

h(D)RD

h(AIV−D)

a(A)

d(COH−RDL)

d(COL−RDH)

su(D)RD

h(A)RD

h(D)RD

100

STRB

d(COL−SL)

Figure 45. Memory Interface Read/Read Timings

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

d(COL−SH)

TEXAS INSTRUMENTS TMS320LF2407A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual