TEXAS INSTRUMENTS TMS320LF2407A Technical data
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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
SPRS145K − JULY 2000 − REVISED AUGUST 2005
DSP CONTROLLERS
D High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
− Low-Power 3.3-V Design
D Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible
With F240
D Flash (LF) and ROM (LC) Device Options
− LF240xA: LF2407A, LF2406A,
LF2403A, LF2402A
− LC240xA: LC2406A, LC2404A,
LC2403A, LC2402A
D On-Chip Memory
− Up to 32K Words x 16 Bits of Flash
EEPROM (4 Sectors) or ROM
− Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
− Up to 2.5K Words x 16 Bits of
Data/Program RAM
− 544 Words of Dual-Access RAM
− Up to 2K Words of Single-Access RAM
D Boot ROM (LF240xA Devices)
− SCI/SPI Bootloader
D Up to Two Event-Manager (EV) Modules
(EVA and EVB), Each Includes:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM
Channels
− Emergency PWM Channel Shutdown
With External PDPINTx
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
− Three Capture Units for Time-Stamping
of External Events
− Input Qualifier for Select Pins
− On-Chip Position Encoder Interface
Circuitry
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
− Applicable for Multiple Motor and/or
Converter Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pin
D External Memory Interface (LF2407A)
− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
D Watchdog (WD) Timer Module
D 10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 500-ns MIN Conversion Time
− Selectable Twin 8-State Sequencers
Triggered by Two Event Managers
D Controller Area Network (CAN) 2.0B Module
(LF2407A, 2406A, 2403A)
D Serial Communications Interface (SCI)
D 16-Bit Serial Peripheral Interface (SPI)
(LF2407A, 2406A, LC2404A, 2403A)
D Phase-Locked-Loop (PLL)-Based Clock
Generation
D Up to 40 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
D Up to Five External Interrupts (Power Drive
Protection, Reset, Two Maskable Interrupts)
D Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral
Independently
D Real-Time JTAG-Compliant Scan-Based
Emulation, IEEE Standard 1149.1
†
(JTAG)
D Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control
Support
D Package Options
− 144-Pin LQFP PGE (LF2407A)
− 100-Pin LQFP PZ (2406A, LC2404A)
− 64-Pin TQFP PAG (LF2403A, LC2403A,
LC2402A)
− 64-Pin QFP PG (2402A)
D Extended Temperature Options (A and S)
− A: − 40°C to 85°C
− S: − 40°C to 125°C
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Copyright 2005, Texas Instruments Incorporated
1
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
Table of Contents
Description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240xA Device Summary 5. . . . . . . . . . . . . . . . .
Functional Block Diagram of the 2407A
DSP Controller 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinouts 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory Map of the 2407A/2406A 29. . . . . . .
Device Reset and Interrupts 30. . . . . . . . . . . . . . . . . . . . .
DSP CPU Core 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240xA Instruction Set 34. . . . . . . . . . . . . . . . . . .
Scan-Based Emulation 34. . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram
Internal Memory 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Manager Modules (EVA, EVB) 45. . . . . . . . . . . .
Enhanced Analog-to-Digital Converter
(ADC) Module 49. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Interface (SCI) Module 53. . . .
of the 2407A DSP CPU 35. .
Controller Area Network (CAN) Module 51. . . . . . . . . .
Serial Peripheral Interface (SPI) Module 55. . . . . . . . . .
PLL-Based Clock Module 57. . . . . . . . . . . . . . . . . . . . . .
Digital I/O and Shared Pin Functions 60. . . . . . . . . . . . .
External Memory Interface (LF2407A) 64. . . . . . . . . . . .
Watchdog (WD) Timer Module 65. . . . . . . . . . . . . . . . . .
Development Support 67. . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Support 70. . . . . . . . . . . . . . . . . . . . . . . . .
LF240xA and LC240xA Electrical
Specifications Data 71. . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 71. . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 71. . . . . . . . . . . . .
Migrating From LF240xA (Flash) Devices to
LC240xA (ROM) Devices 110. . . . . . . . . . . . . . . . . . .
Migrating From 240x Devices to 240xA Devices 111. . .
Migrating From LF240x Devices to
LC240xA Devices 112. . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Register Description 113. . . . . . . . . . . . . . . . . .
Mechanical Data 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
SPRS145K − JULY 2000 − REVISED AUGUST 2005
REVISION HISTORY
PAGE HIGHLIGHTS
1 Deleted C240 from the second bullet on the features page
16 Modified description of the signal TRST in Table 2
27 Modified the Program section of the memory map in Figure 7
58 Changed the text under external reference crystal clock option
71 Modified Note 2 in the absolute maximum ratings table
71 Added the RS signal to Group 1 in the notes on the recommended operating conditions table
77 Changed the maximum logic−low level of 0.8 to 0.4 V in the signal transition levels section
110 Added LC2403A device to Table 18
DSP CONTROLLERS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
3
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
description
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of
digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The
240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost,
low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital
motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing
performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary
section for device-specific features.
The 240xA generation offers an array of memory sizes and different peripherals tailored to meet the specific
price/performance points required by various applications. Flash devices of up to 32K words offer a
cost-effective reprogrammable solution for volume production. The 240xA devices offer a password-based
“code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in
on-chip Flash/ROM. Note that Flash-based devices contain a 256-word boot ROM to facilitate in-circuit
programming. The 240xA family also includes ROM devices that are fully pin-to-pin compatible with their Flash
counterparts.
All 240xA devices offer at least one event manager module which has been optimized for digital motor control
and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM
generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital
conversion. Devices with dual event managers enable multiple motor and/or converter control with a single
240xA DSP controller. Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes
inadvertent pin-triggering by glitches.
The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 375 ns and
offers up to 16 channels of analog input. The autosequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. For systems requiring additional communication interfaces, the 2407A, 2406A,
2404A, and 2403A offer a 16-bit synchronous serial peripheral interface (SPI). The 2407A, 2406A, and 2403A
offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize
device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger
supports this family. Numerous third-party developers not only offer device-level development tools, but also
system-level design and development support.
TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
TMS320x240xA device summary
Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation
of devices.
Table 1. Hardware Features of 240xA Devices
FEATURE LF2407A LF2406A LF2403A LF2402A LC2406A LC2404A LC2403A LC2402A
C2xx DSP Core Yes Yes Yes Yes Yes Yes Yes Yes
Instruction Cycle 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns
MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS
Dual-Access
RAM (16-bit word)
3.3-V On-chip Flash (16-bit word)
(4 sectors: 4K, 12K, 12K, 4K)
On-chip ROM (16-bit word) — — — — 32K 16K 16K 6K
Code Security for On-Chip Flash/ROM Ye s Yes Yes Yes Yes Yes Yes Yes
Boot ROM Yes Yes Yes Yes — — — —
External Memory Interface Yes — — — — — — —
Event Managers A and B (EVA and EVB)
S General-Purpose (GP) Timers 4 4 2 2 4 4 2 2
S Compare (CMP)/PWM 12/16 12/16 6/8 6/8 12/16 12/16 6/8 6/8
S Capture (CAP)/QEP 6/4 6/4 3/2 3/2 6/4 6/4 3/2 3/2
S Input qualifier circuitry on
PDPINTx
XINT1/2, and ADCSOC pins
S Status of PDPINTx pin reflected
in COMCONx register
Watchdog Timer Yes Yes Yes Yes Yes Yes Yes Yes
10-Bit ADC Yes Yes Yes Yes Yes Yes Yes Yes
S Channels 16 16 8 8 16 16 8 8
S Conversion Time (minimum) 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns
SPI Yes Yes Yes — Ye s Ye s Ye s —
SCI Yes Ye s Ye s Yes Ye s Ye s Yes Yes
CAN Yes Yes Yes — Ye s — Yes —
Digital I/O Pins
(Shared)
External Interrupts 5 5 3 3 5 5 3 3
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Packaging
Product Status:
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
RAM (DARAM)
Single-Access
RAM (SARAM)
, CAPx, QEPx,
544 544 544 544 544 544 544 544
2K 2K 512 512 2K 1K 512 —
32K 32K 16K 8K — — — —
EVA,
EVB
Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes
41 41 21 21 41 41 21 21
144-pin
PGE
PD PD PD PD PD PD PD PD
EVA,
EVB
100-pinPZ64-pin
EVA EVA
PAG
EVA,
EVB
64-pinPG100-pinPZ100-pinPZ64-pin
EVA,
EVB
EVA EVA
PAG
PG, PAG
64-pin
Denotes features that are different/new compared to 240x devices.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
5
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
functional block diagram of the 2407A DSP controller
PLLF
PLLV
XINT1/IOPA2
RS
CLKOUT/IOPE0
TMS2
BIO/IOPC1
MP/MC
BOOT_EN/XF
VDD (3.3 V)
TP1
TP2
V
(5V)
CCP
A0−A15
D0−D15
PS, DS, IS
R/W
RD
READY
STRB
WE
ENA_144
VIS_OE
W/R / IOPC0
PDPINTA
CAP1/QEP1/IOPA3
CAP2/QEP2/IOPA4
CAP3/IOPA5
PWM1/IOPA6
PWM2/IOPA7
PWM3/IOPB0
PWM4/IOPB1
PWM5/IOPB2
PWM6/IOPB3
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
TDIRA/IOPB6
TCLKINA/IOPB7
DARAM (B0)
256 Words
C2xx
DSP
Core
V
SS
DARAM (B1)
256 Words
DARAM (B2)
32 Words
PLL Clock
10-Bit ADC
(With Twin
Autosequencer)
SCI
SARAM (2K Words)
SPI
Flash/ROM
(32K Words:
4K/12K/12K/4K)
External Memory
Interface
CAN
WD
Digital I/O
(Shared With
Other Pins)
JTAG Port
Event Manager A
D 3 × Capture Input
D 6 × Compare/PWM
Output
D 2 × GP
Timers/PWM
Event Manager B
D 3 × Capture Input
D 6 × Compare/PWM
Output
D 2 × GP
Timers/PWM
CCA
PLLF2
XTAL1/CLKIN
XTAL2
ADCIN00−ADCIN07
ADCIN08−ADCIN15
V
CCA
V
SSA
V
REFHI
V
REFLO
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
SCIRXD/IOPA1
SPISIMO/IOPC2
SPISOMI/IOPC3
SPICLK/IOPC4
SPISTE/IOPC5
CANTX/IOPC6
CANRX/IOPC7
Port A(0−7) IOPA[0:7]
Port B(0−7) IOPB[0:7]
Port C(0−7) IOPC[0:7]
Port D(0) IOPD[0]
Port E(0−7) IOPE[0:7]
Port F(0−6) IOPF[0:6]
TRST
TDO
TDI
TMS
TCK
EMU0
EMU1
PDPINTB
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/IOPF1
PWM7/IOPE1
PWM8/IOPE2
PWM9/IOPE3
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/IOPF5
Indicates optional modules.
The memory size and peripheral selection of these modules change for different 240xA devices.
See Table 1 for device-specific details.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pinouts
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
TRST
TDIRB/IOPF4
V
SSO
V
DDO
T4PWM/T4CMP/IOPF3
T3PWM/T3CMP/IOPF2
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
XINT2/ADCSOC/IOPD0
PDPINTA
PLLF2
PLLF
PLLV
PLLV
CCA
CCA
TDIRA/IOPB6
D10
D11
W/R/IOPC0
D12
D13
XINT1/IOPA2
D14
SCITXD/IOPA0
SCIRXD/IOPA1
D15
V
SPISIMO/IOPC2
SPISOMI/IOPC3
V
A15
/IOPC5
SPISTE
A14
SPICLK/IOPC4
TMS2
PGE PACKAGE
†
(TOP VIEW)
‡
IOPF5
SS
SSO
DDO
V
V
PDPINTB
D5
138
A12
D4
137
136
A11
IOPB2
PWM5/
TCK
135
IOPE5
PWM11/
D3
134RS133
A10
IOPB1
PWM4/
TDI
TDO
TMS
D6
144
143
142
141
140
139
1
2
3
4
5
D7
6
7
8
9
D8
10
11
12
13
D9
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SS
29
DD
30
31
32
33
34
35
36
373839404142434445464748495051525354555657585960616263646566676869
A13
SSO
DDO
V
V
IOPE6
IOPB7
IOPB3
PWM6/
PWM12/
TCLKINA/
DD
IOPF6
D1
D2
V
132
131
130
129
TMS320LF2407A PGE
A9
SS
DD
V
V
IOPB0
PWM3/
V
128
A8
D0
TCLKINB/
127
126
IOPA7
IOPE4
PWM2/
PWM10/
SSO
V
125
IOPA6
PWM1/
XTAL1/CLKIN
XTAL2
124
123
A7
CCP
V
BOOT_EN/XF
ENA_144
122
121
TP1
IOPE3
PWM9/
IOPC1BIO/
READY
119
120
A6
IOPE2
PWM8/
SSA
MP/MC
V
118
117
A5
TP2
CCA
V
116
IOPE1
PWM7/
REFHI
V
115
SSO
V
REFLO
V
114
DDO
V
ADCIN00
ADCIN08
113
112
A4
IOPF1
CAP6/
ADCIN01
ADCIN09
111
110
707172
A3
IOPC7
CANRX/
ADCIN10
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
IOPC6
CANTX/
ADCIN11
ADCIN02
ADCIN12
ADCIN03
ADCIN13
ADCIN04
ADCIN05
ADCIN14
ADCIN06
ADCIN07
ADCIN15
VIS_OE
STRB
V
DDO
V
SSO
RD
R/W
EMU1/OFF
EMU0
WE
CAP4/QEP3/IOPE7
DS
V
DD
V
SS
PS
CAP1/QEP1/IOPA3
IS
CAP5/QEP4/IOPF0
A0
CAP2/QEP2/IOPA4
A1
V
DDO
V
SSO
CAP3/IOPA5
A2
CLKOUT/IOPE0
†
Bold, italicized pin names indicate pin function after reset.
‡
BOOT_EN is available only on Flash devices.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
7
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pinouts (continued)
DDO
V
SSO
V
OFF
EMU1/
†
IOPE7
IOPA3
IOPF0
DD
SS
EMU0
CAP4/QEP3/VCAP1/QEP1/
CAP5/QEP4/
V
IOPA4
/IOPE0
IOPA5
DDO
SSO
CAP2/QEP2/VCAP3/
CLKOUT
V
51525354555657585960616263646566676869707172737475
25242322212019181716151413121110987654321
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26100
CANTX/IOPC6
CANRX/IOPC7
CAP6/IOPF1
V
DDO
V
SSO
PWM7/IOPE1
TP2
PWM8/IOPE2
TP1
PWM9/IOPE3
¶
V
CCP
PWM1/IOPA6
PWM10/IOPE4
PWM2/IOPA7
PWM3/IOPB0
V
DD
V
SS
PWM4/IOPB1
PWM11/IOPE5
PWM5/IOPB2
V
DDO
V
SSO
PWM6/IOPB3
PWM12/IOPE6
TCLKINA/IOPB7
ADCIN10
ADCIN01
ADCIN09
ADCIN00
ADCIN08
V
REFLO
V
REFHI
V
CCA
V
SSA
BIO/IOPC1
BOOT_EN
/XF
XTAL1/CLKIN
XTAL2
TCLKINB/IOPF5
V
V
IOPF6
RS
TCK
PDPINTB
TDI
V
SSO
V
DDO
TDO
TMS
PZ PACKAGE
( TOP VIEW)
ADCIN11
ADCIN02
ADCIN12
ADCIN03
ADCIN13
ADCIN04
ADCIN05
ADCIN14
ADCIN06
ADCIN07
ADCIN15
76
77
78
79
80
81
82
83
84
85
§
86
87
88
89
90
SS
DD
91
92
93
94
95
96
97
98
99
TMS320LC2404A PZ
TMS320LC2406A PZ
TMS320LF2406A PZ
‡
‡
SSOVSSO
DDO
TRST
V
IOPF4
IOPF3
V
TDIRB/
TDIRB/ IOPF4
T4PWM/T4CMP/
†
Bold, italicized pin names indicate pin function after reset.
‡
CANTX and CANRX are not available on LC2404A devices.
§
BOOT_EN is available only on Flash devices.
¶
On the ROM devices (LC240xA), V
is a No Connect (NC).
CCP
PLLF
IOPF2
PLLF2
PDPINTA
T3PWM/T3CMP/
CCA
IOPB6
IOPB4
PLLV
TDIRA/
T1PWM/T1CMP/
IOPA2
IOPA0
IOPC0
IOPD0
IOPB5
XINT1/
SCITXD/
T2PWM/T2CMP/
XINT2/ADCSOC/
SS
DD
V
V
IOPA1
SCIRXD/
IOPC2
IOPC3
IOPC5
SPISTE/
SPISIMO/
SPISOMI/
TMS2
IOPC4
SPICLK/
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pinouts (continued)
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
T1PWM/T1CMP/IOPB4
T2PWM/T2CMP/IOPB5
†‡
CCA
PLLV
PLLF
PDPINTA
PLLF2
DDO
V
SSO
V
TRST
IOPC4
TMS2
SPICLK/
PAG PACKAGE
IOPC3
IOPC2
IOPA1
SPISOMI/
SPISIMO/
SCIRXD/
(TOP VIEW)
IOPA0
XINT2/ADCSOC/IOPD0
SCITXD/
TCLKINA/IOPB7
PWM6/IOPB3
V
SSO
V
DDO
PWM5/IOPB2
PWM4/IOPB1
V
SS
V
DD
PWM3/IOPB0
PWM2/IOPA7
PWM1/IOPA6
V
CCP
TP1
TP2
CANRX/IOPC7
16
ADCIN03
ADCIN05
ADCIN04
33
32
3150
3051
2952
2853
27
2655
2556
2457
2358
2259
2160
2061
1962
1863
ADCIN02
TMS
TDO
TDI
TCK
RS
V
DD
V
SS
XTAL2
XTAL1/CLKIN
BOOT_EN/XF
V
SSA
V
CCA
V
REFHI
V
REFLO
ADCIN00
ADCIN01CANTX/IOPC6
§
48
47 46 45 44 4342 41 40 39 38 37 36 35 34
49
54
TMS320LF2403A PAG
TMS320LC2403A PAG
TMS320LC2402A PAG
¶
64 17
1
234567 89101112131415
SS
DD
V
/IOPE0
V
CAP3/IOPA5
EMU0
EMU1/ OFF
SSO
V
DDO
V
ADCIN07
ADCIN06
CLKOUT
CAP2/QEP2/IOPA4
CAP1/QEP1/IOPA3
†
Bold, italicized pin names indicate pin function after reset.
‡
For LC2402A, the following pins are different from what is shown:
Pin 45: IOPC2
Pin 46: IOPC3
Pin 47: IOPC4
Pin 63: IOPC7
Pin 64: IOPC6
§
BOOT_EN is available only on flash devices.
¶
On the ROM devices (LC240xA), V
is a No Connect (NC).
CCP
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
9
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pinouts (continued)
IOPD0
IOPB5
†
IOPB4
PG PACKAGE
(TOP VIEW)
V
DDO
PWM5/IOPB2
PWM4/IOPB1
V
SS
V
DD
PWM3/IOPB0
PWM2/IOPA7
PWM1/IOPA6
V
CCP
TP1
TP2
IOPC7
IOPC6
SSO
V
IOPB7
IOPB3
TCLKINA/
PWM6/
TMS2
IOPC4
IOPC2
IOPC3
IOPA1
IOPA0
XINT2/ADCSOC/
SCITXD/
SCIRXD/
CCA
T1PWM/T1CMP/
T2PWM/T2CMP/
PLLV
PLLF2
PLLF
SSO
DDO
PDPINTA
TRST
V
V
3351 343550 49 48 47 46 45 44 43 42 41 40 39 38 37 36
52
53
54
55
56
57
58
59
§
60
TMS320LC2402A PG
TMS320LF2402A PG
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
TMS
TDO
TDI
TCK
RS
V
DD
V
SS
XTAL2
XTAL1/CLKIN
BOOT_EN/XF
V
SSA
V
CCA
V
REFHI
‡
191 2 3 4 5 6 7 8 9101112131415161718
SS
VDDV
OFF
SSO
DDO
V
V
IOPA5
/IOPE0
CAP3/
IOPA4
IOPA3
EMU0
EMU1/
ADCIN05
ADCIN06
ADCIN07
ADCIN02
ADCIN03
ADCIN04
REFLO
V
ADCIN00
ADCIN01
CLKOUT
CAP1/QEP1/
CAP2/QEP2/
†
Bold, italicized pin names indicate pin function after reset.
‡
BOOT_EN is available only on Flash devices.
§
On the ROM devices (LC240xA), V
10
is a No Connect (NC).
CCP
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions
The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A
device. Table 2 lists the signals available in the 240xA generation of devices.
Table 2. LF240xA and LC240xA Pin List and Package Options
2403A,
PIN NAME
CAP1/QEP1/IOPA3 83 57 57 4
CAP2/QEP2/IOPA4 79 55 55 3
CAP3/IOPA5 75 52 52 2 Capture input #3 (EVA) or GPIO (↑)
PWM1/IOPA6 56 39 39 59 Compare/PWM output pin #1 (EVA) or GPIO (↑)
PWM2/IOPA7 54 37 37 58 Compare/PWM output pin #2 (EVA) or GPIO (↑)
PWM3/IOPB0 52 36 36 57 Compare/PWM output pin #3 (EVA) or GPIO (↑)
PWM4/IOPB1 47 33 33 54 Compare/PWM output pin #4 (EVA) or GPIO (↑)
PWM5/IOPB2 44 31 31 53 Compare/PWM output pin #5 (EVA) or GPIO (↑)
PWM6/IOPB3 40 28 28 50 Compare/PWM output pin #6 (EVA) or GPIO (↑)
T1PWM/T1CMP/IOPB4 16 12 12 40 Timer 1 compare output (EVA) or GPIO (↑)
T2PWM/T2CMP/IOPB5 18 13 13 41 Timer 2 compare output (EVA) or GPIO (↑)
TDIRA/IOPB6 14 11 11
TCLKINA/IOPB7 37 26 26 49
CAP4/QEP3/IOPE7 88 60 60
CAP5/QEP4/IOPF0 81 56 56
CAP6/IOPF1 69 48 48 Capture input #6 (EVB) or GPIO (↑)
PWM7/IOPE1 65 45 45 Compare/PWM output pin #7 (EVB) or GPIO (↑)
PWM8/IOPE2 62 43 43 Compare/PWM output pin #8 (EVB) or GPIO (↑)
PWM9/IOPE3 59 41 41 Compare/PWM output pin #9 (EVB) or GPIO (↑)
PWM10/IOPE4 55 38 38 Compare/PWM output pin #10 (EVB) or GPIO (↑)
PWM11/IOPE5 46 32 32 Compare/PWM output pin #11 (EVB) or GPIO (↑)
PWM12/IOPE6 38 27 27 Compare/PWM output pin #12 (EVB) or GPIO (↑)
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
LF2407A
(144-PGE)
CCA
, VSS, or V
DDO
2406A
(100-PZ)
be isolated from the digital supply voltage (and V
SSO
LC2404A
(100-PZ)
EVENT MANAGER A (EVA)
EVENT MANAGER B (EVB)
) should be left unconnected. All power supply pins must be connected appropriately for proper
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
Capture input #1/quadrature encoder pulse input #1 (EVA) or
GPIO (↑)
Capture input #2/quadrature encoder pulse input #2 (EVA) or
GPIO (↑)
Counting direction for general-purpose (GP) timer (EVA) or
GPIO. If TDIRA = 1, upward counting is selected. If
TDIRA = 0, downward counting is selected. (↑)
External clock input for GP timer (EVA) or GPIO. Note that
the timer can also use the internal device clock. (↑)
Capture input #4/quadrature encoder pulse input #3 (EVB) or
GPIO (↑)
Capture input #5/quadrature encoder pulse input #4 (EVB) or
GPIO (↑)
from digital ground) to maintain the specified accuracy
SSA
†‡
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
11
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
SSA
DESCRIPTION
Counting direction for general-purpose (GP) timer
(EVB) or GPIO. If TDIRB = 1, upward counting is
selected. If TDIRB = 0, downward counting is
selected. (↑)
External clock input for GP timer (EVB) or GPIO.
Note that the timer can also use the internal
device clock. (↑)
§
from digital ground) to maintain the specified accuracy
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
EVENT MANAGER B (EVB) (CONTINUED)
T3PWM/T3CMP/IOPF2 8 7 7 Timer 3 compare output (EVB) or GPIO (↑)
T4PWM/T4CMP/IOPF3 6 5 5 Timer 4 compare output (EVB) or GPIO (↑)
TDIRB/IOPF4 2 2 2
TCLKINB/IOPF5 126 89 89
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADCIN00 112 79 79 18 Analog input #0 to the ADC
ADCIN01 110 77 77 17 Analog input #1 to the ADC
ADCIN02 107 74 74 16 Analog input #2 to the ADC
ADCIN03 105 72 72 15 Analog input #3 to the ADC
ADCIN04 103 70 70 14 Analog input #4 to the ADC
ADCIN05 102 69 69 13 Analog input #5 to the ADC
ADCIN06 100 67 67 12 Analog input #6 to the ADC
ADCIN07 99 66 66 11 Analog input #7 to the ADC
ADCIN08 113 80 80 Analog input #8 to the ADC
ADCIN09 111 78 78 Analog input #9 to the ADC
ADCIN10 109 76 76 Analog input #10 to the ADC
ADCIN11 108 75 75 Analog input #11 to the ADC
ADCIN12 106 73 73 Analog input #12 to the ADC
ADCIN13 104 71 71 Analog input #13 to the ADC
ADCIN14 101 68 68 Analog input #14 to the ADC
ADCIN15 98 65 65 Analog input #15 to the ADC
V
REFHI
V
REFLO
V
CCA
V
SSA
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
CCA
DDO
, VSS, or V
115 82 82 20 ADC analog high-voltage reference input
114 81 81 19 ADC analog low-voltage reference input
116 83 83 21 Analog supply voltage for ADC (3.3 V)
117 84 84 22 Analog ground reference for ADC
be isolated from the digital supply voltage (and V
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
CONTROLLER AREA NETWORK (CAN), SERIAL COMMUNICATIONS INTERFACE (SCI), SERIAL PERIPHERAL INTERFACE (SPI)
CANRX/IOPC7
CANTX/IOPC6
SCITXD/IOPA0 25 17 17 43 SCI asynchronous serial port transmit data or GPIO (↑)
SCIRXD/IOPA1 26 18 18 44
SPICLK/IOPC4
SPISIMO/IOPC2
SPISOMI/IOPC3
SPISTE/IOPC5
CANRX 70 49 − 63 CAN receive data or GPIO (LF2403A) (↑)
IOPC7 70 49 49 63 GPIO only (2402A) (↑)
CANTX 72 50 − 64 CAN transmit data or GPIO (LF2403A) (↑)
IOPC6 72 50 50 64 GPIO only (2402A) (↑)
SPICLK 35 24 24 47 SPI clock or GPIO (LF2403A) (↑)
IOPC4 35 24 24 47 GPIO only (2402A) (↑)
SPISIMO 30 21 21 45 SPI slave in, master out or GPIO (LF2403A) (↑)
IOPC2 30 21 21 45 GPIO only (2402A) (↑)
SPISOMI 32 22 22 46 SPI slave out, master in or GPIO (LF2403A) (↑)
IOPC3 32 22 22 46 GPIO only (2402A) (↑)
SPISTE 33 23 23 −
IOPC5 33 23 23 −
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
EXTERNAL INTERRUPTS, CLOCK
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
SCI asynchronous serial port receive data or or
GPIO (↑)
SPI slave transmit-enable (optional) or GPIO (↑)
Device Reset (in) and Watchdog Reset (out).
Device reset. RS causes the device to terminate execution
and to set PC = 0. When RS
execution begins at location 0x0000 of program memory.
RS 133 93 93 28
PDPINTA 7 6 6 36
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
be isolated from the digital supply voltage (and V
CCA
, VSS, or V
DDO
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
This pin is driven low by the DSP when a watchdog reset
occurs. During watchdog reset, the RS
low for the watchdog reset duration of 128 CLKIN cycles.
The output buffer of this pin is an open-drain with an
internal pullup (20 µA, typical). It is recommended that this
pin be driven by an open-drain device. (↑)
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVA) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTA
from digital ground) to maintain the specified accuracy
SSA
is a falling-edge-sensitive interrupt. (↑)
is brought to a high level,
pin will be driven
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
13
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
g
BOOT_EN /
during reset and then driven as an output signal for XF. After
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
XINT1/IOPA2 23 16 16
XINT2/ADCSOC/IOPD0 21 15 15 42
CLKOUT/IOPE0 73 51 51 1
PDPINTB 137 95 95
XTAL1/CLKIN 123 87 87 24
XTAL2 124 88 88 25
PLLV
CCA
IOPF6 131 92 92 General-purpose I/O (↑)
BOOT_EN 121 86 − 23
BOOT_EN /
XF
XF 121 86 86 23
PLLF 11 9 9 38 PLL loop filter input 1
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
LF2407A
(144-PGE)
12 10 10 39 PLL supply (3.3 V)
be isolated from the digital supply voltage (and V
CCA
, VSS, or V
DDO
2406A
(100-PZ)
EXTERNAL INTERRUPTS, CLOCK (CONTINUED)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
LC2404A
(100-PZ)
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
External user interrupt 1 or GPIO. Both XINT1 and XINT2
are edge-sensitive. The edge polarity is
programmable. (↑)
External user interrupt 2 and ADC start of conversion or
GPIO. External “start-of-conversion” input for ADC/GPIO.
Both XINT1 and XINT2 are edge-sensitive. The edge
polarity is programmable. (↑)
Clock output or GPIO. This pin outputs either the CPU clock
(CLKOUT) or the watchdog clock (WDCLK). The selection
is made by the CLKSRC bit (bit 14) of the system control
and status register (SCSR). This pin can be used as a GPIO
if not used as a clock output pin. (↑)
Power drive protection interrupt input. This interrupt, when
activated, puts the PWM output pins (EVB) in the
high-impedance state should motor drive/power converter
abnormalities, such as overvoltage or overcurrent, etc.,
arise. PDPINTB
PLL oscillator input pin. Crystal input to PLL/clock source
input to PLL. XTAL1/CLKIN is tied to one side of a reference
crystal.
Crystal output. PLL oscillator output pin. XTAL2 is tied to
one side of a reference crystal. This pin goes in the
high-impedance state when EMU1/OFF
Boot ROM enable, GPO, XF. This pin will be sampled as
input (BOOT_EN
reset and then driven as an output signal for XF. After
durin
reset, XF is driven high. ROM devices do not have boot
ROM, hence, no BOOT_EN modes. The BOOT_EN
must be driven with a passive circuit only. (↑)
from digital ground) to maintain the specified accuracy
SSA
is a falling-edge-sensitive interrupt. (↑)
) to update SCSR2.3 (BOOT_EN bit)
is active low.
pin
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
PLLF2 10 8 8 37 PLL loop filter input 2
V
(5V) 58 40 40 60
CCP
TP1 60 42 42 61 Test pin 1. Do not connect.
TP2 63 44 44 62 Test pin 2. Do not connect.
BIO/IOPC1 119 85 85
EMU0 90 61 61 7
EMU1/OFF 91 62 62 8
TCK 135 94 94 29 JTAG test clock with internal pullup (↑)
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
LF2407A
(144-PGE)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED)
CCA
, VSS, or V
DDO
2406A
(100-PZ)
be isolated from the digital supply voltage (and V
SSO
LC2404A
(100-PZ)
) should be left unconnected. All power supply pins must be connected appropriately for proper
LC2402A
(64-PAG)
and
2402A
(64-PG)
Flash programming voltage pin. This pin must be connected to
a 5-V supply for Flash programming. The Flash cannot be
programmed if this pin is connected to GND. When not
programming the Flash (i.e., during normal device operation),
this pin can either be left connected to the 5-V supply or it can
be tied to GND. This pin must not be left floating at any time. Do
not use any current-limiting resistor in series with the 5-V supply
on this pin. This pin is a “no connect” (NC) on ROM parts (i.e.,
this pin is not connected to any circuitry internal to the device).
Connecting this pin to 5 V or leaving it open makes no difference
on ROM parts.
Branch control input. BIO is polled by the BCND pma,BIO
instruction. If BIO
it should be pulled high. This pin is configured as a branch
control input by all device resets. It can be used as a GPIO, if
not used as a branch control input. (↑)
EMULATION AND TEST
Emulator I/O #0 with internal pullup. When TRST is driven high,
this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan. (↑)
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST
is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as an input/output through the
JTAG scan. When TRST is driven low, this pin is configured as
OFF
high-impedance state. Note that OFF
testing and emulation purposes (not for multiprocessing
applications). Therefore, for the OFF
apply:
TRST
EMU0 = 1
EMU1/OFF
DESCRIPTION
is low, a branch is executed. If BIO is not used,
. EMU1/OFF, when active low, puts all output drivers in the
= 0
= 0 (↑)
from digital ground) to maintain the specified accuracy
SSA
is used exclusively for
condition, the following
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
15
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
TDI 139 96 96 30
TDO 142 99 99 31
TMS 144 100 100 32
TMS2 36 25 25 48
LF2407A
(144-PGE)
2406A
(100-PZ)
EMULATION AND TEST (CONTINUED)
LC2404A
(100-PZ)
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
JTAG test data input (TDI) with internal pullup. TDI
is clocked into the selected register (instruction or
data) on a rising edge of TCK. (↑)
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge of
TCK. (↓)
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK. (↑)
JTAG test-mode select 2 (TMS2) with internal
pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK. Used for
test and emulation only. This pin can be left
unconnected in user applications. If the PLL bypass
mode is desired, TMS2, TMS, and TRST
held low during reset. (↑)
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. (↓)
should be
NOTE: Do not use pullup resistors on TRST
an internal pulldown device. TRST
TRST 1 1 1 33
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
be isolated from the digital supply voltage (and V
CCA
DDO
, VSS, or V
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
test pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST
instances, an external pulldown resistor is highly
recommended. The value of this resistor should be
based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally
offers adequate protection. Since this is
application−specific, it is recommended that each
target board be validated for proper operation of the
debugger and the application. (I ↓)
from digital ground) to maintain the specified accuracy
SSA
is an active high
; it has
may be left floating. In other
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
y
interface. It is normally low, unless a memory write
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
SSA
Data space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
I/O space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
Program space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
Read/write qualifier signal. R/W indicates transfer
direction during communication to an external
device. It is normally in read mode (high), unless
low level is asserted for performing a write
operation. R/W
¶
state.
Write/Read qualifier or GPIO. This is an inverted
R/W
signal useful for zero-wait-state memory
interface. It is normall
operation is performed. See Table 12, Port C
section, for reset note regarding LF2406A and
LF2402A. (↑)
Read-enable strobe. Read-select indicates an
active, external read cycle. RD
external program, data, and I/O reads. RD
placed in the high-impedance state.
Write-enable strobe. The falling edge of WE
indicates that the device is driving the external
data bus (D15− D0). WE
program, data, and I/O writes. WE
high-impedance state.
External memory access strobe. STRB is always
high unless asserted low to indicate an external
bus cycle. STRB is active for all off-chip
accesses. STRB
¶
state.
from digital ground) to maintain the specified accuracy
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS
DS 87
IS 82
PS 84
R/W 92
W/R 19
W/R / IOPC0
IOPC0 19 14 14
RD 93
WE 89
STRB 96
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
be isolated from the digital supply voltage (and V
CCA
, VSS, or V
DDO
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
DSP CONTROLLERS
DESCRIPTION
¶
¶
¶
is placed in the high-impedance
low, unless a memory write
is active on all
¶
is active on all external
¶
is placed in the high-impedance
is placed in the
is
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
17
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
READY 120
MP/MC 118
ENA_144 122
VIS_OE 97
A0 80 Bit 0 of the 16-bit address bus
A1 78 Bit 1 of the 16-bit address bus
A2 74 Bit 2 of the 16-bit address bus
A3 71 Bit 3 of the 16-bit address bus
A4 68 Bit 4 of the 16-bit address bus
A5 64 Bit 5 of the 16-bit address bus
A6 61 Bit 6 of the 16-bit address bus
A7 57 Bit 7 of the 16-bit address bus
A8 53 Bit 8 of the 16-bit address bus
A9 51 Bit 9 of the 16-bit address bus
A10 48 Bit 10 of the 16-bit address bus
A11 45 Bit 11 of the 16-bit address bus
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
LF2407A
(144-PGE)
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
CCA
, VSS, or V
DDO
2406A
(100-PZ)
be isolated from the digital supply voltage (and V
SSO
LC2404A
(100-PZ)
) should be left unconnected. All power supply pins must be connected appropriately for proper
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
READY is pulled low to add wait states for external accesses.
READY indicates that an external device is prepared for a bus
transaction to be completed. If the device is not ready, it pulls the
READY pin low. The processor waits one cycle and checks
READY again. Note that the processor performs
READY-detection if at least one software wait state is
programmed. To meet the external READY timing parameters,
the wait-state generator control register (WSGR) should be
programmed for at least one wait state. (↑)
Microprocessor/Microcomputer mode select. If this pin is low
during reset, the device is put in microcomputer mode and
program execution begins at 0000h of internal program memory
(Flash EEPROM). A high value during reset puts the device in
microprocessor mode and program execution begins at 0000h
of external program memory. This line sets the MP/MC
in the SCSR2 register). (↓)
Active high to enable external interface signals. If pulled low, the
2407A behaves like the 2406A/2403A/2402A—i.e., it has no
external memory and generates an illegal address if DS
asserted. This pin has an internal pulldown. (↓)
Visibility output enable (active when data bus is output). This pin
is active (low) whenever the external data bus is driving as an
output during visibility mode. Can be used by external decode
logic to prevent data bus contention while running in visibility
mode.
from digital ground) to maintain the specified accuracy
SSA
bit (bit 2
is
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
I/O buffer supply +3.3 V. Digital logic and buffer supply
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
PIN NAME
A12 43 Bit 12 of the 16-bit address bus
A13 39 Bit 13 of the 16-bit address bus
A14 34 Bit 14 of the 16-bit address bus
A15 31 Bit 15 of the 16-bit address bus
D0 127 Bit 0 of 16-bit data bus (↑)
D1 130 Bit 1 of 16-bit data bus (↑)
D2 132 Bit 2 of 16-bit data bus (↑)
D3 134 Bit 3 of 16-bit data bus (↑)
D4 136 Bit 4 of 16-bit data bus (↑)
D5 138 Bit 5 of 16-bit data bus (↑)
D6 143 Bit 6 of 16-bit data bus (↑)
D7 5 Bit 7 of 16-bit data bus (↑)
D8 9 Bit 8 of 16-bit data bus (↑)
D9 13 Bit 9 of 16-bit data bus (↑)
D10 15 Bit 10 of 16-bit data bus (↑)
D11 17 Bit 11 of 16-bit data bus (↑)
D12 20 Bit 12 of 16-bit data bus (↑)
D13 22 Bit 13 of 16-bit data bus (↑)
D14 24 Bit 14 of 16-bit data bus (↑)
D15 27 Bit 15 of 16-bit data bus (↑)
#
V
DD
#
V
DDO
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
LF2407A
(144-PGE)
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
29 20 20 6
50 35 35 27
86 59 59 56
129 91 91
4 4 4 10
42 30 30 35
67 47 47 52
77 54 54
95 64 64
141 98 98
CCA
, VSS, or V
DDO
2406A
(100-PZ)
be isolated from the digital supply voltage (and V
SSO
LC2404A
(100-PZ)
) should be left unconnected. All power supply pins must be connected appropriately for proper
LC2402A
(64-PAG)
and
2402A
(64-PG)
POWER SUPPLY
DESCRIPTION
Core supply +3.3 V. Digital logic supply voltage.
I/O buffer supply +3.3 V. Digital logic and buffer supply
voltage.
from digital ground) to maintain the specified accuracy
SSA
DSP CONTROLLERS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
19
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
V
SSO
I/O buffer ground. Digital logic and buffer ground reference.
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
Core ground. Digital logic ground reference.
I/O buffer ground. Digital logic and buffer ground reference.
from digital ground) to maintain the specified accuracy
SSA
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
POWER SUPPLY (CONTINUED)
28 19 19 5
#
V
SS
49 34 34 26
85 58 58 55
128 90 90
3 3 3 9
41 29 29 34
66 46 46 51
V
SSO
#
76 53 53
94 63 63
125 97 97
140
†
Bold, italicized pin names indicate pin function after reset.
‡
GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
and improve the noise immunity of the ADC.
¶
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (VDD, V
be isolated from the digital supply voltage (and V
CCA
DDO
, VSS, or V
) should be left unconnected. All power supply pins must be connected appropriately for proper
SSO
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory maps
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
Hex Program
0000
0FFF
1000
3FFF
4000
6FFF
7000
7FFF
8000
87FF
8800
FDFF
FE00
FEFF
FF00
FFFF
Flash Sector 0 (4K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
On-Chip DARAM (B0)
†
(0040−0043h)
Flash Sector 1 (12K)
Flash Sector 2 (12K)
Flash Sector 3 (4K)
SARAM (2K)
Internal (PON = 1)
External (PON=0)
External
Reserved‡ (CNF = 1)
External (CNF = 0)
External (CNF = 0)
‡
(CNF = 1)
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0FFF
1000
6FFF
7000
7FFF
8000
FFFF
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (2K)
Internal (DON = 1)
Reserved (DON=0)
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
External
Hex I/O
0000
¶
External
FEFF
FF00
FF0E
FF0F
FF10
FFFE
FFFF
Flash Control Mode Register
Wait-State Generator Control
Reserved
Reserved
Register (On-Chip)
On-Chip Flash Memory (Sectored) − if MP/MC = 0
External Program Memory − if MP/MC
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
Addresses 0040h−0043h in on-chip program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved when
CNF = 1.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
= 1
SARAM (See Table 1 for details.)
Reserved or Illegal
Figure 1. TMS320LF2407A Memory Map
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
21
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
memory maps (continued)
Hex Program
0000
Flash Sector 0 (4K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
0FFF
1000
3FFF
4000
6FFF
7000
7FFF
8000
87FF
8800
FDFF
FE00
FEFF
FF00
On-Chip DARAM (B0)
FFFF
†
(0040−0043h)
Flash Sector 1 (12K)
Flash Sector 2 (12K)
Flash Sector 3 (4K)
SARAM (2K)
Internal (PON = 1)
Reserved (PON=0)
Illegal
Reserved
External (CNF = 0)
‡
‡
(CNF = 1)
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0FFF
1000
6FFF
7000
7FFF
8000
FFFF
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (2K)
Internal (DON = 1)
Reserved (DON = 0)
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
Illegal
Hex I/O
0000
¶
Illegal
FEFF
FF00
FF0E
FF0F
FF10
FFFE
FFFF
Flash Control Mode Register
Reserved
Reserved
Reserved
On-Chip Flash Memory (Sectored)
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
SARAM (See Table 1 for details.)
Reserved or Illegal
Figure 2. TMS320LF2406A Memory Map
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
ИИИИИИИИИ
ИИИИИИИИИ
ИИИИИИИИИ
ИИИИИИИИИ
ИИИИИИИИИ
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
memory maps (continued)
SPRS145K − JULY 2000 − REVISED AUGUST 2005
DSP CONTROLLERS
Hex
0000
0FFF
1000
3FFF
4000
7FFF
8000
81FF
8200
87FF
8800
Program
Flash Sector 0 (4K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Flash Sector 1 (12K)
Reserved
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
Reserved
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
07FF
0800
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
09FF
0A00
Reserved
0FFF
1000
6FFF
7000
Peripheral Memory-Mapped
Illegal
Registers (System, WD, ADC,
7FFF
8000
SCI, I/O, Interrupts)
Hex I/O
0000
¶
Illegal
FDFF
FDFF
FE00
FE00
FEFF
FEFF
FF00
FF00
On-Chip DARAM (B0)
FFFF
FFFF
On-Chip Flash Memory (Sectored)
Illegal
Reserved
‡
‡
(CNF = 1)
Reserved (CNF = 0)
Illegal
FFFF
FEFF
FF00
FF0E
FF0F
FF10
FFFE
Flash Control Mode Register
Reserved
Reserved
Reserved
FFFF
SARAM (See Table 1 for details.)
Reserved or Illegal
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
Figure 3. TMS320LF2403A Memory Map
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
23
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
memory maps (continued)
Hex
0000
0FFF
1000
1FFF
2000
7FFF
8000
81FF
8200
87FF
8800
Program
Flash Sector 0 (4K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Flash Sector 1 (4K)
Reserved
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
Reserved
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
09FF
0A00
0FFF
1000
6FFF
7000
7FFF
8000
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
Reserved
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
Hex I/O
0000
¶
Illegal
Illegal
FDFF
FDFF
FE00
FE00
Reserved
FEFF
FEFF
FF00
FF00
On-Chip DARAM (B0)
Reserved (CNF = 0)
FFFF
FFFF
On-Chip Flash Memory (Sectored)
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
‡
‡
(CNF = 1)
FFFF
Illegal
FEFF
FF00
FF0E
FF0F
FF10
FFFE
FFFF
Flash Control Mode Register
SARAM (See Table 1 for details.)
Reserved or Illegal
Reserved
Reserved
Reserved
Figure 4. TMS320LF2402A Memory Map
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
memory maps (continued)
SPRS145K − JULY 2000 − REVISED AUGUST 2005
DSP CONTROLLERS
Hex
0000
7FBF
7FC0
7FFF
8000
87FF
8800
Program
On-Chip ROM (32K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Reserved
SARAM (2K)
Internal (PON = 1)
Reserved (PON = 0)
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0FFF
1000
6FFF
7000
7FFF
8000
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (2K)
Internal (DON = 1)
Reserved (DON = 0)
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, CAN, I/O, Interrupts)
¶
Illegal
Reserved
Illegal
FDFF
FE00
Reserved
FEFF
FF00
On-Chip DARAM (B0)‡ (CNF = 1)
Reserved (CNF = 0)
FFFF
On-Chip ROM memory
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
‡
FFFF
SARAM (See Table 1 for details.)
Reserved or Illegal
Figure 5. TMS320LC2406A Memory Map
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
25
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
memory maps (continued)
Hex
0000
3FBF
3FC0
3FFF
4000
7FFF
8000
83FF
8400
Program
On-Chip ROM (16K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Reserved
Reserved
SARAM (1K)
Internal (PON = 1)
Reserved (PON = 0)
Reserved
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0BFF
0C00
6FFF
7000
7FFF
8000
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (1K)
Internal (DON = 1)
Reserved (DON = 0)
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, SPI, I/O, Interrupts)
¶
Illegal
FDFF
FE00
Reserved
FEFF
FF00
On-Chip DARAM (B0)‡ (CNF = 1)
Reserved (CNF = 0)
FFFF
On-Chip ROM memory
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
‡
FFFF
SARAM (See Table 1 for details.)
Reserved or Illegal
Figure 6. TMS320LC2404A Memory Map
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
memory maps (continued)
SPRS145K − JULY 2000 − REVISED AUGUST 2005
DSP CONTROLLERS
Hex
0000
3FBF
3FCO
3FFF
4000
7FFF
8000
81FF
8200
87FF
8800
Program
On-chip ROM (16K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Reserved
Reserved
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
Reserved
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
09FF
0A00
0FFF
1000
6FFF
7000
7FFF
8000
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
Reserved
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
¶
Illegal
FDFF
FE00
Reserved
FEFF
FF00
FFFF
On-Chip Flash Memory (Sectored)
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
On-Chip DARAM (B0)‡ (CNF = 1)
Reserved (CNF = 0)
‡
FFFF
Illegal
SARAM (See Table 1 for details.)
Reserved or Illegal
Figure 7. TMS320LC2403A Memory Map
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
27
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
memory maps (continued)
Hex
0000
17BF
17C0
17FF
1800
7FFF
8000
87FF
8800
Program
On-Chip ROM (6K)
Interrupt Vectors (0000−003Fh)
Reserved
User code begins at 0044h
†
(0040−0043h)
Reserved
Reserved
Reserved
Reserved
Hex Data
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0FFF
1000
6FFF
7000
7FFF
8000
Memory-Mapped
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM (B0)§ (CNF = 0)
Reserved (CNF = 1)
On-Chip DARAM (B1)
Reserved
Illegal
Reserved
Illegal
Peripheral Memory-Mapped
Registers (System, WD, ADC,
SCI, I/O, Interrupts)
¶
Illegal
FDFF
FE00
Reserved
FEFF
FF00
On-Chip DARAM (B0)
Reserved (CNF = 0)
FFFF
On-Chip ROM memory
†
Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
‡
‡
(CNF = 1)
FFFF
Reserved or Illegal
Figure 8. TMS320LC2402A Memory Map
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
peripheral memory map of the 2407A/2406A
Hex
0000
005F
0060
007F
0080
00FF
0100
01FF
0200
02FF
0300
03FF
0400
04FF
0500
07FF
0800
0FFF
1000
6FFF
7000
73FF
7400
743F
7440
74FF
7500
753F
7540
77EF
77F0
77F3
77F4
77FF
7800
7FFF
8000
FFFF
Illegal
Reserved
†
Available in LF2407A only
Memory-Mapped Registers
and Reserved
On-Chip DARAM B2
Illegal
Reserved
On-Chip DARAM B0
On-Chip DARAM B1
Reserved
Illegal
SARAM (2K)
Illegal
Peripheral Frame 1 (PF1)
Peripheral Frame 2 (PF2)
Illegal
Peripheral Frame 3 (PF3)
Illegal
Code Security Passwords
Reserved
Illegal
External
“Illegal” indicates that access to
these addresses causes a
nonmaskable interrupt (NMI).
“Reserved” indicates addresses that
are reserved for test.
†
SPRS145K − JULY 2000 − REVISED AUGUST 2005
Reserved
Interrupt-Mask Register
Reserved
Interrupt Flag Register
Emulation Registers
and Reserved
Illegal
System Configuration and
Control Registers
Watchdog Timer Registers
Illegal
SPI
SCI
Illegal
External-Interrupt Registers
Illegal
Digital I/O Control Registers
ADC Control Registers
Illegal
CAN Control Registers
Illegal
CAN Mailbox
Illegal
Event Manager − EVA
General-Purpose
Timer Registers
Compare, PWM, and
Deadband Registers
Capture and QEP Registers
Interrupt Mask, Vector and
Flag Registers
Illegal
Event Manager − EVB
General-Purpose
Timer Registers
Compare, PWM, and
Deadband Registers
Capture and QEP Registers
Interrupt Mask, Vector, and
Flag Registers
Reserved
DSP CONTROLLERS
Hex
0000
0003
0004
0005
0006
0007
005F
7000−700F
7010−701F
7020−702F
7030−703F
7040−704F
7050−705F
7060−706F
7070−707F
7080−708F
7090−709F
70A0−70BF
70C0−70FF
7100−710E
710F−71FF
7200−722F
7230−73FF
7400−7408
7411−7419
7420−7429
742C−7431
7432−743F
7500−7508
7511−7519
7520−7529
752C−7531
7532−753F
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
29
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K − JULY 2000 − REVISED AUGUST 2005
device reset and interrupts
The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types
of interrupt sources.
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
− External interrupts are generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the
CPU interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
− Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in
each peripheral and by the CPU IMR, which can mask each maskable interrupt line at the DSP core.
D Software-generated interrupts for the LF240xA devices include:
− The INTR instruction. This instruction allows initialization of any LF240xA interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
− The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only
software activation is provided.
− The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
− An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to
share the six core level interrupts. Figure 9 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 9) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely
code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x − plus additional
interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt
grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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