TEXAS INSTRUMENTS TMS320F28335, TMS320F28334, TMS320F28332 Technical data

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

Data Manual

Literature Number: SPRS439B

June 2007 – Revised October 2007

ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Contents

Revision History .......................................................................................................................... 10

1 TMS320F28335, TMS320F28334, TMS320F28332 DSCs ............................................................ 11

1.1 Features ..................................................................................................................... 11

1.2 Getting Started .............................................................................................................. 12

2 Introduction ....................................................................................................................... 13

2.1 Pin Assignments ............................................................................................................ 13

2.2 Signal Descriptions ......................................................................................................... 23

3 Functional Overview ........................................................................................................... 32

3.1 Memory Maps .............................................................................................................. 33

3.2 Brief Descriptions ........................................................................................................... 39

3.2.1 C28x CPU ....................................................................................................... 39

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 40

3.2.3 Peripheral Bus .................................................................................................. 40

3.2.4 Real-Time JTAG and Analysis ................................................................................ 40

3.2.5 External Interface (XINTF) ..................................................................................... 40

3.2.6 Flash .............................................................................................................. 40

3.2.7 M0, M1 SARAMs ............................................................................................... 41

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 41

3.2.9 Boot ROM ........................................................................................................ 41

3.2.10 Security .......................................................................................................... 42

3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 43

3.2.12 External Interrupts (XINT1-XINT7, XNMI) .................................................................... 43

3.2.13 Oscillator and PLL .............................................................................................. 44

3.2.14 Watchdog ........................................................................................................ 44

3.2.15 Peripheral Clocking ............................................................................................. 44

3.2.16 Low-Power Modes .............................................................................................. 44

3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 44

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 45

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 45

3.2.20 Control Peripherals ............................................................................................. 45

3.2.21 Serial Port Peripherals ......................................................................................... 46

3.3 Register Map ................................................................................................................ 46

3.4 Device Emulation Registers ............................................................................................... 48

3.5 Interrupts .................................................................................................................... 49

3.5.1 External Interrupts .............................................................................................. 53

3.6 System Control ............................................................................................................. 53

3.6.1 OSC and PLL Block ............................................................................................ 55

3.6.2 Watchdog Block ................................................................................................. 58

3.7 Low-Power Modes Block .................................................................................................. 59

4 Peripherals ........................................................................................................................ 60

4.1 DMA Overview .............................................................................................................. 61

4.2 32-Bit CPU-Timers 0/1/2 .................................................................................................. 62

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 64

4.4 High-Resolution PWM (HRPWM) ........................................................................................ 66

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ............................................................................ 67

4.6 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 69

4.7 Analog-to-Digital Converter (ADC) Module ............................................................................. 71

4.7.1 ADC Connections if the ADC Is Not Used ................................................................... 74

4.7.2 ADC Registers ................................................................................................... 74

4.7.3 ADC Calibration .................................................................................................. 75

Contents 2 Submit Documentation Feedback

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

4.8 Multichannel Buffered Serial Port (McBSP) Module ................................................................... 76

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 79

4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) ........................................... 84

4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ...................................................................... 88

4.12 Inter-Integrated Circuit (I2C) .............................................................................................. 91

4.13 GPIO MUX .................................................................................................................. 93

4.14 External Interface (XINTF) ................................................................................................ 98

5 Device Support ................................................................................................................. 101

5.1 Device and Development Support Tool Nomenclature .............................................................. 101

5.2 Documentation Support .................................................................................................. 103

6 Electrical Specifications .................................................................................................... 106

6.1 Absolute Maximum Ratings ............................................................................................. 106

6.2 Recommended Operating Conditions .................................................................................. 107

6.3 Electrical Characteristics ................................................................................................ 107

6.4 Current Consumption .................................................................................................... 108

6.4.1 Reducing Current Consumption ............................................................................. 111

6.4.2 Current Consumption Graphs ................................................................................ 112

6.4.2.1 Thermal Design Considerations .............................................................................. 113

6.5 Emulator Connection Without Signal Buffering for the DSP ........................................................ 113

6.6 Timing Parameter Symbology ........................................................................................... 114

6.6.1 General Notes on Timing Parameters ....................................................................... 114

6.6.2 Test Load Circuit .............................................................................................. 114

6.6.3 Device Clock Table ........................................................................................... 114

6.7 Clock Requirements and Characteristics ............................................................................. 116

6.8 Power Sequencing ........................................................................................................ 117

6.8.1 Power Management and Supervisory Circuit Solutions ................................................... 117

6.9 General-Purpose Input/Output (GPIO) ................................................................................. 120

6.9.1 GPIO - Output Timing ......................................................................................... 120

6.9.2 GPIO - Input Timing ........................................................................................... 121

6.9.3 Sampling Window Width for Input Signals .................................................................. 122

6.9.4 Low-Power Mode Wakeup Timing ........................................................................... 123

6.10 Enhanced Control Peripherals .......................................................................................... 126

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ........................................................ 126

6.10.2 Trip-Zone Input Timing ........................................................................................ 126

6.10.3 External Interrupt Timing ...................................................................................... 128

6.10.4 I2C Electrical Specification and Timing ..................................................................... 129

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing .................................................... 129

6.10.6 SPI Slave Mode Timing ....................................................................................... 133

6.10.7 External Interface (XINTF) Timing ........................................................................... 135

6.10.8 XHOLD and XHOLDA Timing ................................................................................ 147

6.10.9 On-Chip Analog-to-Digital Converter ........................................................................ 150

6.10.10 Detailed Descriptions ........................................................................................ 155

6.10.11 Multichannel Buffered Serial Port (McBSP) Timing ....................................................... 156

7 Thermal/Mechanical Data ................................................................................................... 162

Contents 3

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

List of Figures

2-1 F28335, F28334, F28332 176-Pin PGF LQFP (Top View) .................................................................. 14

2-2 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .................... 15

2-3 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View) .................. 16

2-4 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .................... 17

2-5 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View) .................. 18

2-6 F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View) ........................... 19

2-7 F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View) .......................... 20

2-8 F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View) ........................... 21

2-9 F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View) .......................... 22

3-1 Functional Block Diagram ....................................................................................................... 32

3-2 F28335 Memory Map ............................................................................................................. 34

3-3 F28334 Memory Map ............................................................................................................. 35

3-4 F28332 Memory Map ............................................................................................................. 36

3-5 External and PIE Interrupt Sources ............................................................................................. 49

3-6 External Interrupts ................................................................................................................ 50

3-7 Multiplexing of Interrupts Using the PIE Block ................................................................................ 51

3-8 Clock and Reset Domains ....................................................................................................... 54

3-9 OSC and PLL Block Diagram ................................................................................................... 55

3-10 Using a 3.3-V External Oscillator ............................................................................................... 56

3-11 Using a 1.9-V External Oscillator ............................................................................................... 56

3-12 Using the Internal Oscillator ..................................................................................................... 56

3-13 Watchdog Module ................................................................................................................. 58

4-1 DMA Functional Block Diagram ................................................................................................. 61

4-2 CPU-Timers ........................................................................................................................ 62

4-3 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 62

4-4 Multiple PWM Modules in a F2833x System .................................................................................. 64

4-5 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 66

4-6 eCAP Functional Block Diagram ................................................................................................ 67

4-7 eQEP Functional Block Diagram ................................................................................................ 69

4-8 Block Diagram of the ADC Module ............................................................................................. 72

4-9 ADC Pin Connections With Internal Reference ............................................................................... 73

4-10 ADC Pin Connections With External Reference .............................................................................. 73

4-11 McBSP Module ................................................................................................................... 77

4-12 eCAN Block Diagram and Interface Circuit .................................................................................... 80

4-13 eCAN-A Memory Map ............................................................................................................ 81

4-14 eCAN-B Memory Map ............................................................................................................ 82

4-15 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 87

4-16 SPI Module Block Diagram (Slave Mode) ..................................................................................... 90

4-17 I2C Peripheral Module Interfaces ............................................................................................... 92

List of Figures4 Submit Documentation Feedback

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

4-18 GPIO MUX Block Diagram ....................................................................................................... 93

4-19 Qualification Using Sampling Window .......................................................................................... 98

4-20 External Interface Block Diagram ............................................................................................... 99

4-21 Typical 16-bit Data Bus XINTF Connections .................................................................................. 99

4-22 Typical 32-bit Data Bus XINTF Connections ................................................................................. 100

5-1 Example of F2833x Device Nomenclature ................................................................................... 102

6-1 Typical Operational Current Versus Frequency (F28335/F28334) ........................................................ 112

6-2 Typical Operational Power Versus Frequency (F28335/F28334) ......................................................... 112

6-3 Emulator Connection Without Signal Buffering for the DSP ............................................................... 113

6-4 3.3-V Test Load Circuit ......................................................................................................... 114

6-5 Clock Timing ..................................................................................................................... 117

6-6 Power-on Reset .................................................................................................................. 118

6-7 Warm Reset ...................................................................................................................... 119

6-8 Example of Effect of Writing Into PLLCR Register .......................................................................... 120

6-9 General-Purpose Output Timing ............................................................................................... 120

6-10 Sampling Mode .................................................................................................................. 121

6-11 General-Purpose Input Timing ................................................................................................. 122

6-12 IDLE Entry and Exit Timing .................................................................................................... 123

6-13 STANDBY Entry and Exit Timing Diagram ................................................................................... 124

6-14 HALT Wake-Up Using GPIOn ................................................................................................. 125

6-15 PWM Hi-Z Characteristics ...................................................................................................... 126

6-16 ADCSOCAO or ADCSOCBO Timing ......................................................................................... 128

6-17 External Interrupt Timing ....................................................................................................... 128

6-18 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 131

6-19 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 133

6-20 SPI Slave Mode External Timing (Clock Phase = 0) ........................................................................ 134

6-21 SPI Slave Mode External Timing (Clock Phase = 1) ........................................................................ 135

6-22 Relationship Between XTIMCLK and SYSCLKOUT ........................................................................ 138

6-23 Example Read Access .......................................................................................................... 140

6-24 Example Write Access .......................................................................................................... 141

6-25 Example Read With Synchronous XREADY Access ....................................................................... 143

6-26 Example Read With Asynchronous XREADY Access ...................................................................... 144

6-27 Write With Synchronous XREADY Access ................................................................................... 146

6-28 Write With Asynchronous XREADY Access ................................................................................. 147

6-29 External Interface Hold Waveform ............................................................................................ 148

6-30 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................... 149

6-31 ADC Power-Up Control Bit Timing ............................................................................................ 151

6-32 ADC Analog Input Impedance Model ......................................................................................... 152

6-33 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 153

6-34 Simultaneous Sampling Mode Timing ........................................................................................ 154

6-35 McBSP Receive Timing ......................................................................................................... 157

List of Figures 5

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

6-36 McBSP Transmit Timing ........................................................................................................ 158

6-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 .................................................... 159

6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 .................................................... 159

6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 .................................................... 160

6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 .................................................... 161

List of Figures6 Submit Documentation Feedback

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

List of Tables

2-1 Hardware Features ............................................................................................................... 13

2-2 Signal Descriptions ............................................................................................................... 23

3-1 Addresses of Flash Sectors in F28335 ......................................................................................... 37

3-2 Addresses of Flash Sectors in F28334 ......................................................................................... 37

3-3 Addresses of Flash Sectors in F28332 ......................................................................................... 37

3-4 Handling Security Code Locations .............................................................................................. 38

3-5 Wait-states ......................................................................................................................... 39

3-6 Boot Mode Selection .............................................................................................................. 42

3-7 Peripheral Frame 0 Registers .................................................................................................. 46

3-8 Peripheral Frame 1 Registers ................................................................................................... 47

3-9 Peripheral Frame 2 Registers ................................................................................................... 47

3-10 Peripheral Frame 3 Registers ................................................................................................... 47

3-11 Device Emulation Registers ..................................................................................................... 48

3-12 PIE Peripheral Interrupts ........................................................................................................ 51

3-13 PIE Configuration and Control Registers ...................................................................................... 52

3-14 External Interrupt Registers ...................................................................................................... 53

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 55

3-16 PLLCR Bit Descriptions .......................................................................................................... 57

3-17 CLKIN Divide Options ............................................................................................................ 57

3-18 Possible PLL Configuration Modes ............................................................................................. 57

3-19 Low-Power Modes ................................................................................................................ 59

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 63

4-2 ePWM Control and Status Registers ........................................................................................... 65

4-3 eCAP Control and Status Registers ............................................................................................ 68

4-4 eQEP Control and Status Registers ............................................................................................ 70

4-5 ADC Registers ..................................................................................................................... 74

4-6 McBSP Register Summary ...................................................................................................... 78

4-7 3.3-V eCAN Transceivers ....................................................................................................... 80

4-8 CAN Register Map ............................................................................................................... 83

4-9 SCI-A Registers .................................................................................................................. 85

4-10 SCI-B Registers .................................................................................................................. 85

4-11 SCI-C Registers .................................................................................................................. 86

4-12 SPI-A Registers ................................................................................................................... 89

4-13 I2C-A Registers .................................................................................................................... 92

4-14 GPIO Registers ................................................................................................................... 94

4-15 GPIO-A Mux Peripheral Selection Matrix ..................................................................................... 95

4-16 GPIO-B Mux Peripheral Selection Matrix ..................................................................................... 96

4-17 GPIO-C Mux Peripheral Selection Matrix ..................................................................................... 97

4-18 XINTF Configuration and Control Register Mapping ........................................................................ 100

List of Tables 7

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

6-1 TMS320F28335 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ............................ 108

6-2 TMS320F28334 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ............................ 109

6-3 TMS320F28332 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ........................... 110

6-4 Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 111

6-5 Clocking and Nomenclature (150-MHz devices) ............................................................................ 115

6-6 Clocking and Nomenclature (100-MHz devices) ............................................................................ 115

6-7 Input Clock Frequency .......................................................................................................... 116

6-8 XCLKIN Timing Requirements - PLL Enabled ............................................................................... 116

6-9 XCLKIN Timing Requirements - PLL Disabled .............................................................................. 116

6-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 116

6-11 Power Management and Supervisory Circuit Solutions .................................................................... 117

6-12 Reset ( XRS) Timing Requirements ........................................................................................... 119

6-13 General-Purpose Output Switching Characteristics ......................................................................... 120

6-14 General-Purpose Input Timing Requirements ............................................................................... 121

6-15 IDLE Mode Timing Requirements ............................................................................................. 123

6-16 IDLE Mode Switching Characteristics ......................................................................................... 123

6-17 STANDBY Mode Timing Requirements ...................................................................................... 123

6-18 STANDBY Mode Switching Characteristics ................................................................................. 124

6-19 HALT Mode Timing Requirements ............................................................................................ 124

6-20 HALT Mode Switching Characteristics ....................................................................................... 125

6-21 ePWM Timing Requirements................................................................................................... 126

6-22 ePWM Switching Characteristics .............................................................................................. 126

6-23 Trip-Zone input Timing Requirements ........................................................................................ 126

6-24 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 150 MHz) .............................................. 127

6-25 Enhanced Capture (eCAP) Timing Requirement ............................................................................ 127

6-26 eCAP Switching Characteristics ............................................................................................... 127

6-27 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................... 127

6-28 eQEP Switching Characteristics ............................................................................................... 127

6-29 External ADC Start-of-Conversion Switching Characteristics .............................................................. 127

6-30 External Interrupt Timing Requirements ...................................................................................... 128

6-31 External Interrupt Switching Characteristics ................................................................................. 128

6-32 I2C Timing ....................................................................................................................... 129

6-33 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 130

6-34 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 132

6-35 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 133

6-36 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 134

6-37 Relationship Between Parameters Configured in XTIMING and Duration of Pulse .................................... 135

6-38 XINTF Clock Configurations .................................................................................................... 137

6-39 External Interface Read Timing Requirements .............................................................................. 139

6-40 External Interface Read Switching Characteristics .......................................................................... 139

6-41 External Interface Write Switching Characteristics .......................................................................... 140

List of Tables8 Submit Documentation Feedback

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

6-42 External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) .................................... 141

6-43 External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ........................................ 141

6-44 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ......................................... 142

6-45 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ........................................ 142

6-46 External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) .................................... 145

6-47 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ......................................... 145

6-48 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ........................................ 145

6-49 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ....................................................... 148

6-50 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................... 149

6-51 ADC Electrical Characteristics (over recommended operating conditions) .............................................. 150

6-52 ADC Power-Up Delays .......................................................................................................... 151

6-53 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ......................................... 151

6-54 Sequential Sampling Mode Timing ............................................................................................ 153

6-55 Simultaneous Sampling Mode Timing ........................................................................................ 154

6-56 McBSP Timing Requirements .................................................................................................. 156

6-57 McBSP Switching Characteristics ............................................................................................. 156

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................. 158

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ............................. 158

6-60 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................. 159

6-61 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ............................. 159

6-62 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................. 160

6-63 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ............................. 160

6-64 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................. 160

6-65 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ............................. 161

7-1 F2833x Thermal Model 176-pin PGF Results ............................................................................... 162

7-2 F2833x Thermal Model 179-pin ZHH Results ............................................................................... 162

7-3 F2833x Thermal Model 176-pin ZJZ Results ............................................................................... 162

List of Tables 9

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

The table lists the technical changes made for this revision.

Location Additions, Deletions, Modifications

Global Changed 1.8 V to 1.9 V

Section 2.2 Modified type on the MCLKXB option of GPIO26 in the Signal Descriptions table
Section 3.1 Added bullets at the beginning of the Memory Maps section

Figure 3-2 – Figure 3-4 Modified all three memory map figures

Table 3-5 Modified Wait-states table

Section 4.7.3 Modified the ADC Calibration section

Section 4.8 Modified clock rate equation in the McBSP Module section
Figure 4-18 Added note to GPIO MUX Block Diagram

Table 4-16 Modified GPIO-B Mux Peripheral Selection Matrix

Figure 5-1 Modified device nomenclature example figure

Section 6.2 Modified clock frequency in Recommended Operating Conditions table

Table 6-5 Modified the LSPCLK values in the Clocking and Nomenclature (150-MHz devices) table

Table 6-6 Modified the HSPCLK value in the Clocking and Nomenclature (100-MHz devices) table
Table 6-53 Modified the Current Consumption for Different ADC Configurations table
Table 6-54 Modified the values in Sequential Sampling Mode Timing table
Table 6-55 Modified the values in Simultaneous Sampling Mode Timing table

Revision History

Changes Made in Revision B

Revision History10 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

1 TMS320F28335, TMS320F28334, TMS320F28332 DSCs

1.1 Features

• High-Performance Static CMOS Technology

– Up to 150 MHz (6.67-ns Cycle Time)
– 1.9-V Core, 3.3-V I/O Design

• High-Performance 32-Bit CPU (TMS320C28x)

– IEEE-754 Single-Precision Floating-Point

Unit (FPU)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)

• Six Channel DMA Controller (for ADC, McBSP,

XINTF, and SARAM) – Two Sample-and-Hold

• 16-bit or 32-bit External Interface (XINTF)

– Over 2M x 16 Address Reach

• On-Chip Memory

– F28335: 256K x 16 Flash, 34K x 16 SARAM
– F28334:128K x 16 Flash, 34K x 16 SARAM
– F28332: 64K x 16 Flash, 26K x 16 SARAM
– 1K x 16 OTP ROM

• Boot ROM (8K x 16)

– With Software Boot Modes (via SCI, SPI,

CAN, I2C, McBSP, XINTF, and Parallel I/O)
– Standard Math Tables

• Clock and System Control

– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module

• GPIO0 to GPIO63 Pins Can Be Connected to

One of the Eight External Core Interrupts – Disable Individual Peripheral Clocks

• Peripheral Interrupt Expansion (PIE) Block • Package Options

That Supports All 58 Peripheral Interrupts

• 128-Bit Security Key/Lock

– Protects Flash/OTP/RAM Blocks
– Prevents Firmware Reverse Engineering

• Enhanced Control Peripherals

– Up to 18 PWM Outputs
– Up to 6 HRPWM Outputs With 150 ps MEP

Resolution
– Up to 6 Event Capture Inputs Boundary Scan Architecture

– Up to 2 Quadrature Encoder Interfaces
– Up to 8 32-bit/Six 16-bit Timers

• Three 32-Bit CPU Timers

• Serial Port Peripherals

– Up to 2 CAN Modules
– Up to 3 SCI (UART) Modules
– Up to 2 McBSP Modules (Configurable as

SPI)
– One SPI Module
– One Inter-Integrated-Circuit (I2C) Bus

• 12-Bit ADC, 16 Channels

– 80-ns Conversion Rate
– 2 x 8 Channel Input Multiplexer

– Single/Simultaneous Conversions
– Internal or External Reference

• Up to 88 Individually Programmable,

Multiplexed GPIO Pins With Input Filtering

• JTAG Boundary Scan Support

• Advanced Emulation Features

– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware

• Development Support Includes

– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– Digital Motor Control and Digital Power

Software Libraries

• Low-Power Modes and Power Savings

– IDLE, STANDBY, HALT Modes Supported

– Lead-free Green Packaging
– Thin Quad Flatpack (PGF)
– MicroStar BGA™ (ZHH)
– Plastic BGA (ZJZ)

• Temperature Options:
– A: –40 ° C to 85 ° C (PGF, ZHH, ZJZ)

– S: –40 ° C to 125 ° C (ZJZ)

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

(1)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, TMS320C54x, TMS320C55x, C28x are trademarks of Texas
Instruments.

ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.

Copyright © 2007–2007, Texas Instruments Incorporated

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:

• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

12 TMS320F28335, TMS320F28334, TMS320F28332 DSCs Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

2 Introduction

The TMS320F28335, TMS320F28334, and TMS320F28332, devices, members of the TMS320C28x™
DSC generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, TMS320F28335, TMS320F28334, and TMS320F28332, are abbreviated as
F28335, F28334, and F28332, respectively. Table 2-1 provides a summary of features for each device.

Table 2-1. Hardware Features

FEATURE F28335 (150 MHz) F28334 (150 MHz) F28332 (100 MHz)

Instruction cycle 6.67 ns 6.67 ns 10 ns
Floating-point Unit Yes Yes Yes

3.3-V on-chip flash (16-bit word) 256K 128K 64K
Single-access RAM (SARAM) (16-bit word) 34K 34K 26K
One-time programmable (OTP) ROM

(16-bit word)
Code security for on-chip flash/SARAM/OTP

blocks
Boot ROM (8K X16) Yes Yes Yes
16/32-bit External Interface (XINTF) Yes Yes Yes
6-channel Direct Memory Access (DMA) Yes Yes Yes
PWM outputs ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6
HRPWM channels ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A
32-bit Capture inputs or auxiliary PWM outputs 6 6 4
32-bit QEP channels (four inputs/channel) 2 2 2
Watchdog timer Yes Yes Yes

No. of channels 16 16 16

12-Bit ADC MSPS 12.5 12.5 12.5

Conversion time 80 ns 80 ns 80 ns
32-Bit CPU timers 3 3 3
Multichannel Buffered Serial Port (McBSP)/SPI 2 2 1
Serial Peripheral Interface (SPI) 1 1 1
Serial Communications Interface (SCI) 3 3 2
Enhanced Controller Area Network (eCAN) 2 2 2
Inter-Integrated Circuit (I2C) 1 1 1
General Purpose I/O pins (shared) 88 88 88
External interrupts 8 8 8

176-Pin PGF Yes Yes Yes
Packaging 179-Ball ZHH Yes Yes Yes

176-Ball ZJZ Yes Yes Yes

Temperature options

Product status TMX TMX TMX

A: –40 ° C to 85 ° C (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ) (PGF, ZHH, ZJZ)

S: –40 ° C to 125 ° C (ZJZ) (ZJZ) (ZJZ)

1K 1K 1K

Yes Yes Yes

2.1 Pin Assignments

The 176-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1 . The 179-ball
ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5 . The 176-ball
ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through

Figure 2-9 .Table 2-2 describes the function(s) of each pin.

Submit Documentation Feedback Introduction 13

www.ti.com

ADVANCE INFORMATION

88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

1

15

114

113

112

11

1

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

GPIO48/ECAP5/XD31
TCK
EMU1
EMU0
V

DD3VFL

V

SS

TEST2
TEST1
XRS
TMS
TRST
TDO
TDI
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO27/ECAP4/EQEP2S/MFSXB
GPIO26/ECAP3/EQEP2I/MCLKXB
V

DDIO

V

SS

GPIO25/ECAP2/EQEP2B/MDRB
GPIO24/ECAP1/EQEP2A/MDXB
GPIO23/EQEP1I/MFSXA/SCIRXDB
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO21/EQEP1B/MDRA/CANRXB
GPIO20/EQEP1A/MDXA/CANTXB
GPIO19/ /SCIRXDB/CANTXASPISTEA
GPIO18/SPICLKA/SCITXDB/CANRXA
V

DD

V

SS

V

DD2A18

V

SS2AGND

ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
V

DDAIO

GPIO75/XD4

GPIO74/XD5

GPIO73/XD6

GPIO72/XD7

GPIO71/XD8

GPIO70/XD9

V

DDVSS

GPIO69/XD10

GPIO68/XD11

GPIO67/XD12

V

DDIOVSS

GPIO66/XD13

V

SSVDD

GPIO65/XD14

GPIO64/XD15

GPIO63/SCITXDC/XD16

GPIO62/SCIRXDC/XD17

GPIO61/MFSRB/XD18

GPIO60/MCLKRB/XD19

GPIO59/MFSRA/XD20

V

DDVSSVDDIOVSS

XCLKIN

X1

V

SS

X2

V

DD

GPIO58/MCLKRA/XD21

GPIO57/ /XD22SPISTEA

GPIO56/SPICLKA/XD23

GPIO55/SPISOMIA/XD24

GPIO54/SPISIMOA/XD25

GPIO53/EQEP1I/XD26

GPIO52/EQEP1S/XD27

V

DDIOVSS

GPIO51/EQEP1B/XD28

GPIO50/EQEP1A/XD29

GPIO49/ECAP6/XD30

GPIO30/CANRXA/XA18

GPIO29/SCITXDA/XA19

V

SS

V

DD

GPIO0/EPWM1A

GPIO1/EPWM1B/ECAP6/MFSRB

GPIO2/EPWM2A

V

SS

V

DDIO

GPIO3/EPWM2B/ECAP5/MCLKRB

GPIO4/EPWM3A

GPIO5/EPWM3B/MFSRA/ECAP1

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

V

SS

V

DD

GPIO7/EPWM4B/MCLKRA/ECAP2

GPIO8/EPWM5A/CANTXB/

ADCSOCAO

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO10/EPWM6A/CANRXB/

ADCSOCBO

GPIO1

1/EPWM6B/SCIRXDB/ECAP4

GPIO12 /CANTXB/MDXB/TZ1

V

SS

V

DD

GPIO13/ /CANRXB/MDRBTZ2

GPIO14/ /XHOLD/ /

TZ3 SCITXDBMCLKXB

GPIO15/ /XHOLDATZ4 /SCIRXDB/MFSXB

GPIO16/SPISIMOA/CANTXB/TZ5

GPIO17/SPISOMIA/CANRXB/TZ6

V

D

D

V

SS

V

DD1A18

V

SS1AGND

V

SSA2

V

DDA2

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

V

SSAIO

GPIO76/XD3

GPIO77/XD2

GPIO78/XD1

GPIO79/XD0

GPIO38/XWE0

XCLKOUT

V

DD

V

SS

GPIO28/SCIRXDA/XZCS6

GPIO34/ECAP1/XREADY

V

DDIO

V

SS

GPIO36/SCIRXDA/XZCS0

V

DD

V

SS

GPIO35/SCITXDA/XR/W

XRD

GPIO37/ECAP2/XZCS7

GPIO40/XA0/XWE1

GPIO41/XA1
GPIO42/XA2

V

DD

V

SS

GPIO43/XA3
GPIO44/XA4
GPIO45/XA5

V

DDIO

V

SS

GPIO46/XA6
GPIO47/XA7
GPIO80/XA8
GPIO81/XA9

GPIO82/XA10

V

SS

V

DD

GPIO83/XA11

GPIO84/XA12

V

DDIO

V

SS

GPIO85/XA13
GPIO86/XA14
GPIO87/XA15
GPIO39/XA16

GPIO31/CANTXA/XA17

GPIO28/SCIRXDA/XZCS6

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Introduction 14 Submit Documentation Feedback

Figure 2-1. F28335, F28334, F28332 176-Pin PGF LQFP (Top View)

www.ti.com

ADVANCE INFORMATION

ADCINB0 ADCINB2 ADCINB6 ADCREFP

ADCINA1

ADCRESEXTADCINA2

ADCLO

ADCINA0 ADCINB4

V

SS1AGND

ADCINA4

ADCINA3 ADCINB3

ADCREFIN

P P

N N

M M

L LADCINA5

GPIO18/
SPICLKA/
SCITXDB/

CANRXA

V

SSA2

ADCINA7 ADCINB7

GPIO17/

SPISOMIA/

CANRXB/

TZ6

V

DD1A18

V

DD

GPIO14/

/

SCITXDB/

MCLKXB

TZ3XHOLD/

GPIO13/

CANRXB/

MDRB

TZ2/

V

DDAIO

K K

J J

H H

1 2 3 4 5

6 7

GPIO20/

EQEP1A/

MDXA/

CANTXB

V

SS2AGND

GPIO21/

EQEP1B/

MDRA/

CANRXB

GPIO22/
EQEP1S/
MCLKXA/
SCITXDB

V

SS

1 2

3

4

5 6

7

V

SSAIO

V

SS

V

DD

V

DD

GPIO23/
EQEP1I/

MFSXA/

SCIRXDB

GPIO19/

SCIRXDB/

CANTXA

SPISTEA/

ADCINA6

GPIO16/

SPISIMOA/

CANTXB/

TZ5

GPIO15/

/

SCIRXDB/

MFSXB

TZ4XHOLDA/

V

DDA2

V

DD2A18

ADCREFMADCINB5ADCINB1

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-2. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View)

Submit Documentation Feedback Introduction 15

www.ti.com

ADVANCE INFORMATION

GPIO50/

EQEP1A/

XD29

TMS TEST2

EMU1

GPIO51/

EQEP1B/

XD28

GPIO48/

ECAP5/

XD31

TCK

GPIO52/

EQEP1S/

XD27

V

SS

GPIO27/

ECAP4/

EQEP2S/

MFSXB

XRS

EMU0

GPIO53/
EQEP1I/

XD26

V

DD

GPIO55/

SPISOMIA/

XD24

V

SS

GPIO56/

SPICLKA/

XD23

GPIO58/

MCLKRA/

XD21

GPIO33/

SCLA/

EPWMSYNCO/

ADCSOCBO

TRST

GPIO32/

SDAA/

EPWMSYNCI/

ADCSOCAO

V

DDIO

8 9

10 11 12 13 14

PP

NN

MM

LL

KK

J

J

HH

GPIO57/

/

XD22

SPISTEA

X1

XCLKIN

GPIO59/
MFSRA/

XD20

V

SS

GPIO25/

ECAP2/

EQEP2B/

MDRB

V

SS

V

DD

V

SS

8 9 10

11 12

13

14

V

SS

V

SS

TEST1

V

DD3VFL

GPIO24/

ECAP1/

EQEP2A/

MDXB

GPIO26/

ECAP3/
EQEP2I/
MCLKXB

TDO

V

DDIO

V

SS

X2

GPIO54/

SPISIMOA/

XD25

TDI

V

DDIO

GPIO49/

ECAP6/

XD30

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-3. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)

Introduction 16 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

GPIO11

EPWM6B

SCIRXDB

ECAP4

/

/

/

GPIO12

CANTXB

MDXB

TZ1//

/

GPIO10
EPWM6A
CANRXB

ADCSOCBO

/

/
/

GPIO9/
EPWM5B/
SCITXDB/

ECAP3

GPIO81/

XA9

GPIO8/

EPWM5A/

CANTXB/

ADCSOCAO

GPIO7/

EPWM4B/

MCLKRA/

ECAP2

GPIO84/

XA12

GPIO6/

EPWM4A/

EPWMSYNCI/

EPWMSYNCO

GPIO4/

EPWM3A

GPIO5/

EPWM3B/

MFSRA/

ECAP1

GPIO3/

EPWM2B/

ECAP5/

MCLKRB

V

DDIO

V

DDIO

V

SS

GPIO2/

EPWM2A

GPIO1/

EPWM1B/

ECAP6/
MFSRB

GPIO86/

XA14

GPIO83/

XA11

G

F

E

D

GPIO0/

EPWM1A

GPIO29/

SCITXDA/

XA19

V

SS

GPIO85/

XA13

GPIO82/

XA10

V

DD

GPIO30/

CANRXA/

XA18

GPIO39/

XA16

V

SS

V

DD

GPIO31/

CANTXA/

XA17

GPIO87/

XA15

V

DDIO

C

B

A

1 2 3 4 5 6 7

G

F

E

D

C

B

A

V

SS

GPIO45/

XA5

V

SS

GPIO80/

XA8

GPIO46/

XA6

GPIO43/

XA3

GPIO44/

XA4

GPIO47/

XA7

V

SS

1 2 3 4 5

6 7

V

SS

V

DD

V

SS

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-4. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View)

Submit Documentation Feedback Introduction 17

www.ti.com

ADVANCE INFORMATION

GPIO60/

MCLKRB/

XD19

GPIO64/

XD15

GPIO63/

SCITXDC/

XD16

GPIO61/
MFSRB/

XD18

GPIO67/

XD12

GPIO65/

XD14

GPIO62/

SCIRXDC

XD17

GPIO78/

XD1

GPIO79/

XD0

GPIO66/

XD13

GPIO68/

XD11

V

SS

GPIO37/

ECAP2/

XZCS7

GPIO34/

ECAP1/

XREADY

GPIO38/

XWE0

GPIO70/

XD9

G

F

E

D

V

DD

GPIO40/

XA0/

XWE1

V

SS

XCLKOUT

GPIO73/

XD6

GPIO42/

XA2

XRD

GPIO28/

SCIRXDA/

XZCS6

V

DD

GPIO35/

SCITXDA/

XR/W

GPIO69/

XD10

V

DDIO

C

B

A

8 9 10 11 12 13 14

G

F

E

D

C

B

A

GPIO74/

XD5

GPIO76/

XD3

GPIO72/

XD7

GPIO75/

XD4

GPIO77/

XD2

V

SS

GPIO41/

XA1

V

SS

V

DD

V

SS

8 9

10 11 12 13 14

V

SS

V

DD

V

SS

V

DDIO

GPIO36/

SCIRXDA/

XZCS0

V

DD

GPIO71/

XD8

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-5. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View)

Introduction 18 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

V

SSA2

ADCINB0 ADCREFM ADCREFP ADCRESEXT ADCREFIN

V

SSAIO

ADCLO

ADCINB1

ADCINB3

ADCINB5 ADCINB7

EMU0

ADCINA2 ADCINA1 ADCINA0 ADCINB2 ADCINB4 ADCINB6 TEST1

ADCINA5 ADCINA4

ADCINA3

V

SS1AGND

V

DDAIO

V

DD2A18

TEST2

ADCINA7 ADCINA6

V

DD1A18

V

DDA2

GPIO15/

/ /

SCIRXDB/

MFSXB

TZ4XHOLDA

GPIO16/

SPISIMOA/

CANTXB/

TZ5

GPIO17/

SPISOMIA/

CANRXB/

TZ6

V

DD

V

SS

V

SS

GPIO14/

/TZ3XHOLD/

SCITXDB/

MCLKXB

V

DD

V

SS

V

SS

P

N

M

L

K

J

H

1 2 3 4 5 6 7

V

SS2AGND

GPIO12/

TZ1/

CANTXB/

MDXB

GPIO13/

TZ2/

CANRXB/

MDRB

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-6. F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)

Submit Documentation Feedback Introduction 19

www.ti.com

ADVANCE INFORMATION

V

SS

V

SS

V

SS

V

SS

P

N

M

L

K

J

H

8 9 10 11 12 13 14

EMU1

GPIO20/

EQEP1A/

MDXA/

CANTXB

GPIO23/
EQEP1I/

MFSXA/

SCIRXDB

GPIO26/

ECAP3/
EQEP2I/
MCLKXB

GPIO33/

SCLA/

EPWMSYNCO/

ADCSOCBO

V

SS

V

SS

GPIO18/
SPICLKA/
SCITXDB/

CANRXA

GPIO21/

EQEP1B/

MDRA/

CANRXB

GPIO24/

ECAP1/

EQEP2A/

MDXB

GPIO27/

ECAP4/

EQEP2S/

MFSXB

TDI

TDO

V

DDIO

GPIO19/

/

SCIRXDB/

CANTXA

SPISTEA

GPIO22/
EQEP1S/
MCLKXA/
SCITXDB

GPIO25/

ECAP2/

EQEP2B/

MDRB

GPIO32/

SDAA/

EPWMSYNCI/

ADSOCAO

TMS

XRS

TCK

V

DD

V

DD3VFL

V

DDIO

TRST

GPIO50/

EQEP1A/

XD29

GPIO49/

ECAP6/

XD30

GPIO48/

ECAP5/

XD31

V

DD

GPIO53

EQEP1I/

XD26

GPIO52/

EQEP1S/

XD27

GPIO51/

EQEP1B/

XD28

V

DD

GPIO56/

SPICLKA/

XD23

GPIO55/

SPISOMIA/

XD24

GPIO54/

SPISIMOA/

XD25

GPIO59/

MFSRA/

XD20

GPIO58/

MCLKRA/

XD21

GPIO57/

/

XD22

SPISTEA

X2

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-7. F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View)

Introduction 20 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

G

F

E

D

C

B

A

1 2 3 4 5 6 7

GPIO9/
EPWM5B/
SCITXDB/

ECAP3

GPIO10/
EPWM6A/
CANRXB/

ADCSOCBO

GPIO11/

EPWM6B/

SCIRXDB/

ECAP4

V

DDIO

V

SS

V

SS

V

SS

V

SS

GPIO6/

EPWM4A/

EPWMSYNCI/

EPWMSYNCO

GPIO7/
EPWM4B/
MCLKRA/

ECAP2

GPIO8/

EPWM5A/

CANTXB/

ADCSOCAO

V

DD

GPIO3/

EPWM2B/

ECAP5/

MCLKRB

GPIO4/

EPWM3A

GPIO5/

EPWM3B/

MFSRA/

ECAP1

V

DDIO

GPIO0/

EPWM1A

GPIO1/

EPWM1B/

ECAP6/

MFSRB

GPIO2/

EPWM2A

V

DD

V

DD

GPIO47/

XA7

V

DDIO

GPIO29/

SCITXDA/

XA19

GPIO30/

CANRXA/

XA18

GPIO39/

XA16

GPIO85/

XA13

GPIO82/

XA10

GPIO46/

XA6

GPIO43/

XA3

V

DDIO

GPIO31/

CANTXA/

XA17

GPIO87/

XA15

GPIO84/

XA12

GPIO81/

XA9

GPIO45/

XA5

GPIO42/

XA2

V

SS

V

SS

GPIO86/

XA14

GPIO83/

XA11

GPIO80/

XA8

GPIO44/

XA4

GPIO41/

XA1

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-8. F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)

Submit Documentation Feedback Introduction 21

www.ti.com

ADVANCE INFORMATION

G

F

E

D

C

B

A

8 9 10 11 12 13 14

X1

V

SS

V

SS

V

SS

V

SS

V

DDIO

GPIO60/

MCLKRB/

XD19

XCLKIN

V

DD

GPIO63/

SCITXDC/

XD16

GPIO62/

SCIRXDC/

XD17

GPIO61/

MFSRB/

XD18

V

DD

GPIO66/

XD13

GPIO65/

XD14

GPIO64/

XD15

V

DD

V

DD

GPIO28/

SCIRXDA/

XZCS6

V

DDIO

GPIO69/

XD10

GPIO68/

XD11

GPIO67/

XD12

GPIO40/

XA0/XWE1

GPIO36/

SCIRXDA/

XZCS0

GPIO38/

XWE0

GPIO78/

XD1

GPIO75/

XD4

GPIO71/

XD8

GPIO70/

XD9

GPIO37/

ECAP2/

XZCS7

GPIO35/

SCITXDA/

XR/W

GPIO79/

XD0

GPIO77/

XD2

GPIO74/

XD5

GPIO72

XD7

V

SS

V

SS

XRD

GPIO34/

ECAP1/

XREADY

XCLKOUT

GPIO76/

XD3

GPIO73/

XD6

V

DDIO

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Figure 2-9. F28335, F28334, F28332 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View)

22 Introduction Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

2.2 Signal Descriptions

Table 2-2 describes the signals on the F2833x devices. All digital inputs are TTL-compatible. All outputs

are 3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-2. Signal Descriptions

PIN NO.

NAME DESCRIPTION

TRST 78 M10 L11

TCK 87 N12 M14 JTAG test clock with internal pullup (I, ↑ )
TMS 79 P10 M12

TDI 76 M9 N12

TDO 77 K9 N13

EMU0 85 L11 N7 (I/O/Z, 8 mA drive ↑ )

EMU1 86 P12 P8 (I/O/Z, 8 mA drive ↑ )

V

DD3VFL

TEST1 81 K10 M7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 82 P11 L7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT 138 C11 A10 and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The

XCLKIN 105 J14 G13 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω
resistor generally offers adequate protection. Since this is application-specific, it is recommended
that each target board be validated for proper operation of the debugger and the application. (I, ↓ )

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑ )

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑ )

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

FLASH

84 M11 L9 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK)

XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins,
the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
used to feed clock to X1 pin), this pin must be tied to GND. (I)

(1)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

Submit Documentation Feedback Introduction 23

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

X1 104 J13 G14 power supply. A 1.9-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

X2 102 J11 H14

XRS 80 L10 M13

ADCINA7 35 K4 K1 ADC Group A, Channel 7 input (I)
ADCINA6 36 J5 K2 ADC Group A, Channel 6 input (I)
ADCINA5 37 L1 L1 ADC Group A, Channel 5 input (I)
ADCINA4 38 L2 L2 ADC Group A, Channel 4 input (I)
ADCINA3 39 L3 L3 ADC Group A, Channel 3 input (I)
ADCINA2 40 M1 M1 ADC Group A, Channel 2 input (I)
ADCINA1 41 N1 M2 ADC Group A, Channel 1 input (I)
ADCINA0 42 M3 M3 ADC Group A, Channel 0 input (I)
ADCINB7 53 K5 N6 ADC Group B, Channel 7 input (I)
ADCINB6 52 P4 M6 ADC Group B, Channel 6 input (I)
ADCINB5 51 N4 N5 ADC Group B, Channel 5 input (I)
ADCINB4 50 M4 M5 ADC Group B, Channel 4 input (I)
ADCINB3 49 L4 N4 ADC Group B, Channel 3 input (I)
ADCINB2 48 P3 M4 ADC Group B, Channel 2 input (I)
ADCINB1 47 N3 N3 ADC Group B, Channel 1 input (I)
ADCINB0 46 P2 P3 ADC Group B, Channel 0 input (I)
ADCLO 43 M2 N2 Low Reference (connect to analog ground) (I)
ADCRESEXT 57 M5 P6 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground.
ADCREFIN 54 L5 P7 External reference input (I)

ADCREFP 56 P5 P5

ADCREFM 55 N5 P4

V

DDA2

V

SSA2

V

DDAIO

V

SSAIO

V

DD1A18

V

SS1AGND

V

DD2A18

V

SS2AGND

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1
must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSC when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑ )
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.

ADC SIGNALS

Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor
of 2.2 μ F to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor
of 2.2 μ F to analog ground. (O)

CPU AND I/O POWER PINS

34 K2 K4 ADC Analog Power Pin
33 K3 P1 ADC Analog Ground Pin
45 N2 L5 ADC Analog I/O Power Pin
44 P1 N1 ADC Analog I/O Ground Pin
31 J4 K3 ADC Analog Power Pin
32 K1 L4 ADC Analog Ground Pin
59 M6 L6 ADC Analog Power Pin
58 K6 P2 ADC Analog Ground Pin

(1)

Introduction 24 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

4 B1 D4
15 B5 D5
23 B11 D8
29 C8 D9
61 D13 E11

101 E9 F4
109 F3 F11 CPU and Logic Digital Power Pins
117 F13 H4
126 H1 J4
139 H12 J11
146 J2 K11
154 K14 L8
167 N6

9 A4 A13
71 B10 B1
93 E7 D7

107 E12 D11
121 F5 E4 Digital I/O Power Pin
143 L8 G4
159 H11 G11
170 N14 L10

N14
3 A5 A1
8 A10 A2

14 A11 A14
22 B4 B14
30 C3 F6
60 C7 F7
70 C9 F8
83 D1 F9
92 D6 G6

103 D14 G7

Digital Ground Pins

106 E8 G8
108 E14 G9
118 F4 H6
120 F12 H7
125 G1 H8
140 H10 H9
144 H13 J6
147 J3 J7
155 J10 J8
160 J12 J9

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

(1)

Submit Documentation Feedback Introduction 25

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

V

SS

V

SS

V

SS

V

SS

V

SS

GPIO0 General purpose input/output 0 (I/O/Z)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- ­GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O)
ECAP6 Enhanced Capture 6 input/output (I/O)
MFSRB McBSP-B receive frame synch (I/O)

GPIO2 General purpose input/output 2 (I/O/Z)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- ­GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O)
ECAP5 Enhanced Capture 5 input/output (I/O)
MCLKRB McBSP-B receive clock (I/O)

GPIO4 General purpose input/output 4 (I/O/Z)
EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- ­GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O)
MFSRA McBSP-A receive frame synch (I/O)
ECAP1 Enhanced Capture input/output 1 (I/O)

GPIO6 General purpose input/output 6 (I/O/Z)
EPWM4A Enhanced PWM4 output A and HRPWM channel (O)
EPWMSYNCI External ePWM sync pulse input (I)
EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z)
EPWM4B Enhanced PWM4 output B (O)
MCLKRA McBSP-A receive clock (I/O)
ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General Purpose Input/Output 8 (I/O/Z)
EPWM5A Enhanced PWM5 output A and HRPWM channel (O)
CANTXB Enhanced CAN-B transmit (O)
ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z)
EPWM5B Enhanced PWM5 output B (O)
SCITXDB SCI-B transmit data(O)
ECAP3 Enhanced capture input/output 3 (I/O)

GPIO10 General purpose input/output 10 (I/O/Z)
EPWM6A Enhanced PWM6 output A and HRPWM channel (O)
CANRXB Enhanced CAN-B receive (I)
ADCSOCBO ADC start-of-conversion B (O)

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

166 M12 P13
171 N10 P14

N11

P6
P8

5 C1 D1

6 D3 D2

7 D2 D3

10 E4 E1

11 E2 E2

12 E3 E3

13 E1 F1

16 F2 F2

17 F1 F3

18 G5 G1

19 G4 G2

Digital Ground Pins

GPIOA AND PERIPHERAL SIGNALS

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(1)

(2) (3)

(2) Some peripheral functions may not be available in all devices. See Table 2-1 for details.
(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.

(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

Introduction 26 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

GPIO11 General purpose input/output 11 (I/O/Z)
EPWM6B Enhanced PWM6 output B (O)
SCIRXDB SCI-B receive data (I)

20 G2 G3

(4)

ECAP4 Enhanced CAP Input/Output 4 (I/O)
GPIO12 General purpose input/output 12 (I/O/Z)

TZ1 Trip Zone input 1 (I)
CANTXB Enhanced CAN-B transmit (O)

21 G3 H1

(5)

MDXB McBSP-B transmit serial data (O)
GPIO13 General purpose input/output 13 (I/O/Z)

TZ2 Trip Zone input 2 (I)
CANRXB Enhanced CAN-B receive (I)

24 H3 H2

(5)

MDRB McBSP-B receive serial data (I)
GPIO14 General purpose input/output 14 (I/O/Z)

(5)

Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface
(XINTF) to release the external bus and place all buses and strobes into a high-impedance state.
To prevent this from happening when TZ3 signal goes active, disable this function by writing

TZ3/ XHOLD XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3

25 H2 H3

goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the
code. The XINTF will release the bus when any current access is complete and there are no
pending accesses on the XINTF. (I)

SCITXDB SCI-B Transmit (I)
MCLKXB McBSP-B transmit clock (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

(5)

Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the
direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is

TZ4/ XHOLDA

26 H4 J1 active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals

chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven
will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released.

External devices should only drive the external bus when XHOLDA is active (low). (I/0)

SCIRXDB SCI-B receive (I)
MFSXB McBSP-B transmit frame synch (I/O)

GPIO16 General purpose input/output 16 (I/O/Z)
SPISIMOA SPI slave in, master out (I/O)
CANTXB Enhanced CAN-B transmit (O)

27 H5 J2

(5)

TZ5 Trip Zone input 5 (I)
GPIO17 General purpose input/output 17 (I/O/Z)

SPISOMIA SPI-A slave out, master in (I/O)
CANRXB Enhanced CAN-B receive (I)

28 J1 J3

(5)

TZ6 Trip zone input 6 (I)
GPIO18 General purpose input/output 18 (I/O/Z)

SPICLKA SPI-A clock input/output (I/O)
SCITXDB SCI-B transmit (O)

62 L6 N8

(5)

CANRXA Enhanced CAN-A receive (I)
GPIO19 General purpose input/output 19 (I/O/Z)

SPISTEA SPI-A slave transmit enable input/output (I/O)
SCIRXDB SCI-B receive (I)

63 K7 M8

(5)

CANTXA Enhanced CAN-A transmit (O)
GPIO20 General purpose input/output 20 (I/O/Z)

EQEP1A Enhanced QEP1 input A (I)
MDXA McBSP-A transmit serial data (O)

64 L7 P9

(5)

CANTXB Enhanced CAN-B transmit (O)
GPIO21 General purpose input/output 21 (I/O/Z)

EQEP1B Enhanced QEP1 input B (I)
MDRA McBSP-A receive serial data (I)

65 P7 N9

(5)

CANRXB Enhanced CAN-B receive (I)

(1)

(5) The pullups on GPIO12-GPIO34 are enabled upon reset.

Submit Documentation Feedback Introduction 27

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO22 General purpose input/output 22 (I/O/Z)
EQEP1S Enhanced QEP1 strobe (I/O)
MCLKXA McBSP-A transmit clock (I/O)
SCITXDB SCI-B transmit (O)

GPIO23 General purpose input/output 23 (I/O/Z)
EQEP1I Enhanced QEP1 index (I/O)
MFSXA McBSP-A transmit frame synch (I/O)
SCIRXDB SCI-B receive (I)

GPIO24 General purpose input/output 24 (I/O/Z)
ECAP1 Enhanced capture 1 (I/O)
EQEP2A Enhanced QEP2 input A (I)
MDXB McBSP-B transmit serial data (O)

GPIO25 General purpose input/output 25 (I/O/Z)
ECAP2 Enhanced capture 2 (I/O)
EQEP2B Enhanced QEP2 input B (I)
MDRB McBSP-B receive serial data (I)

GPIO26 General purpose input/output 26 (I/O/Z)
ECAP3 Enhanced capture 3 (I/O)
EQEP2I Enhanced QEP2 index (I/O)
MCLKXB McBSP-B transmit clock (I/O)

GPIO27 General purpose input/output 27 (I/O/Z)
ECAP4 Enhanced capture 4 (I/O)
EQEP2S Enhanced QEP2 strobe (I/O)
MFSXB McBSP-B transmit frame synch (I/O)

GPIO28 General purpose input/output 28 (I/O/Z)
SCIRXDA 141 E10 D10 SCI receive data (I)
XZCS6 External Interface zone 6 chip select (O)

GPIO29 General purpose input/output 29. (I/O/Z)
SCITXDA 2 C2 C1 SCI transmit data (O)
XA19 External Interface Address Line 19 (O)

GPIO30 General purpose input/output 30 (I/O/Z)
CANRXA 1 B2 C2 Enhanced CAN-A receive (I)
XA18 External Interface Address Line 18 (O)

GPIO31 General purpose input/output 31 (I/O/Z)
CANTXA 176 A2 B2 Enhanced CAN-A transmit (O)
XA17 External Interface Address Line 17 (O)

GPIO32 General purpose input/output 32 (I/O/Z)
SDAA I2C data open-drain bidirectional port (I/OD)
EPWMSYNCI Enhanced PWM external sync pulse input (I)
ADCSOCAO ADC start-of-conversion A (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z)
SCLA I2C clock open-drain bidirectional port (I/OD)
EPWMSYNCO Enhanced PWM external synch pulse output (O)
ADCSOCBO ADC start-of-conversion B (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z)
ECAP1 142 D10 A9 Enhanced Capture input/output 1 (I/O)
XREADY External Interface Ready signal

GPIO35 General-Purpose Input/Output 35 (I/O/Z)
SCITXDA 148 A9 B9 SCI-A transmit data (O)
XR/ W External Interface read, not write strobe

GPIO36 General-Purpose Input/Output 36 (I/O/Z)
SCIRXDA 145 C10 C9 SCI receive data (I)
XZCS0 External Interface zone 0 chip select (O)

GPIO37 General-Purpose Input/Output 37 (I/O/Z)
ECAP2 150 D9 B8 Enhanced Capture input/output 2 (I/O)
XZCS7 External Interface zone 7 chip select (O)

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

66 N7 M9

67 M7 P10

68 M8 N10

69 N8 M10

72 K8 P11

73 L9 N11

74 N9 M11

75 P9 P12

(1)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

Introduction 28 Submit Documentation Feedback

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO38 General-Purpose Input/Output 38 (I/O/Z)

- 137 D11 C10 ­XWE0 External Interface Write Enable 0 (O)

GPIO39 General-Purpose Input/Output 39 (I/O/Z)

- 175 B3 C3 ­XA16 External Interface Address Line 16 (O)

GPIO40 General-Purpose Input/Output 40 (I/O/Z)

- 151 D8 C8 ­XA0/ XWE1 External Interface Address Line 0/External Interface Write Enable 1 (O)

GPIO41 General-Purpose Input/Output 41 (I/O/Z)

- 152 A8 A7 ­XA1 External Interface Address Line 1 (O)

GPIO42 General-Purpose Input/Output 42 (I/O/Z)

- 153 B8 B7 ­XA2 External Interface Address Line 2 (O)

GPIO43 General-Purpose Input/Output 43 (I/O/Z)

- 156 B7 C7 ­XA3 External Interface Address Line 3 (O)

GPIO44 General-Purpose Input/Output 44 (I/O/Z)

- 157 A7 A6 ­XA4 External Interface Address Line 4 (O)

GPIO45 General-Purpose Input/Output 45 (I/O/Z)

- 158 D7 B6 ­XA5 External Interface Address Line 5 (O)

GPIO46 General-Purpose Input/Output 46 (I/O/Z)

- 161 B6 C6 ­XA6 External Interface Address Line 6 (O)

GPIO47 General-Purpose Input/Output 47 (I/O/Z)

- 162 A6 D6 ­XA7 External Interface Address Line 7 (O)

GPIO48 General-Purpose Input/Output 48 (I/O/Z)
ECAP5 88 P13 L14 Enhanced Capture input/output 5 (I/O)
XD31 External Interface Data Line 31 (O)

GPIO49 General-Purpose Input/Output 49 (I/O/Z)
ECAP6 89 N13 L13 Enhanced Capture input/output 6 (I/O)
XD30 External Interface Data Line 30 (O)

GPIO50 General-Purpose Input/Output 50 (I/O/Z)
EQEP1A 90 P14 L12 Enhanced QEP 1input A (I)
XD29 External Interface Data Line 29 (O)

GPIO51 General-Purpose Input/Output 51 (I/O/Z)
EQEP1B 91 M13 K14 Enhanced QEP 1input B (I)
XD28 External Interface Data Line 28 (O)

GPIO52 General-Purpose Input/Output 52 (I/O/Z)
EQEP1S 94 M14 K13 Enhanced QEP 1Strobe (I/O)
XD27 External Interface Data Line 27 (O)

GPIO53 General-Purpose Input/Output 53 (I/O/Z)
EQEP1I 95 L12 K12 Enhanced CAP1 lndex (I/O)
XD26 External Interface Data Line 26 (O)

GPIO54 General-Purpose Input/Output 54 (I/O/Z)
SPISIMOA 96 L13 J14 SPI-A slave in, master out (I/O)
XD25 External Interface Data Line 25 (O)

GPIO55 General-Purpose Input/Output 55 (I/O/Z)
SPISOMIA 97 L14 J13 SPI-A slave out, master in (I/O)
XD24 External Interface Data Line 24 (O)

GPIO56 General-Purpose Input/Output 56 (I/O/Z)
SPICLKA 98 K11 J12 SPI-A clock (I/O)
XD23 External Interface Data Line 23 (O)

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

(1)

Submit Documentation Feedback Introduction 29

www.ti.com

ADVANCE INFORMATION

TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)

SPRS439B – JUNE 2007 – REVISED OCTOBER 2007

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO57 General-Purpose Input/Output 57 (I/O/Z)
SPISTEA 99 K13 H13 SPI-A slave transmit enable (I/O)
XD22 External Interface Data Line 22 (O)

GPIO58 General-Purpose Input/Output 58 (I/O/Z)
MCLKRA 100 K12 H12 McBSP-A receive clock (I/O)
XD21 External Interface Data Line 21 (O)

GPIO59 General-Purpose Input/Output 59 (I/O/Z)
MFSRA 110 H14 H11 McBSP-A receive frame synch (I/O)
XD20 External Interface Data Line 20 (O)

GPIO60 General-Purpose Input/Output 60 (I/O/Z)
MCLKRB 111 G14 G12 McBSP-B receive clock (I/O)
XD19 External Interface Data Line 19 (O)

GPIO61 General-Purpose Input/Output 61 (I/O/Z)
MFSRB 112 G12 F14 McBSP-B receive frame synch (I/O)
XD18 External Interface Data Line 18 (O)

GPIO62 General-Purpose Input/Output 62 (I/O/Z)
SCIRXDC 113 G13 F13 SCI-C receive data (I)
XD17 External Interface Data Line 17 (O)

GPIO63 General-Purpose Input/Output 63 (I/O/Z)
SCITXDC 114 G11 F12 SCI-C transmit data (O)
XD16 External Interface Data Line 16 (O)

GPIO64 General-Purpose Input/Output 64 (I/O/Z)

- 115 G10 E14 ­XD15 External Interface Data Line 15 (O)

GPIO65 General-Purpose Input/Output 65 (I/O/Z)

- 116 F14 E13 ­XD14 External Interface Data Line 14 (O)

GPIO66 General-Purpose Input/Output 66 (I/O/Z)

- 119 F11 E12 ­XD13 External Interface Data Line 13 (O)

GPIO67 General-Purpose Input/Output 67 (I/O/Z)

- 122 E13 D14 ­XD12 External Interface Data Line 12 (O)

GPIO68 General-Purpose Input/Output 68 (I/O/Z)

- 123 E11 D13 ­XD11 External Interface Data Line 11 (O)

GPIO69 General-Purpose Input/Output 69 (I/O/Z)

- 124 F10 D12 ­XD10 External Interface Data Line 10 (O)

GPIO70 General-Purpose Input/Output 70 (I/O/Z)

- 127 D12 C14 ­XD9 External Interface Data Line 9 (O)

GPIO71 General-Purpose Input/Output 71 (I/O/Z)

- 128 C14 C13 ­XD8 External Interface Data Line 8 (O)

GPIO72 General-Purpose Input/Output 72 (I/O/Z)

- 129 B14 B13 ­XD7 External Interface Data Line 7 (O)

GPIO73 General-Purpose Input/Output 73 (I/O/Z)

- 130 C12 A12 ­XD6 External Interface Data Line 6 (O)

GPIO74 General-Purpose Input/Output 74 (I/O/Z)

- 131 C13 B12 ­XD5 External Interface Data Line 5 (O)

GPIO75 General-Purpose Input/Output 75 (I/O/Z)

- 132 A14 C12 ­XD4 External Interface Data Line 4 (O)

PGF ZHH ZJZ

PIN BAL BAL

# L # L #

(1)

Introduction 30 Submit Documentation Feedback